19536dfccSTor Krill /*
29536dfccSTor Krill * (C) Copyright 2008
39536dfccSTor Krill * Tor Krill, Excito Elektronik i Skåne , tor@excito.com
49536dfccSTor Krill *
59536dfccSTor Krill * Modelled after the ds1337 driver
69536dfccSTor Krill *
7*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
89536dfccSTor Krill */
99536dfccSTor Krill
109536dfccSTor Krill /*
119536dfccSTor Krill * Date & Time support (no alarms) for Intersil
129536dfccSTor Krill * ISL1208 Real Time Clock (RTC).
139536dfccSTor Krill */
149536dfccSTor Krill
159536dfccSTor Krill #include <common.h>
169536dfccSTor Krill #include <command.h>
179536dfccSTor Krill #include <rtc.h>
189536dfccSTor Krill #include <i2c.h>
199536dfccSTor Krill
209536dfccSTor Krill /*---------------------------------------------------------------------*/
219536dfccSTor Krill #ifdef DEBUG_RTC
229536dfccSTor Krill #define DEBUGR(fmt,args...) printf(fmt ,##args)
239536dfccSTor Krill #else
249536dfccSTor Krill #define DEBUGR(fmt,args...)
259536dfccSTor Krill #endif
269536dfccSTor Krill /*---------------------------------------------------------------------*/
279536dfccSTor Krill
289536dfccSTor Krill /*
299536dfccSTor Krill * RTC register addresses
309536dfccSTor Krill */
319536dfccSTor Krill
329536dfccSTor Krill #define RTC_SEC_REG_ADDR 0x0
339536dfccSTor Krill #define RTC_MIN_REG_ADDR 0x1
349536dfccSTor Krill #define RTC_HR_REG_ADDR 0x2
359536dfccSTor Krill #define RTC_DATE_REG_ADDR 0x3
369536dfccSTor Krill #define RTC_MON_REG_ADDR 0x4
379536dfccSTor Krill #define RTC_YR_REG_ADDR 0x5
389536dfccSTor Krill #define RTC_DAY_REG_ADDR 0x6
399536dfccSTor Krill #define RTC_STAT_REG_ADDR 0x7
409536dfccSTor Krill /*
419536dfccSTor Krill * RTC control register bits
429536dfccSTor Krill */
439536dfccSTor Krill
449536dfccSTor Krill /*
459536dfccSTor Krill * RTC status register bits
469536dfccSTor Krill */
479536dfccSTor Krill #define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */
489536dfccSTor Krill #define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */
499536dfccSTor Krill #define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */
509536dfccSTor Krill #define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */
519536dfccSTor Krill #define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
529536dfccSTor Krill #define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
539536dfccSTor Krill
549536dfccSTor Krill static uchar rtc_read (uchar reg);
559536dfccSTor Krill static void rtc_write (uchar reg, uchar val);
569536dfccSTor Krill
579536dfccSTor Krill /*
589536dfccSTor Krill * Get the current time from the RTC
599536dfccSTor Krill */
609536dfccSTor Krill
rtc_get(struct rtc_time * tmp)61b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp)
629536dfccSTor Krill {
63b73a19e1SYuri Tikhonov int rel = 0;
649536dfccSTor Krill uchar sec, min, hour, mday, wday, mon, year, status;
659536dfccSTor Krill
669536dfccSTor Krill status = rtc_read (RTC_STAT_REG_ADDR);
679536dfccSTor Krill sec = rtc_read (RTC_SEC_REG_ADDR);
689536dfccSTor Krill min = rtc_read (RTC_MIN_REG_ADDR);
699536dfccSTor Krill hour = rtc_read (RTC_HR_REG_ADDR);
709536dfccSTor Krill wday = rtc_read (RTC_DAY_REG_ADDR);
719536dfccSTor Krill mday = rtc_read (RTC_DATE_REG_ADDR);
729536dfccSTor Krill mon = rtc_read (RTC_MON_REG_ADDR);
739536dfccSTor Krill year = rtc_read (RTC_YR_REG_ADDR);
749536dfccSTor Krill
759536dfccSTor Krill DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
769536dfccSTor Krill "hr: %02x min: %02x sec: %02x status: %02x\n",
779536dfccSTor Krill year, mon, mday, wday, hour, min, sec, status);
789536dfccSTor Krill
799536dfccSTor Krill if (status & RTC_STAT_BIT_RTCF) {
809536dfccSTor Krill printf ("### Warning: RTC oscillator has stopped\n");
819536dfccSTor Krill rtc_write(RTC_STAT_REG_ADDR,
829536dfccSTor Krill rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF));
83b73a19e1SYuri Tikhonov rel = -1;
849536dfccSTor Krill }
859536dfccSTor Krill
869536dfccSTor Krill tmp->tm_sec = bcd2bin (sec & 0x7F);
879536dfccSTor Krill tmp->tm_min = bcd2bin (min & 0x7F);
889536dfccSTor Krill tmp->tm_hour = bcd2bin (hour & 0x3F);
899536dfccSTor Krill tmp->tm_mday = bcd2bin (mday & 0x3F);
909536dfccSTor Krill tmp->tm_mon = bcd2bin (mon & 0x1F);
919536dfccSTor Krill tmp->tm_year = bcd2bin (year)+2000;
929536dfccSTor Krill tmp->tm_wday = bcd2bin (wday & 0x07);
939536dfccSTor Krill tmp->tm_yday = 0;
949536dfccSTor Krill tmp->tm_isdst= 0;
959536dfccSTor Krill
969536dfccSTor Krill DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
979536dfccSTor Krill tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
989536dfccSTor Krill tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
99b73a19e1SYuri Tikhonov
100b73a19e1SYuri Tikhonov return rel;
1019536dfccSTor Krill }
1029536dfccSTor Krill
1039536dfccSTor Krill /*
1049536dfccSTor Krill * Set the RTC
1059536dfccSTor Krill */
rtc_set(struct rtc_time * tmp)106d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp)
1079536dfccSTor Krill {
1089536dfccSTor Krill DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
1099536dfccSTor Krill tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1109536dfccSTor Krill tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
1119536dfccSTor Krill
1129536dfccSTor Krill /* enable write */
1139536dfccSTor Krill rtc_write(RTC_STAT_REG_ADDR,
1149536dfccSTor Krill rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC);
1159536dfccSTor Krill
1169536dfccSTor Krill rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
1179536dfccSTor Krill rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
1189536dfccSTor Krill rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
1199536dfccSTor Krill rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
1209536dfccSTor Krill rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */
1219536dfccSTor Krill rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
1229536dfccSTor Krill rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
1239536dfccSTor Krill
1249536dfccSTor Krill /* disable write */
1259536dfccSTor Krill rtc_write(RTC_STAT_REG_ADDR,
1269536dfccSTor Krill rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC);
127d1e23194SJean-Christophe PLAGNIOL-VILLARD
128d1e23194SJean-Christophe PLAGNIOL-VILLARD return 0;
1299536dfccSTor Krill }
1309536dfccSTor Krill
rtc_reset(void)1319536dfccSTor Krill void rtc_reset (void)
1329536dfccSTor Krill {
1339536dfccSTor Krill }
1349536dfccSTor Krill
1359536dfccSTor Krill /*
1369536dfccSTor Krill * Helper functions
1379536dfccSTor Krill */
1389536dfccSTor Krill
rtc_read(uchar reg)1399536dfccSTor Krill static uchar rtc_read (uchar reg)
1409536dfccSTor Krill {
1416d0f6bcfSJean-Christophe PLAGNIOL-VILLARD return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
1429536dfccSTor Krill }
1439536dfccSTor Krill
rtc_write(uchar reg,uchar val)1449536dfccSTor Krill static void rtc_write (uchar reg, uchar val)
1459536dfccSTor Krill {
1466d0f6bcfSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
1479536dfccSTor Krill }
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