10c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
20c698dcaSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2006
30c698dcaSJean-Christophe PLAGNIOL-VILLARD * Markus Klotzbuecher, mk@denx.de
40c698dcaSJean-Christophe PLAGNIOL-VILLARD *
51a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
60c698dcaSJean-Christophe PLAGNIOL-VILLARD */
70c698dcaSJean-Christophe PLAGNIOL-VILLARD
80c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
90c698dcaSJean-Christophe PLAGNIOL-VILLARD * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
100c698dcaSJean-Christophe PLAGNIOL-VILLARD * Extremly Accurate DS3231 Real Time Clock (RTC).
110c698dcaSJean-Christophe PLAGNIOL-VILLARD *
120c698dcaSJean-Christophe PLAGNIOL-VILLARD * copied from ds1337.c
130c698dcaSJean-Christophe PLAGNIOL-VILLARD */
140c698dcaSJean-Christophe PLAGNIOL-VILLARD
150c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
160c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <command.h>
170c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <rtc.h>
180c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <i2c.h>
190c698dcaSJean-Christophe PLAGNIOL-VILLARD
20871c18ddSMichal Simek #if defined(CONFIG_CMD_DATE)
210c698dcaSJean-Christophe PLAGNIOL-VILLARD
220c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
230c698dcaSJean-Christophe PLAGNIOL-VILLARD * RTC register addresses
240c698dcaSJean-Christophe PLAGNIOL-VILLARD */
250c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SEC_REG_ADDR 0x0
260c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_MIN_REG_ADDR 0x1
270c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_HR_REG_ADDR 0x2
280c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_DAY_REG_ADDR 0x3
290c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_DATE_REG_ADDR 0x4
300c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_MON_REG_ADDR 0x5
310c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_YR_REG_ADDR 0x6
320c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_REG_ADDR 0x0e
330c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_STAT_REG_ADDR 0x0f
340c698dcaSJean-Christophe PLAGNIOL-VILLARD
350c698dcaSJean-Christophe PLAGNIOL-VILLARD
360c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
370c698dcaSJean-Christophe PLAGNIOL-VILLARD * RTC control register bits
380c698dcaSJean-Christophe PLAGNIOL-VILLARD */
390c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
400c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
410c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
420c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
430c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
440c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
450c698dcaSJean-Christophe PLAGNIOL-VILLARD
460c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
470c698dcaSJean-Christophe PLAGNIOL-VILLARD * RTC status register bits
480c698dcaSJean-Christophe PLAGNIOL-VILLARD */
490c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
500c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
510c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
52*c340941eSPriyanka Jain #define RTC_STAT_BIT_BB32KHZ 0x40 /* Battery backed 32KHz Output */
53*c340941eSPriyanka Jain #define RTC_STAT_BIT_EN32KHZ 0x8 /* Enable 32KHz Output */
540c698dcaSJean-Christophe PLAGNIOL-VILLARD
550c698dcaSJean-Christophe PLAGNIOL-VILLARD
560c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg);
570c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val);
580c698dcaSJean-Christophe PLAGNIOL-VILLARD
590c698dcaSJean-Christophe PLAGNIOL-VILLARD
600c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
610c698dcaSJean-Christophe PLAGNIOL-VILLARD * Get the current time from the RTC
620c698dcaSJean-Christophe PLAGNIOL-VILLARD */
rtc_get(struct rtc_time * tmp)63b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp)
640c698dcaSJean-Christophe PLAGNIOL-VILLARD {
65b73a19e1SYuri Tikhonov int rel = 0;
660c698dcaSJean-Christophe PLAGNIOL-VILLARD uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
670c698dcaSJean-Christophe PLAGNIOL-VILLARD
680c698dcaSJean-Christophe PLAGNIOL-VILLARD control = rtc_read (RTC_CTL_REG_ADDR);
690c698dcaSJean-Christophe PLAGNIOL-VILLARD status = rtc_read (RTC_STAT_REG_ADDR);
700c698dcaSJean-Christophe PLAGNIOL-VILLARD sec = rtc_read (RTC_SEC_REG_ADDR);
710c698dcaSJean-Christophe PLAGNIOL-VILLARD min = rtc_read (RTC_MIN_REG_ADDR);
720c698dcaSJean-Christophe PLAGNIOL-VILLARD hour = rtc_read (RTC_HR_REG_ADDR);
730c698dcaSJean-Christophe PLAGNIOL-VILLARD wday = rtc_read (RTC_DAY_REG_ADDR);
740c698dcaSJean-Christophe PLAGNIOL-VILLARD mday = rtc_read (RTC_DATE_REG_ADDR);
750c698dcaSJean-Christophe PLAGNIOL-VILLARD mon_cent = rtc_read (RTC_MON_REG_ADDR);
760c698dcaSJean-Christophe PLAGNIOL-VILLARD year = rtc_read (RTC_YR_REG_ADDR);
770c698dcaSJean-Christophe PLAGNIOL-VILLARD
78397b40caSWolfgang Denk debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
790c698dcaSJean-Christophe PLAGNIOL-VILLARD "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
800c698dcaSJean-Christophe PLAGNIOL-VILLARD year, mon_cent, mday, wday, hour, min, sec, control, status);
810c698dcaSJean-Christophe PLAGNIOL-VILLARD
820c698dcaSJean-Christophe PLAGNIOL-VILLARD if (status & RTC_STAT_BIT_OSF) {
830c698dcaSJean-Christophe PLAGNIOL-VILLARD printf ("### Warning: RTC oscillator has stopped\n");
840c698dcaSJean-Christophe PLAGNIOL-VILLARD /* clear the OSF flag */
850c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_STAT_REG_ADDR,
860c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
87b73a19e1SYuri Tikhonov rel = -1;
880c698dcaSJean-Christophe PLAGNIOL-VILLARD }
890c698dcaSJean-Christophe PLAGNIOL-VILLARD
900c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_sec = bcd2bin (sec & 0x7F);
910c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_min = bcd2bin (min & 0x7F);
920c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour = bcd2bin (hour & 0x3F);
930c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_mday = bcd2bin (mday & 0x3F);
940c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
950c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
960c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
970c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_yday = 0;
980c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_isdst= 0;
990c698dcaSJean-Christophe PLAGNIOL-VILLARD
100397b40caSWolfgang Denk debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
1010c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1020c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
103b73a19e1SYuri Tikhonov
104b73a19e1SYuri Tikhonov return rel;
1050c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1060c698dcaSJean-Christophe PLAGNIOL-VILLARD
1070c698dcaSJean-Christophe PLAGNIOL-VILLARD
1080c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
1090c698dcaSJean-Christophe PLAGNIOL-VILLARD * Set the RTC
1100c698dcaSJean-Christophe PLAGNIOL-VILLARD */
rtc_set(struct rtc_time * tmp)111d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp)
1120c698dcaSJean-Christophe PLAGNIOL-VILLARD {
1130c698dcaSJean-Christophe PLAGNIOL-VILLARD uchar century;
1140c698dcaSJean-Christophe PLAGNIOL-VILLARD
115397b40caSWolfgang Denk debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
1160c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1170c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
1180c698dcaSJean-Christophe PLAGNIOL-VILLARD
1190c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
1200c698dcaSJean-Christophe PLAGNIOL-VILLARD
1210c698dcaSJean-Christophe PLAGNIOL-VILLARD century = (tmp->tm_year >= 2000) ? 0x80 : 0;
1220c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
1230c698dcaSJean-Christophe PLAGNIOL-VILLARD
1240c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
1250c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
1260c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
1270c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
1280c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
129d1e23194SJean-Christophe PLAGNIOL-VILLARD
130d1e23194SJean-Christophe PLAGNIOL-VILLARD return 0;
1310c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1320c698dcaSJean-Christophe PLAGNIOL-VILLARD
1330c698dcaSJean-Christophe PLAGNIOL-VILLARD
1340c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
1350c698dcaSJean-Christophe PLAGNIOL-VILLARD * Reset the RTC. We also enable the oscillator output on the
1360c698dcaSJean-Christophe PLAGNIOL-VILLARD * SQW/INTB* pin and program it for 32,768 Hz output. Note that
1370c698dcaSJean-Christophe PLAGNIOL-VILLARD * according to the datasheet, turning on the square wave output
1380c698dcaSJean-Christophe PLAGNIOL-VILLARD * increases the current drain on the backup battery from about
1390c698dcaSJean-Christophe PLAGNIOL-VILLARD * 600 nA to 2uA.
1400c698dcaSJean-Christophe PLAGNIOL-VILLARD */
rtc_reset(void)1410c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void)
1420c698dcaSJean-Christophe PLAGNIOL-VILLARD {
1430c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2);
1440c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1450c698dcaSJean-Christophe PLAGNIOL-VILLARD
146*c340941eSPriyanka Jain /*
147*c340941eSPriyanka Jain * Enable 32KHz output
148*c340941eSPriyanka Jain */
rtc_enable_32khz_output(void)149*c340941eSPriyanka Jain void rtc_enable_32khz_output(void)
150*c340941eSPriyanka Jain {
151*c340941eSPriyanka Jain rtc_write(RTC_STAT_REG_ADDR,
152*c340941eSPriyanka Jain RTC_STAT_BIT_BB32KHZ | RTC_STAT_BIT_EN32KHZ);
153*c340941eSPriyanka Jain }
1540c698dcaSJean-Christophe PLAGNIOL-VILLARD
1550c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
1560c698dcaSJean-Christophe PLAGNIOL-VILLARD * Helper functions
1570c698dcaSJean-Christophe PLAGNIOL-VILLARD */
1580c698dcaSJean-Christophe PLAGNIOL-VILLARD
1590c698dcaSJean-Christophe PLAGNIOL-VILLARD static
rtc_read(uchar reg)1600c698dcaSJean-Christophe PLAGNIOL-VILLARD uchar rtc_read (uchar reg)
1610c698dcaSJean-Christophe PLAGNIOL-VILLARD {
1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
1630c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1640c698dcaSJean-Christophe PLAGNIOL-VILLARD
1650c698dcaSJean-Christophe PLAGNIOL-VILLARD
rtc_write(uchar reg,uchar val)1660c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val)
1670c698dcaSJean-Christophe PLAGNIOL-VILLARD {
1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
1690c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1700c698dcaSJean-Christophe PLAGNIOL-VILLARD
1710c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif
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