10c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
20c698dcaSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2001, 2002, 2003
30c698dcaSJean-Christophe PLAGNIOL-VILLARD * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
40c698dcaSJean-Christophe PLAGNIOL-VILLARD * Keith Outwater, keith_outwater@mvis.com`
50c698dcaSJean-Christophe PLAGNIOL-VILLARD * Steven Scholz, steven.scholz@imc-berlin.de
60c698dcaSJean-Christophe PLAGNIOL-VILLARD *
71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+
80c698dcaSJean-Christophe PLAGNIOL-VILLARD */
90c698dcaSJean-Christophe PLAGNIOL-VILLARD
100c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
110c698dcaSJean-Christophe PLAGNIOL-VILLARD * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
120c698dcaSJean-Christophe PLAGNIOL-VILLARD * DS1374 Real Time Clock (RTC).
130c698dcaSJean-Christophe PLAGNIOL-VILLARD *
140c698dcaSJean-Christophe PLAGNIOL-VILLARD * based on ds1337.c
150c698dcaSJean-Christophe PLAGNIOL-VILLARD */
160c698dcaSJean-Christophe PLAGNIOL-VILLARD
170c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <common.h>
180c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <command.h>
190c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <rtc.h>
200c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <i2c.h>
210c698dcaSJean-Christophe PLAGNIOL-VILLARD
22871c18ddSMichal Simek #if defined(CONFIG_CMD_DATE)
230c698dcaSJean-Christophe PLAGNIOL-VILLARD
240c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/
250c698dcaSJean-Christophe PLAGNIOL-VILLARD #undef DEBUG_RTC
260c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUG_RTC
270c698dcaSJean-Christophe PLAGNIOL-VILLARD
280c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG_RTC
290c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...) printf(fmt ,##args)
300c698dcaSJean-Christophe PLAGNIOL-VILLARD #else
310c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...)
320c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif
330c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/
340c698dcaSJean-Christophe PLAGNIOL-VILLARD
356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_I2C_RTC_ADDR
366d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_I2C_RTC_ADDR 0x68
370c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif
380c698dcaSJean-Christophe PLAGNIOL-VILLARD
396d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_RTC_DS1374) && (CONFIG_SYS_I2C_SPEED > 400000)
400c698dcaSJean-Christophe PLAGNIOL-VILLARD # error The DS1374 is specified up to 400kHz in fast mode!
410c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif
420c698dcaSJean-Christophe PLAGNIOL-VILLARD
430c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
440c698dcaSJean-Christophe PLAGNIOL-VILLARD * RTC register addresses
450c698dcaSJean-Christophe PLAGNIOL-VILLARD */
460c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE0_ADDR 0x00 /* TimeOfDay */
470c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE1_ADDR 0x01
480c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE2_ADDR 0x02
490c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TOD_CNT_BYTE3_ADDR 0x03
500c698dcaSJean-Christophe PLAGNIOL-VILLARD
510c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE0_ADDR 0x04
520c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE1_ADDR 0x05
530c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_WD_ALM_CNT_BYTE2_ADDR 0x06
540c698dcaSJean-Christophe PLAGNIOL-VILLARD
550c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_ADDR 0x07 /* RTC-CoNTrol-register */
560c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_ADDR 0x08 /* RTC-StatusRegister */
570c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_TCS_DS_ADDR 0x09 /* RTC-TrickleChargeSelect DiodeSelect-register */
580c698dcaSJean-Christophe PLAGNIOL-VILLARD
590c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_AIE (1<<0) /* Bit 0 - Alarm Interrupt enable */
600c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS1 (1<<1) /* Bit 1/2 - Rate Select square wave output */
610c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS2 (1<<2) /* Bit 2/2 - Rate Select square wave output */
620c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WDSTR (1<<3) /* Bit 3 - Watchdog Reset Steering */
630c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_BBSQW (1<<4) /* Bit 4 - Battery-Backed Square-Wave */
640c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WD_ALM (1<<5) /* Bit 5 - Watchdoc/Alarm Counter Select */
650c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_WACE (1<<6) /* Bit 6 - Watchdog/Alarm Counter Enable WACE*/
660c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_EN_OSC (1<<7) /* Bit 7 - Enable Oscilator */
670c698dcaSJean-Christophe PLAGNIOL-VILLARD
680c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_BIT_AF 0x01 /* Bit 0 = Alarm Flag */
690c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SR_BIT_OSF 0x80 /* Bit 7 - Osc Stop Flag */
700c698dcaSJean-Christophe PLAGNIOL-VILLARD
710c698dcaSJean-Christophe PLAGNIOL-VILLARD const char RtcTodAddr[] = {
720c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE0_ADDR,
730c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE1_ADDR,
740c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE2_ADDR,
750c698dcaSJean-Christophe PLAGNIOL-VILLARD RTC_TOD_CNT_BYTE3_ADDR
760c698dcaSJean-Christophe PLAGNIOL-VILLARD };
770c698dcaSJean-Christophe PLAGNIOL-VILLARD
780c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg);
79472d5460SYork Sun static void rtc_write(uchar reg, uchar val, bool set);
800c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write_raw (uchar reg, uchar val);
810c698dcaSJean-Christophe PLAGNIOL-VILLARD
820c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
830c698dcaSJean-Christophe PLAGNIOL-VILLARD * Get the current time from the RTC
840c698dcaSJean-Christophe PLAGNIOL-VILLARD */
rtc_get(struct rtc_time * tm)85b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tm){
86b73a19e1SYuri Tikhonov int rel = 0;
870c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned long time1, time2;
880c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned int limit;
890c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned char tmp;
900c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned int i;
910c698dcaSJean-Christophe PLAGNIOL-VILLARD
920c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
930c698dcaSJean-Christophe PLAGNIOL-VILLARD * Since the reads are being performed one byte at a time,
940c698dcaSJean-Christophe PLAGNIOL-VILLARD * there is a chance that a carry will occur during the read.
950c698dcaSJean-Christophe PLAGNIOL-VILLARD * To detect this, 2 reads are performed and compared.
960c698dcaSJean-Christophe PLAGNIOL-VILLARD */
970c698dcaSJean-Christophe PLAGNIOL-VILLARD limit = 10;
980c698dcaSJean-Christophe PLAGNIOL-VILLARD do {
990c698dcaSJean-Christophe PLAGNIOL-VILLARD i = 4;
1000c698dcaSJean-Christophe PLAGNIOL-VILLARD time1 = 0;
1010c698dcaSJean-Christophe PLAGNIOL-VILLARD while (i--) {
1020c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp = rtc_read(RtcTodAddr[i]);
1030c698dcaSJean-Christophe PLAGNIOL-VILLARD time1 = (time1 << 8) | (tmp & 0xff);
1040c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1050c698dcaSJean-Christophe PLAGNIOL-VILLARD
1060c698dcaSJean-Christophe PLAGNIOL-VILLARD i = 4;
1070c698dcaSJean-Christophe PLAGNIOL-VILLARD time2 = 0;
1080c698dcaSJean-Christophe PLAGNIOL-VILLARD while (i--) {
1090c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp = rtc_read(RtcTodAddr[i]);
1100c698dcaSJean-Christophe PLAGNIOL-VILLARD time2 = (time2 << 8) | (tmp & 0xff);
1110c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1120c698dcaSJean-Christophe PLAGNIOL-VILLARD } while ((time1 != time2) && limit--);
1130c698dcaSJean-Christophe PLAGNIOL-VILLARD
1140c698dcaSJean-Christophe PLAGNIOL-VILLARD if (time1 != time2) {
1150c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("can't get consistent time from rtc chip\n");
116b73a19e1SYuri Tikhonov rel = -1;
1170c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1180c698dcaSJean-Christophe PLAGNIOL-VILLARD
1194109df6fSKim Phillips DEBUGR ("Get RTC s since 1.1.1970: %ld\n", time1);
1200c698dcaSJean-Christophe PLAGNIOL-VILLARD
1219f9276c3SSimon Glass rtc_to_tm(time1, tm); /* To Gregorian Date */
1220c698dcaSJean-Christophe PLAGNIOL-VILLARD
123b73a19e1SYuri Tikhonov if (rtc_read(RTC_SR_ADDR) & RTC_SR_BIT_OSF) {
1240c698dcaSJean-Christophe PLAGNIOL-VILLARD printf ("### Warning: RTC oscillator has stopped\n");
125b73a19e1SYuri Tikhonov rel = -1;
126b73a19e1SYuri Tikhonov }
1270c698dcaSJean-Christophe PLAGNIOL-VILLARD
1280c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
1290c698dcaSJean-Christophe PLAGNIOL-VILLARD tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
1300c698dcaSJean-Christophe PLAGNIOL-VILLARD tm->tm_hour, tm->tm_min, tm->tm_sec);
131b73a19e1SYuri Tikhonov
132b73a19e1SYuri Tikhonov return rel;
1330c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1340c698dcaSJean-Christophe PLAGNIOL-VILLARD
1350c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
1360c698dcaSJean-Christophe PLAGNIOL-VILLARD * Set the RTC
1370c698dcaSJean-Christophe PLAGNIOL-VILLARD */
rtc_set(struct rtc_time * tmp)138d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp){
1390c698dcaSJean-Christophe PLAGNIOL-VILLARD
1400c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned long time;
1410c698dcaSJean-Christophe PLAGNIOL-VILLARD unsigned i;
1420c698dcaSJean-Christophe PLAGNIOL-VILLARD
1430c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
1440c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
1450c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
1460c698dcaSJean-Christophe PLAGNIOL-VILLARD
1470c698dcaSJean-Christophe PLAGNIOL-VILLARD if (tmp->tm_year < 1970 || tmp->tm_year > 2069)
1480c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("WARNING: year should be between 1970 and 2069!\n");
1490c698dcaSJean-Christophe PLAGNIOL-VILLARD
150*71420983SSimon Glass time = rtc_mktime(tmp);
1510c698dcaSJean-Christophe PLAGNIOL-VILLARD
1524109df6fSKim Phillips DEBUGR ("Set RTC s since 1.1.1970: %ld (0x%02lx)\n", time, time);
1530c698dcaSJean-Christophe PLAGNIOL-VILLARD
1540c698dcaSJean-Christophe PLAGNIOL-VILLARD /* write to RTC_TOD_CNT_BYTEn_ADDR */
1550c698dcaSJean-Christophe PLAGNIOL-VILLARD for (i = 0; i <= 3; i++) {
1560c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write_raw(RtcTodAddr[i], (unsigned char)(time & 0xff));
1570c698dcaSJean-Christophe PLAGNIOL-VILLARD time = time >> 8;
1580c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1590c698dcaSJean-Christophe PLAGNIOL-VILLARD
1600c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Start clock */
161472d5460SYork Sun rtc_write(RTC_CTL_ADDR, RTC_CTL_BIT_EN_OSC, false);
162d1e23194SJean-Christophe PLAGNIOL-VILLARD
163d1e23194SJean-Christophe PLAGNIOL-VILLARD return 0;
1640c698dcaSJean-Christophe PLAGNIOL-VILLARD }
1650c698dcaSJean-Christophe PLAGNIOL-VILLARD
1660c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
1670c698dcaSJean-Christophe PLAGNIOL-VILLARD * Reset the RTC. We setting the date back to 1970-01-01.
1680c698dcaSJean-Christophe PLAGNIOL-VILLARD * We also enable the oscillator output on the SQW/OUT pin and program
1690c698dcaSJean-Christophe PLAGNIOL-VILLARD * it for 32,768 Hz output. Note that according to the datasheet, turning
1700c698dcaSJean-Christophe PLAGNIOL-VILLARD * on the square wave output increases the current drain on the backup
1710c698dcaSJean-Christophe PLAGNIOL-VILLARD * battery to something between 480nA and 800nA.
1720c698dcaSJean-Christophe PLAGNIOL-VILLARD */
rtc_reset(void)1730c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void){
1740c698dcaSJean-Christophe PLAGNIOL-VILLARD
1750c698dcaSJean-Christophe PLAGNIOL-VILLARD struct rtc_time tmp;
1760c698dcaSJean-Christophe PLAGNIOL-VILLARD
1770c698dcaSJean-Christophe PLAGNIOL-VILLARD /* clear status flags */
178472d5460SYork Sun rtc_write(RTC_SR_ADDR, (RTC_SR_BIT_AF|RTC_SR_BIT_OSF), false); /* clearing OSF and AF */
1790c698dcaSJean-Christophe PLAGNIOL-VILLARD
1800c698dcaSJean-Christophe PLAGNIOL-VILLARD /* Initialise DS1374 oriented to MPC8349E-ADS */
1810c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_EN_OSC
1820c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_WACE
183472d5460SYork Sun |RTC_CTL_BIT_AIE), false);/* start osc, disable WACE, clear AIE
1840c698dcaSJean-Christophe PLAGNIOL-VILLARD - set to 0 */
1850c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_ADDR, (RTC_CTL_BIT_WD_ALM
1860c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_WDSTR
1870c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_RS1
1880c698dcaSJean-Christophe PLAGNIOL-VILLARD |RTC_CTL_BIT_RS2
189472d5460SYork Sun |RTC_CTL_BIT_BBSQW), true);/* disable WD/ALM, WDSTR set to INT-pin,
1900c698dcaSJean-Christophe PLAGNIOL-VILLARD set BBSQW and SQW to 32k
1910c698dcaSJean-Christophe PLAGNIOL-VILLARD - set to 1 */
1920c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year = 1970;
1930c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mon = 1;
1940c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mday= 1;
1950c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour = 0;
1960c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_min = 0;
1970c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_sec = 0;
1980c698dcaSJean-Christophe PLAGNIOL-VILLARD
1990c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_set(&tmp);
2000c698dcaSJean-Christophe PLAGNIOL-VILLARD
2010c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n",
2020c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
2030c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
2040c698dcaSJean-Christophe PLAGNIOL-VILLARD
205472d5460SYork Sun rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAC, true);
206472d5460SYork Sun rtc_write(RTC_WD_ALM_CNT_BYTE1_ADDR, 0xDE, true);
207472d5460SYork Sun rtc_write(RTC_WD_ALM_CNT_BYTE2_ADDR, 0xAD, true);
2080c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2090c698dcaSJean-Christophe PLAGNIOL-VILLARD
2100c698dcaSJean-Christophe PLAGNIOL-VILLARD /*
2110c698dcaSJean-Christophe PLAGNIOL-VILLARD * Helper functions
2120c698dcaSJean-Christophe PLAGNIOL-VILLARD */
rtc_read(uchar reg)2130c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg)
2140c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
2160c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2170c698dcaSJean-Christophe PLAGNIOL-VILLARD
rtc_write(uchar reg,uchar val,bool set)218472d5460SYork Sun static void rtc_write(uchar reg, uchar val, bool set)
2190c698dcaSJean-Christophe PLAGNIOL-VILLARD {
220472d5460SYork Sun if (set == true) {
2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD val |= i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg);
2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
2230c698dcaSJean-Christophe PLAGNIOL-VILLARD } else {
2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg) & ~val;
2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
2260c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2270c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2280c698dcaSJean-Christophe PLAGNIOL-VILLARD
rtc_write_raw(uchar reg,uchar val)2290c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write_raw (uchar reg, uchar val)
2300c698dcaSJean-Christophe PLAGNIOL-VILLARD {
2316d0f6bcfSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
2320c698dcaSJean-Christophe PLAGNIOL-VILLARD }
2330c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif
234