10c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 20c698dcaSJean-Christophe PLAGNIOL-VILLARD * (C) Copyright 2001, 2002, 2003 30c698dcaSJean-Christophe PLAGNIOL-VILLARD * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 40c698dcaSJean-Christophe PLAGNIOL-VILLARD * Keith Outwater, keith_outwater@mvis.com` 50c698dcaSJean-Christophe PLAGNIOL-VILLARD * Steven Scholz, steven.scholz@imc-berlin.de 60c698dcaSJean-Christophe PLAGNIOL-VILLARD * 71a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 80c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 90c698dcaSJean-Christophe PLAGNIOL-VILLARD 100c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 110c698dcaSJean-Christophe PLAGNIOL-VILLARD * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim) 12412921d2SMarkus Niebel * DS1307 and DS1338/9 Real Time Clock (RTC). 130c698dcaSJean-Christophe PLAGNIOL-VILLARD * 140c698dcaSJean-Christophe PLAGNIOL-VILLARD * based on ds1337.c 150c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 160c698dcaSJean-Christophe PLAGNIOL-VILLARD 170c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <common.h> 180c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <command.h> 190c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <rtc.h> 200c698dcaSJean-Christophe PLAGNIOL-VILLARD #include <i2c.h> 210c698dcaSJean-Christophe PLAGNIOL-VILLARD 22871c18ddSMichal Simek #if defined(CONFIG_CMD_DATE) 230c698dcaSJean-Christophe PLAGNIOL-VILLARD 240c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/ 250c698dcaSJean-Christophe PLAGNIOL-VILLARD #undef DEBUG_RTC 260c698dcaSJean-Christophe PLAGNIOL-VILLARD 270c698dcaSJean-Christophe PLAGNIOL-VILLARD #ifdef DEBUG_RTC 280c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...) printf(fmt ,##args) 290c698dcaSJean-Christophe PLAGNIOL-VILLARD #else 300c698dcaSJean-Christophe PLAGNIOL-VILLARD #define DEBUGR(fmt,args...) 310c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 320c698dcaSJean-Christophe PLAGNIOL-VILLARD /*---------------------------------------------------------------------*/ 330c698dcaSJean-Christophe PLAGNIOL-VILLARD 346d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifndef CONFIG_SYS_I2C_RTC_ADDR 356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD # define CONFIG_SYS_I2C_RTC_ADDR 0x68 360c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 370c698dcaSJean-Christophe PLAGNIOL-VILLARD 386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #if defined(CONFIG_RTC_DS1307) && (CONFIG_SYS_I2C_SPEED > 100000) 390c698dcaSJean-Christophe PLAGNIOL-VILLARD # error The DS1307 is specified only up to 100kHz! 400c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 410c698dcaSJean-Christophe PLAGNIOL-VILLARD 420c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 430c698dcaSJean-Christophe PLAGNIOL-VILLARD * RTC register addresses 440c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 450c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SEC_REG_ADDR 0x00 460c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_MIN_REG_ADDR 0x01 470c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_HR_REG_ADDR 0x02 480c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_DAY_REG_ADDR 0x03 490c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_DATE_REG_ADDR 0x04 500c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_MON_REG_ADDR 0x05 510c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_YR_REG_ADDR 0x06 520c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_REG_ADDR 0x07 530c698dcaSJean-Christophe PLAGNIOL-VILLARD 540c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_SEC_BIT_CH 0x80 /* Clock Halt (in Register 0) */ 550c698dcaSJean-Christophe PLAGNIOL-VILLARD 560c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS0 0x01 /* Rate select 0 */ 570c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_RS1 0x02 /* Rate select 1 */ 580c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_SQWE 0x10 /* Square Wave Enable */ 590c698dcaSJean-Christophe PLAGNIOL-VILLARD #define RTC_CTL_BIT_OUT 0x80 /* Output Control */ 600c698dcaSJean-Christophe PLAGNIOL-VILLARD 61*c79e1c1cSAndy Fleming /* MCP7941X-specific bits */ 62*c79e1c1cSAndy Fleming #define MCP7941X_BIT_ST 0x80 63*c79e1c1cSAndy Fleming #define MCP7941X_BIT_VBATEN 0x08 64*c79e1c1cSAndy Fleming 650c698dcaSJean-Christophe PLAGNIOL-VILLARD static uchar rtc_read (uchar reg); 660c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val); 670c698dcaSJean-Christophe PLAGNIOL-VILLARD 680c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 690c698dcaSJean-Christophe PLAGNIOL-VILLARD * Get the current time from the RTC 700c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 71b73a19e1SYuri Tikhonov int rtc_get (struct rtc_time *tmp) 720c698dcaSJean-Christophe PLAGNIOL-VILLARD { 73b73a19e1SYuri Tikhonov int rel = 0; 740c698dcaSJean-Christophe PLAGNIOL-VILLARD uchar sec, min, hour, mday, wday, mon, year; 750c698dcaSJean-Christophe PLAGNIOL-VILLARD 76*c79e1c1cSAndy Fleming #ifdef CONFIG_RTC_MCP79411 77*c79e1c1cSAndy Fleming read_rtc: 78*c79e1c1cSAndy Fleming #endif 790c698dcaSJean-Christophe PLAGNIOL-VILLARD sec = rtc_read (RTC_SEC_REG_ADDR); 800c698dcaSJean-Christophe PLAGNIOL-VILLARD min = rtc_read (RTC_MIN_REG_ADDR); 810c698dcaSJean-Christophe PLAGNIOL-VILLARD hour = rtc_read (RTC_HR_REG_ADDR); 820c698dcaSJean-Christophe PLAGNIOL-VILLARD wday = rtc_read (RTC_DAY_REG_ADDR); 830c698dcaSJean-Christophe PLAGNIOL-VILLARD mday = rtc_read (RTC_DATE_REG_ADDR); 840c698dcaSJean-Christophe PLAGNIOL-VILLARD mon = rtc_read (RTC_MON_REG_ADDR); 850c698dcaSJean-Christophe PLAGNIOL-VILLARD year = rtc_read (RTC_YR_REG_ADDR); 860c698dcaSJean-Christophe PLAGNIOL-VILLARD 870c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x " 880c698dcaSJean-Christophe PLAGNIOL-VILLARD "hr: %02x min: %02x sec: %02x\n", 890c698dcaSJean-Christophe PLAGNIOL-VILLARD year, mon, mday, wday, hour, min, sec); 900c698dcaSJean-Christophe PLAGNIOL-VILLARD 91*c79e1c1cSAndy Fleming #ifdef CONFIG_RTC_DS1307 920c698dcaSJean-Christophe PLAGNIOL-VILLARD if (sec & RTC_SEC_BIT_CH) { 930c698dcaSJean-Christophe PLAGNIOL-VILLARD printf ("### Warning: RTC oscillator has stopped\n"); 940c698dcaSJean-Christophe PLAGNIOL-VILLARD /* clear the CH flag */ 950c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_SEC_REG_ADDR, 960c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_read (RTC_SEC_REG_ADDR) & ~RTC_SEC_BIT_CH); 97b73a19e1SYuri Tikhonov rel = -1; 980c698dcaSJean-Christophe PLAGNIOL-VILLARD } 99*c79e1c1cSAndy Fleming #endif 100*c79e1c1cSAndy Fleming 101*c79e1c1cSAndy Fleming #ifdef CONFIG_RTC_MCP79411 102*c79e1c1cSAndy Fleming /* make sure that the backup battery is enabled */ 103*c79e1c1cSAndy Fleming if (!(wday & MCP7941X_BIT_VBATEN)) { 104*c79e1c1cSAndy Fleming rtc_write(RTC_DAY_REG_ADDR, 105*c79e1c1cSAndy Fleming wday | MCP7941X_BIT_VBATEN); 106*c79e1c1cSAndy Fleming } 107*c79e1c1cSAndy Fleming 108*c79e1c1cSAndy Fleming /* clock halted? turn it on, so clock can tick. */ 109*c79e1c1cSAndy Fleming if (!(sec & MCP7941X_BIT_ST)) { 110*c79e1c1cSAndy Fleming rtc_write(RTC_SEC_REG_ADDR, MCP7941X_BIT_ST); 111*c79e1c1cSAndy Fleming printf("Started RTC\n"); 112*c79e1c1cSAndy Fleming goto read_rtc; 113*c79e1c1cSAndy Fleming } 114*c79e1c1cSAndy Fleming #endif 115*c79e1c1cSAndy Fleming 1160c698dcaSJean-Christophe PLAGNIOL-VILLARD 1170c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_sec = bcd2bin (sec & 0x7F); 1180c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_min = bcd2bin (min & 0x7F); 1190c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour = bcd2bin (hour & 0x3F); 1200c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_mday = bcd2bin (mday & 0x3F); 1210c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_mon = bcd2bin (mon & 0x1F); 1220c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year = bcd2bin (year) + ( bcd2bin (year) >= 70 ? 1900 : 2000); 1230c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_wday = bcd2bin ((wday - 1) & 0x07); 1240c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_yday = 0; 1250c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_isdst= 0; 1260c698dcaSJean-Christophe PLAGNIOL-VILLARD 1270c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 1280c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, 1290c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour, tmp->tm_min, tmp->tm_sec); 130b73a19e1SYuri Tikhonov 131b73a19e1SYuri Tikhonov return rel; 1320c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1330c698dcaSJean-Christophe PLAGNIOL-VILLARD 1340c698dcaSJean-Christophe PLAGNIOL-VILLARD 1350c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 1360c698dcaSJean-Christophe PLAGNIOL-VILLARD * Set the RTC 1370c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 138d1e23194SJean-Christophe PLAGNIOL-VILLARD int rtc_set (struct rtc_time *tmp) 1390c698dcaSJean-Christophe PLAGNIOL-VILLARD { 1400c698dcaSJean-Christophe PLAGNIOL-VILLARD DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", 1410c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, 1420c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp->tm_hour, tmp->tm_min, tmp->tm_sec); 1430c698dcaSJean-Christophe PLAGNIOL-VILLARD 1440c698dcaSJean-Christophe PLAGNIOL-VILLARD if (tmp->tm_year < 1970 || tmp->tm_year > 2069) 1450c698dcaSJean-Christophe PLAGNIOL-VILLARD printf("WARNING: year should be between 1970 and 2069!\n"); 1460c698dcaSJean-Christophe PLAGNIOL-VILLARD 1470c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100)); 1480c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon)); 149*c79e1c1cSAndy Fleming #ifdef CONFIG_RTC_MCP79411 150*c79e1c1cSAndy Fleming rtc_write (RTC_DAY_REG_ADDR, 151*c79e1c1cSAndy Fleming bin2bcd (tmp->tm_wday + 1) | MCP7941X_BIT_VBATEN); 152*c79e1c1cSAndy Fleming #else 1530c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1)); 154*c79e1c1cSAndy Fleming #endif 1550c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday)); 1560c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour)); 1570c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min)); 158*c79e1c1cSAndy Fleming #ifdef CONFIG_RTC_MCP79411 159*c79e1c1cSAndy Fleming rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec) | MCP7941X_BIT_ST); 160*c79e1c1cSAndy Fleming #else 1610c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec)); 162*c79e1c1cSAndy Fleming #endif 163d1e23194SJean-Christophe PLAGNIOL-VILLARD 164d1e23194SJean-Christophe PLAGNIOL-VILLARD return 0; 1650c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1660c698dcaSJean-Christophe PLAGNIOL-VILLARD 1670c698dcaSJean-Christophe PLAGNIOL-VILLARD 1680c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 1690c698dcaSJean-Christophe PLAGNIOL-VILLARD * Reset the RTC. We setting the date back to 1970-01-01. 1700c698dcaSJean-Christophe PLAGNIOL-VILLARD * We also enable the oscillator output on the SQW/OUT pin and program 1710c698dcaSJean-Christophe PLAGNIOL-VILLARD * it for 32,768 Hz output. Note that according to the datasheet, turning 1720c698dcaSJean-Christophe PLAGNIOL-VILLARD * on the square wave output increases the current drain on the backup 1730c698dcaSJean-Christophe PLAGNIOL-VILLARD * battery to something between 480nA and 800nA. 1740c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 1750c698dcaSJean-Christophe PLAGNIOL-VILLARD void rtc_reset (void) 1760c698dcaSJean-Christophe PLAGNIOL-VILLARD { 1770c698dcaSJean-Christophe PLAGNIOL-VILLARD struct rtc_time tmp; 1780c698dcaSJean-Christophe PLAGNIOL-VILLARD 1790c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_SEC_REG_ADDR, 0x00); /* clearing Clock Halt */ 1800c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_write (RTC_CTL_REG_ADDR, RTC_CTL_BIT_SQWE | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS0); 1810c698dcaSJean-Christophe PLAGNIOL-VILLARD 1820c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year = 1970; 1830c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mon = 1; 1840c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_mday= 1; 1850c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour = 0; 1860c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_min = 0; 1870c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_sec = 0; 1880c698dcaSJean-Christophe PLAGNIOL-VILLARD 1890c698dcaSJean-Christophe PLAGNIOL-VILLARD rtc_set(&tmp); 1900c698dcaSJean-Christophe PLAGNIOL-VILLARD 1910c698dcaSJean-Christophe PLAGNIOL-VILLARD printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", 1920c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_year, tmp.tm_mon, tmp.tm_mday, 1930c698dcaSJean-Christophe PLAGNIOL-VILLARD tmp.tm_hour, tmp.tm_min, tmp.tm_sec); 1940c698dcaSJean-Christophe PLAGNIOL-VILLARD 1950c698dcaSJean-Christophe PLAGNIOL-VILLARD return; 1960c698dcaSJean-Christophe PLAGNIOL-VILLARD } 1970c698dcaSJean-Christophe PLAGNIOL-VILLARD 1980c698dcaSJean-Christophe PLAGNIOL-VILLARD 1990c698dcaSJean-Christophe PLAGNIOL-VILLARD /* 2000c698dcaSJean-Christophe PLAGNIOL-VILLARD * Helper functions 2010c698dcaSJean-Christophe PLAGNIOL-VILLARD */ 2020c698dcaSJean-Christophe PLAGNIOL-VILLARD 2030c698dcaSJean-Christophe PLAGNIOL-VILLARD static 2040c698dcaSJean-Christophe PLAGNIOL-VILLARD uchar rtc_read (uchar reg) 2050c698dcaSJean-Christophe PLAGNIOL-VILLARD { 2066d0f6bcfSJean-Christophe PLAGNIOL-VILLARD return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg)); 2070c698dcaSJean-Christophe PLAGNIOL-VILLARD } 2080c698dcaSJean-Christophe PLAGNIOL-VILLARD 2090c698dcaSJean-Christophe PLAGNIOL-VILLARD 2100c698dcaSJean-Christophe PLAGNIOL-VILLARD static void rtc_write (uchar reg, uchar val) 2110c698dcaSJean-Christophe PLAGNIOL-VILLARD { 2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val); 2130c698dcaSJean-Christophe PLAGNIOL-VILLARD } 2140c698dcaSJean-Christophe PLAGNIOL-VILLARD #endif 215