1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 #include <asm/arch-rockchip/hardware.h> 6 #include <asm/io.h> 7 #include <common.h> 8 #include <dm.h> 9 #include <linux/iopoll.h> 10 #include <linux/string.h> 11 #include <rng.h> 12 13 #define RK_HW_RNG_MAX 32 14 15 #define _SBF(s, v) ((v) << (s)) 16 17 /* start of CRYPTO V1 register define */ 18 #define CRYPTO_V1_CTRL 0x0008 19 #define CRYPTO_V1_RNG_START BIT(8) 20 #define CRYPTO_V1_RNG_FLUSH BIT(9) 21 22 #define CRYPTO_V1_TRNG_CTRL 0x0200 23 #define CRYPTO_V1_OSC_ENABLE BIT(16) 24 #define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x) 25 26 #define CRYPTO_V1_TRNG_DOUT_0 0x0204 27 /* end of CRYPTO V1 register define */ 28 29 /* start of CRYPTO V2 register define */ 30 #define CRYPTO_V2_RNG_CTL 0x0400 31 #define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00) 32 #define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01) 33 #define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02) 34 #define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03) 35 #define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00) 36 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01) 37 #define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02) 38 #define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03) 39 #define CRYPTO_V2_RNG_ENABLE BIT(1) 40 #define CRYPTO_V2_RNG_START BIT(0) 41 #define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404 42 #define CRYPTO_V2_RNG_DOUT_0 0x0410 43 /* end of CRYPTO V2 register define */ 44 45 /* start of TRNG V1 register define */ 46 #define TRNG_V1_CTRL 0x0000 47 #define TRNG_V1_CTRL_NOP _SBF(0, 0x00) 48 #define TRNG_V1_CTRL_RAND _SBF(0, 0x01) 49 #define TRNG_V1_CTRL_SEED _SBF(0, 0x02) 50 51 #define TRNG_V1_MODE 0x0008 52 #define TRNG_V1_MODE_128_BIT _SBF(3, 0x00) 53 #define TRNG_V1_MODE_256_BIT _SBF(3, 0x01) 54 55 #define TRNG_V1_IE 0x0010 56 #define TRNG_V1_IE_GLBL_EN BIT(31) 57 #define TRNG_V1_IE_SEED_DONE_EN BIT(1) 58 #define TRNG_V1_IE_RAND_RDY_EN BIT(0) 59 60 #define TRNG_V1_ISTAT 0x0014 61 #define TRNG_V1_ISTAT_RAND_RDY BIT(0) 62 63 /* RAND0 ~ RAND7 */ 64 #define TRNG_V1_RAND0 0x0020 65 #define TRNG_V1_RAND7 0x003C 66 67 #define TRNG_V1_AUTO_RQSTS 0x0060 68 69 #define TRNG_V1_VERSION 0x00F0 70 #define TRNG_v1_VERSION_CODE 0x46BC 71 /* end of TRNG V1 register define */ 72 73 /* start of RKRNG register define */ 74 #define RKRNG_CTRL 0x0010 75 #define RKRNG_CTRL_INST_REQ BIT(0) 76 #define RKRNG_CTRL_RESEED_REQ BIT(1) 77 #define RKRNG_CTRL_TEST_REQ BIT(2) 78 #define RKRNG_CTRL_SW_DRNG_REQ BIT(3) 79 #define RKRNG_CTRL_SW_TRNG_REQ BIT(4) 80 81 #define RKRNG_STATE 0x0014 82 #define RKRNG_STATE_INST_ACK BIT(0) 83 #define RKRNG_STATE_RESEED_ACK BIT(1) 84 #define RKRNG_STATE_TEST_ACK BIT(2) 85 #define RKRNG_STATE_SW_DRNG_ACK BIT(3) 86 #define RKRNG_STATE_SW_TRNG_ACK BIT(4) 87 88 /* DRNG_DATA_0 ~ DNG_DATA_7 */ 89 #define RKRNG_DRNG_DATA_0 0x0070 90 #define RKRNG_DRNG_DATA_7 0x008C 91 92 /* end of RKRNG register define */ 93 94 #define RK_RNG_TIME_OUT 50000 /* max 50ms */ 95 96 #define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos)) 97 #define trng_read(pdata, pos) readl((pdata)->base + (pos)) 98 99 struct rk_rng_soc_data { 100 int (*rk_rng_init)(struct udevice *dev); 101 int (*rk_rng_read)(struct udevice *dev, void *data, size_t len); 102 }; 103 104 struct rk_rng_platdata { 105 fdt_addr_t base; 106 struct rk_rng_soc_data *soc_data; 107 }; 108 109 static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size) 110 { 111 u32 count = RK_HW_RNG_MAX / sizeof(u32); 112 u32 reg, tmp_len; 113 114 if (size > RK_HW_RNG_MAX) 115 return -EINVAL; 116 117 while (size && count) { 118 reg = readl(addr); 119 tmp_len = min(size, sizeof(u32)); 120 memcpy(buf, ®, tmp_len); 121 addr += sizeof(u32); 122 buf += tmp_len; 123 size -= tmp_len; 124 count--; 125 } 126 127 return 0; 128 } 129 130 static int cryptov1_rng_read(struct udevice *dev, void *data, size_t len) 131 { 132 struct rk_rng_platdata *pdata = dev_get_priv(dev); 133 u32 reg = 0; 134 int retval; 135 136 if (len > RK_HW_RNG_MAX) 137 return -EINVAL; 138 139 /* enable osc_ring to get entropy, sample period is set as 100 */ 140 writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100), 141 pdata->base + CRYPTO_V1_TRNG_CTRL); 142 143 rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START, 144 CRYPTO_V1_RNG_START); 145 146 retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg, 147 !(reg & CRYPTO_V1_RNG_START), 148 RK_RNG_TIME_OUT); 149 if (retval) 150 goto exit; 151 152 rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len); 153 154 exit: 155 /* close TRNG */ 156 rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START); 157 158 return 0; 159 } 160 161 static int cryptov2_rng_read(struct udevice *dev, void *data, size_t len) 162 { 163 struct rk_rng_platdata *pdata = dev_get_priv(dev); 164 u32 reg = 0; 165 int retval; 166 167 if (len > RK_HW_RNG_MAX) 168 return -EINVAL; 169 170 /* enable osc_ring to get entropy, sample period is set as 100 */ 171 writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT); 172 173 reg |= CRYPTO_V2_RNG_256_BIT_LEN; 174 reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0; 175 reg |= CRYPTO_V2_RNG_ENABLE; 176 reg |= CRYPTO_V2_RNG_START; 177 178 rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg); 179 180 retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg, 181 !(reg & CRYPTO_V2_RNG_START), 182 RK_RNG_TIME_OUT); 183 if (retval) 184 goto exit; 185 186 rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len); 187 188 exit: 189 /* close TRNG */ 190 rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff); 191 192 return retval; 193 } 194 195 static int trngv1_init(struct udevice *dev) 196 { 197 u32 status, version; 198 u32 auto_reseed_cnt = 1000; 199 struct rk_rng_platdata *pdata = dev_get_priv(dev); 200 201 version = trng_read(pdata, TRNG_V1_VERSION); 202 if (version != TRNG_v1_VERSION_CODE) { 203 printf("wrong trng version, expected = %08x, actual = %08x", 204 TRNG_V1_VERSION, version); 205 return -EFAULT; 206 } 207 208 /* wait in case of RND_RDY triggered at firs power on */ 209 readl_poll_timeout(pdata->base + TRNG_V1_ISTAT, status, 210 (status & TRNG_V1_ISTAT_RAND_RDY), 211 RK_RNG_TIME_OUT); 212 213 /* clear RAND_RDY flag for first power on */ 214 trng_write(pdata, TRNG_V1_ISTAT, status); 215 216 /* auto reseed after (auto_reseed_cnt * 16) byte rand generate */ 217 trng_write(pdata, TRNG_V1_AUTO_RQSTS, auto_reseed_cnt); 218 219 return 0; 220 } 221 222 static int trngv1_rng_read(struct udevice *dev, void *data, size_t len) 223 { 224 struct rk_rng_platdata *pdata = dev_get_priv(dev); 225 u32 reg = 0; 226 int retval; 227 228 if (len > RK_HW_RNG_MAX) 229 return -EINVAL; 230 231 trng_write(pdata, TRNG_V1_MODE, TRNG_V1_MODE_256_BIT); 232 trng_write(pdata, TRNG_V1_CTRL, TRNG_V1_CTRL_RAND); 233 234 retval = readl_poll_timeout(pdata->base + TRNG_V1_ISTAT, reg, 235 (reg & TRNG_V1_ISTAT_RAND_RDY), 236 RK_RNG_TIME_OUT); 237 /* clear ISTAT */ 238 trng_write(pdata, TRNG_V1_ISTAT, reg); 239 240 if (retval) 241 goto exit; 242 243 rk_rng_read_regs(pdata->base + TRNG_V1_RAND0, data, len); 244 245 exit: 246 /* close TRNG */ 247 trng_write(pdata, TRNG_V1_CTRL, TRNG_V1_CTRL_NOP); 248 249 return retval; 250 } 251 252 static int rkrng_init(struct udevice *dev) 253 { 254 struct rk_rng_platdata *pdata = dev_get_priv(dev); 255 u32 reg = 0; 256 257 rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff); 258 259 reg = trng_read(pdata, RKRNG_STATE); 260 trng_write(pdata, RKRNG_STATE, reg); 261 262 return 0; 263 } 264 265 static int rkrng_rng_read(struct udevice *dev, void *data, size_t len) 266 { 267 struct rk_rng_platdata *pdata = dev_get_priv(dev); 268 u32 reg = 0; 269 int retval; 270 271 if (len > RK_HW_RNG_MAX) 272 return -EINVAL; 273 274 reg = RKRNG_CTRL_SW_DRNG_REQ; 275 276 rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg); 277 278 retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg, 279 (reg & RKRNG_STATE_SW_DRNG_ACK), 280 RK_RNG_TIME_OUT); 281 if (retval) 282 goto exit; 283 284 trng_write(pdata, RKRNG_STATE, reg); 285 286 rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len); 287 288 exit: 289 /* close TRNG */ 290 rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff); 291 292 return retval; 293 } 294 295 static int rockchip_rng_read(struct udevice *dev, void *data, size_t len) 296 { 297 unsigned char *buf = data; 298 unsigned int i; 299 int ret = -EIO; 300 301 struct rk_rng_platdata *pdata = dev_get_priv(dev); 302 303 if (!len) 304 return 0; 305 306 if (!pdata->soc_data || !pdata->soc_data->rk_rng_read) 307 return -EINVAL; 308 309 for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) { 310 ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX); 311 if (ret) 312 goto exit; 313 } 314 315 if (len % RK_HW_RNG_MAX) 316 ret = pdata->soc_data->rk_rng_read(dev, buf, 317 len % RK_HW_RNG_MAX); 318 319 exit: 320 return ret; 321 } 322 323 static int rockchip_rng_ofdata_to_platdata(struct udevice *dev) 324 { 325 struct rk_rng_platdata *pdata = dev_get_priv(dev); 326 327 memset(pdata, 0x00, sizeof(*pdata)); 328 329 pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev); 330 if (!pdata->base) 331 return -ENOMEM; 332 333 return 0; 334 } 335 336 static int rockchip_rng_probe(struct udevice *dev) 337 { 338 struct rk_rng_platdata *pdata = dev_get_priv(dev); 339 int ret = 0; 340 341 pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev); 342 343 if (pdata->soc_data->rk_rng_init) 344 ret = pdata->soc_data->rk_rng_init(dev); 345 346 return ret; 347 } 348 349 static const struct rk_rng_soc_data cryptov1_soc_data = { 350 .rk_rng_read = cryptov1_rng_read, 351 }; 352 353 static const struct rk_rng_soc_data cryptov2_soc_data = { 354 .rk_rng_read = cryptov2_rng_read, 355 }; 356 357 static const struct rk_rng_soc_data trngv1_soc_data = { 358 .rk_rng_init = trngv1_init, 359 .rk_rng_read = trngv1_rng_read, 360 }; 361 362 static const struct rk_rng_soc_data rkrng_soc_data = { 363 .rk_rng_init = rkrng_init, 364 .rk_rng_read = rkrng_rng_read, 365 }; 366 367 static const struct dm_rng_ops rockchip_rng_ops = { 368 .read = rockchip_rng_read, 369 }; 370 371 static const struct udevice_id rockchip_rng_match[] = { 372 { 373 .compatible = "rockchip,cryptov1-rng", 374 .data = (ulong)&cryptov1_soc_data, 375 }, 376 { 377 .compatible = "rockchip,cryptov2-rng", 378 .data = (ulong)&cryptov2_soc_data, 379 }, 380 { 381 .compatible = "rockchip,trngv1", 382 .data = (ulong)&trngv1_soc_data, 383 }, 384 { 385 .compatible = "rockchip,rkrng", 386 .data = (ulong)&rkrng_soc_data, 387 }, 388 {}, 389 }; 390 391 U_BOOT_DRIVER(rockchip_rng) = { 392 .name = "rockchip-rng", 393 .id = UCLASS_RNG, 394 .of_match = rockchip_rng_match, 395 .ops = &rockchip_rng_ops, 396 .probe = rockchip_rng_probe, 397 .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata, 398 .priv_auto_alloc_size = sizeof(struct rk_rng_platdata), 399 }; 400