1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _SFC_NOR_H 8 #define _SFC_NOR_H 9 10 #include "sfc.h" 11 12 #define NOR_PAGE_SIZE 256 13 #define NOR_BLOCK_SIZE (64 * 1024) 14 #define NOR_SECS_BLK (NOR_BLOCK_SIZE / 512) 15 #define NOR_SECS_PAGE 8 16 17 #define FEA_READ_STATUE_MASK (0x3 << 0) 18 #define FEA_STATUE_MODE1 0 19 #define FEA_STATUE_MODE2 1 20 #define FEA_4BIT_READ BIT(2) 21 #define FEA_4BIT_PROG BIT(3) 22 #define FEA_4BYTE_ADDR BIT(4) 23 #define FEA_4BYTE_ADDR_MODE BIT(5) 24 25 /*Command Set*/ 26 #define CMD_READ_JEDECID (0x9F) 27 #define CMD_READ_DATA (0x03) 28 #define CMD_READ_STATUS (0x05) 29 #define CMD_WRITE_STATUS (0x01) 30 #define CMD_PAGE_PROG (0x02) 31 #define CMD_SECTOR_ERASE (0x20) 32 #define CMD_BLK64K_ERASE (0xD8) 33 #define CMD_BLK32K_ERASE (0x52) 34 #define CMD_CHIP_ERASE (0xC7) 35 #define CMD_WRITE_EN (0x06) 36 #define CMD_WRITE_DIS (0x04) 37 #define CMD_PAGE_READ (0x13) 38 #define CMD_GET_FEATURE (0x0F) 39 #define CMD_SET_FEATURE (0x1F) 40 #define CMD_PROG_LOAD (0x02) 41 #define CMD_PROG_EXEC (0x10) 42 #define CMD_BLOCK_ERASE (0xD8) 43 #define CMD_READ_DATA_X2 (0x3B) 44 #define CMD_READ_DATA_X4 (0x6B) 45 #define CMD_PROG_LOAD_X4 (0x32) 46 #define CMD_READ_STATUS2 (0x35) 47 #define CMD_READ_STATUS3 (0x15) 48 #define CMD_WRITE_STATUS2 (0x31) 49 #define CMD_WRITE_STATUS3 (0x11) 50 /* X1 cmd, X1 addr, X1 data */ 51 #define CMD_FAST_READ_X1 (0x0B) 52 /* X1 cmd, X1 addr, X2 data */ 53 #define CMD_FAST_READ_X2 (0x3B) 54 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 55 #define CMD_FAST_READ_X4 (0x6B) 56 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 57 #define CMD_FAST_4READ_X4 (0x6C) 58 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 59 #define CMD_FAST_READ_A4 (0xEB) 60 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 61 #define CMD_PAGE_PROG_X4 (0x32) 62 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 63 #define CMD_PAGE_PROG_A4 (0x38) 64 #define CMD_RESET_NAND (0xFF) 65 #define CMD_ENTER_4BYTE_MODE (0xB7) 66 #define CMD_EXIT_4BYTE_MODE (0xE9) 67 #define CMD_ENABLE_RESER (0x66) 68 #define CMD_RESET_DEVICE (0x99) 69 #define CMD_READ_PARAMETER (0x5A) 70 71 enum NOR_ERASE_TYPE { 72 ERASE_SECTOR = 0, 73 ERASE_BLOCK64K, 74 ERASE_CHIP 75 }; 76 77 enum SNOR_IO_MODE { 78 IO_MODE_SPI = 0, 79 IO_MODE_QPI 80 }; 81 82 enum SNOR_READ_MODE { 83 READ_MODE_NOMAL = 0, 84 READ_MODE_FAST 85 }; 86 87 enum SNOR_ADDR_MODE { 88 ADDR_MODE_3BYTE = 0, 89 ADDR_MODE_4BYTE 90 }; 91 92 typedef int (*SNOR_WRITE_STATUS)(u32 reg_index, u8 status); 93 94 struct SFNOR_DEV { 95 u32 capacity; 96 u8 manufacturer; 97 u8 mem_type; 98 u16 page_size; 99 u32 blk_size; 100 101 u8 read_cmd; 102 u8 prog_cmd; 103 u8 sec_erase_cmd; 104 u8 blk_erase_cmd; 105 u8 QE_bits; 106 107 enum SNOR_READ_MODE read_mode; 108 enum SNOR_ADDR_MODE addr_mode; 109 enum SNOR_IO_MODE io_mode; 110 111 enum SFC_DATA_LINES read_lines; 112 enum SFC_DATA_LINES prog_lines; 113 114 SNOR_WRITE_STATUS write_status; 115 }; 116 117 struct flash_info { 118 u32 id; 119 120 u8 block_size; 121 u8 sector_size; 122 u8 read_cmd; 123 u8 prog_cmd; 124 125 u8 read_cmd_4; 126 u8 prog_cmd_4; 127 u8 sector_erase_cmd; 128 u8 block_erase_cmd; 129 130 u8 feature; 131 u8 density; /* (1 << density) sectors*/ 132 u8 QE_bits; 133 u8 reserved2; 134 }; 135 136 int snor_init(struct SFNOR_DEV *p_dev); 137 u32 snor_get_capacity(struct SFNOR_DEV *p_dev); 138 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 139 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 140 int snor_erase(struct SFNOR_DEV *p_dev, 141 u32 addr, 142 enum NOR_ERASE_TYPE erase_type); 143 int snor_read_id(u8 *data); 144 int snor_prog_page(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 145 int snor_read_data(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size); 146 int snor_reset_device(void); 147 int snor_disable_QE(struct SFNOR_DEV *p_dev); 148 149 #endif 150