1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _SFNOR_H 8 #define _SFNOR_H 9 10 #include "sfc.h" 11 12 /* Four line data transmission detection */ 13 #define SNOR_4BIT_DATA_DETECT_EN 0 14 15 #define NOR_PAGE_SIZE 256 16 #define NOR_BLOCK_SIZE (64 * 1024) 17 #define NOR_SECS_BLK (NOR_BLOCK_SIZE / 512) 18 #define NOR_SECS_PAGE 4 19 20 #define FEA_READ_STATUE_MASK (0x3 << 0) 21 #define FEA_STATUE_MODE1 0 22 #define FEA_STATUE_MODE2 1 23 #define FEA_4BIT_READ BIT(2) 24 #define FEA_4BIT_PROG BIT(3) 25 #define FEA_4BYTE_ADDR BIT(4) 26 #define FEA_4BYTE_ADDR_MODE BIT(5) 27 28 /*Manufactory ID*/ 29 #define MID_WINBOND 0xEF 30 #define MID_GIGADEV 0xC8 31 #define MID_MICRON 0x2C 32 #define MID_MACRONIX 0xC2 33 #define MID_SPANSION 0x01 34 #define MID_EON 0x1C 35 #define MID_ST 0x20 36 37 /*Command Set*/ 38 #define CMD_READ_JEDECID (0x9F) 39 #define CMD_READ_DATA (0x03) 40 #define CMD_READ_STATUS (0x05) 41 #define CMD_WRITE_STATUS (0x01) 42 #define CMD_PAGE_PROG (0x02) 43 #define CMD_SECTOR_ERASE (0x20) 44 #define CMD_BLK64K_ERASE (0xD8) 45 #define CMD_BLK32K_ERASE (0x52) 46 #define CMD_CHIP_ERASE (0xC7) 47 #define CMD_WRITE_EN (0x06) 48 #define CMD_WRITE_DIS (0x04) 49 #define CMD_PAGE_READ (0x13) 50 #define CMD_GET_FEATURE (0x0F) 51 #define CMD_SET_FEATURE (0x1F) 52 #define CMD_PROG_LOAD (0x02) 53 #define CMD_PROG_EXEC (0x10) 54 #define CMD_BLOCK_ERASE (0xD8) 55 #define CMD_READ_DATA_X2 (0x3B) 56 #define CMD_READ_DATA_X4 (0x6B) 57 #define CMD_PROG_LOAD_X4 (0x32) 58 #define CMD_READ_STATUS2 (0x35) 59 #define CMD_READ_STATUS3 (0x15) 60 #define CMD_WRITE_STATUS2 (0x31) 61 #define CMD_WRITE_STATUS3 (0x11) 62 /* X1 cmd, X1 addr, X1 data */ 63 #define CMD_FAST_READ_X1 (0x0B) 64 /* X1 cmd, X1 addr, X2 data */ 65 #define CMD_FAST_READ_X2 (0x3B) 66 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 67 #define CMD_FAST_READ_X4 (0x6B) 68 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 69 #define CMD_FAST_4READ_X4 (0x6C) 70 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 71 #define CMD_FAST_READ_A4 (0xEB) 72 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 73 #define CMD_PAGE_PROG_X4 (0x32) 74 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 75 #define CMD_PAGE_PROG_A4 (0x38) 76 #define CMD_RESET_NAND (0xFF) 77 #define CMD_ENTER_4BYTE_MODE (0xB7) 78 #define CMD_EXIT_4BYTE_MODE (0xE9) 79 #define CMD_ENABLE_RESER (0x66) 80 #define CMD_RESET_DEVICE (0x99) 81 #define CMD_READ_PARAMETER (0x5A) 82 83 enum NOR_ERASE_TYPE { 84 ERASE_SECTOR = 0, 85 ERASE_BLOCK64K, 86 ERASE_CHIP 87 }; 88 89 enum SNOR_IO_MODE { 90 IO_MODE_SPI = 0, 91 IO_MODE_QPI 92 }; 93 94 enum SNOR_READ_MODE { 95 READ_MODE_NOMAL = 0, 96 READ_MODE_FAST 97 }; 98 99 enum SNOR_ADDR_MODE { 100 ADDR_MODE_3BYTE = 0, 101 ADDR_MODE_4BYTE 102 }; 103 104 typedef int (*SNOR_WRITE_STATUS)(u32 reg_index, u8 status); 105 106 struct SFNOR_DEV { 107 u32 capacity; 108 u8 manufacturer; 109 u8 mem_type; 110 u16 page_size; 111 u32 blk_size; 112 113 u8 read_cmd; 114 u8 prog_cmd; 115 u8 sec_erase_cmd; 116 u8 blk_erase_cmd; 117 u8 QE_bits; 118 119 enum SNOR_READ_MODE read_mode; 120 enum SNOR_ADDR_MODE addr_mode; 121 enum SNOR_IO_MODE io_mode; 122 123 enum SFC_DATA_LINES read_lines; 124 enum SFC_DATA_LINES prog_lines; 125 126 SNOR_WRITE_STATUS write_status; 127 struct mutex lock; /* to lock this object */ 128 }; 129 130 struct flash_info { 131 u32 id; 132 133 u8 block_size; 134 u8 sector_size; 135 u8 read_cmd; 136 u8 prog_cmd; 137 138 u8 read_cmd_4; 139 u8 prog_cmd_4; 140 u8 sector_erase_cmd; 141 u8 block_erase_cmd; 142 143 u8 feature; 144 u8 density; /* (1 << density) sectors*/ 145 u8 QE_bits; 146 u8 reserved2; 147 }; 148 149 int snor_init(struct SFNOR_DEV *p_dev); 150 u32 snor_get_capacity(struct SFNOR_DEV *p_dev); 151 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data); 152 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, const void *p_data); 153 154 #endif 155