1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "sfc_nor.h" 12 #include "rkflash_debug.h" 13 #include "rkflash_blk.h" 14 15 static struct flash_info spi_flash_tbl[] = { 16 /* GD25Q32B */ 17 {0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0}, 18 /* GD25Q64B */ 19 {0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0}, 20 /* GD25Q127C and GD25Q128C*/ 21 {0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 22 /* GD25Q256B */ 23 {0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0}, 24 /* GD25Q512MC */ 25 {0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0}, 26 /* 25Q128FV */ 27 {0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 28 /* 25Q256FV */ 29 {0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0}, 30 /* XT25F128A */ 31 {0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0}, 32 /* MX25L25635E/F */ 33 {0xc22019, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x30, 16, 6, 0}, 34 }; 35 36 static const u8 sfnor_dev_code[] = { 37 0x11, 38 0x12, 39 0x13, 40 0x14, 41 0x15, 42 0x16, 43 0x17, 44 0x18, 45 0x19 46 }; 47 48 static const u32 sfnor_capacity[] = { 49 0x20000, /* 128k-byte */ 50 0x40000, /* 256k-byte */ 51 0x80000, /* 512k-byte */ 52 0x100000, /* 1M-byte */ 53 0x200000, /* 2M-byte */ 54 0x400000, /* 4M-byte */ 55 0x800000, /* 8M-byte */ 56 0x1000000, /* 16M-byte */ 57 0x2000000 /* 32M-byte */ 58 }; 59 60 static struct flash_info *g_spi_flash_info; 61 62 static int snor_write_en(void) 63 { 64 int ret; 65 union SFCCMD_DATA sfcmd; 66 67 sfcmd.d32 = 0; 68 sfcmd.b.cmd = CMD_WRITE_EN; 69 70 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 71 72 return ret; 73 } 74 75 static int snor_enter_4byte_mode(void) 76 { 77 int ret; 78 union SFCCMD_DATA sfcmd; 79 80 sfcmd.d32 = 0; 81 sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 82 83 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 84 return ret; 85 } 86 87 static int snor_read_status(u32 reg_index, u8 *status) 88 { 89 int ret; 90 union SFCCMD_DATA sfcmd; 91 u8 read_stat_cmd[] = {CMD_READ_STATUS, 92 CMD_READ_STATUS2, CMD_READ_STATUS3}; 93 sfcmd.d32 = 0; 94 sfcmd.b.cmd = read_stat_cmd[reg_index]; 95 sfcmd.b.datasize = 1; 96 97 ret = sfc_request(sfcmd.d32, 0, 0, status); 98 99 return ret; 100 } 101 102 static int snor_wait_busy(int timeout) 103 { 104 int ret; 105 union SFCCMD_DATA sfcmd; 106 int i; 107 u32 status; 108 109 sfcmd.d32 = 0; 110 sfcmd.b.cmd = CMD_READ_STATUS; 111 sfcmd.b.datasize = 1; 112 113 for (i = 0; i < timeout; i++) { 114 ret = sfc_request(sfcmd.d32, 0, 0, &status); 115 if (ret != SFC_OK) 116 return ret; 117 118 if ((status & 0x01) == 0) 119 return SFC_OK; 120 121 sfc_delay(1); 122 } 123 PRINT_SFC_E("%s error %x\n", __func__, timeout); 124 125 return SFC_BUSY_TIMEOUT; 126 } 127 128 static int snor_write_status2(u32 reg_index, u8 status) 129 { 130 int ret; 131 union SFCCMD_DATA sfcmd; 132 u8 status2[2]; 133 u8 read_index; 134 135 status2[reg_index] = status; 136 read_index = (reg_index == 0) ? 1 : 0; 137 ret = snor_read_status(read_index, &status2[read_index]); 138 if (ret != SFC_OK) 139 return ret; 140 141 snor_write_en(); 142 143 sfcmd.d32 = 0; 144 sfcmd.b.cmd = CMD_WRITE_STATUS; 145 sfcmd.b.datasize = 2; 146 sfcmd.b.rw = SFC_WRITE; 147 148 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 149 if (ret != SFC_OK) 150 return ret; 151 152 ret = snor_wait_busy(10000); /* 10ms */ 153 154 return ret; 155 } 156 157 static int snor_write_status(u32 reg_index, u8 status) 158 { 159 int ret; 160 union SFCCMD_DATA sfcmd; 161 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 162 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 163 snor_write_en(); 164 sfcmd.d32 = 0; 165 sfcmd.b.cmd = write_stat_cmd[reg_index]; 166 sfcmd.b.datasize = 1; 167 sfcmd.b.rw = SFC_WRITE; 168 169 ret = sfc_request(sfcmd.d32, 0, 0, &status); 170 if (ret != SFC_OK) 171 return ret; 172 173 ret = snor_wait_busy(10000); /* 10ms */ 174 175 return ret; 176 } 177 178 static int snor_erase(struct SFNOR_DEV *p_dev, 179 u32 addr, 180 enum NOR_ERASE_TYPE erase_type) 181 { 182 int ret; 183 union SFCCMD_DATA sfcmd; 184 int timeout[] = {400, 2000, 40000}; /* ms */ 185 186 if (erase_type > ERASE_CHIP) 187 return SFC_PARAM_ERR; 188 189 sfcmd.d32 = 0; 190 if (erase_type == ERASE_BLOCK64K) 191 sfcmd.b.cmd = p_dev->blk_erase_cmd; 192 else if (erase_type == ERASE_SECTOR) 193 sfcmd.b.cmd = p_dev->sec_erase_cmd; 194 else 195 sfcmd.b.cmd = CMD_CHIP_ERASE; 196 197 sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 198 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 199 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 200 sfcmd.b.addrbits = SFC_ADDR_32BITS; 201 202 snor_write_en(); 203 204 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 205 if (ret != SFC_OK) 206 return ret; 207 208 ret = snor_wait_busy(timeout[erase_type] * 1000); 209 return ret; 210 } 211 212 static int snor_prog_page(struct SFNOR_DEV *p_dev, 213 u32 addr, 214 void *p_data, 215 u32 size) 216 { 217 int ret; 218 union SFCCMD_DATA sfcmd; 219 union SFCCTRL_DATA sfctrl; 220 221 sfcmd.d32 = 0; 222 sfcmd.b.cmd = p_dev->prog_cmd; 223 sfcmd.b.addrbits = SFC_ADDR_24BITS; 224 sfcmd.b.datasize = size; 225 sfcmd.b.rw = SFC_WRITE; 226 227 sfctrl.d32 = 0; 228 sfctrl.b.datalines = p_dev->prog_lines; 229 sfctrl.b.enbledma = 0; 230 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 231 sfctrl.b.addrlines = SFC_4BITS_LINE; 232 233 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 234 sfcmd.b.addrbits = SFC_ADDR_32BITS; 235 236 snor_write_en(); 237 238 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 239 if (ret != SFC_OK) 240 return ret; 241 242 ret = snor_wait_busy(10000); 243 244 return ret; 245 } 246 247 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 248 { 249 int ret = SFC_OK; 250 u32 page_size, len; 251 u8 *p_buf = (u8 *)p_data; 252 253 page_size = NOR_PAGE_SIZE; 254 while (size) { 255 len = page_size < size ? page_size : size; 256 ret = snor_prog_page(p_dev, addr, p_buf, len); 257 if (ret != SFC_OK) 258 return ret; 259 260 size -= len; 261 addr += len; 262 p_buf += len; 263 } 264 265 return ret; 266 } 267 268 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 269 { 270 int ret = SFC_OK; 271 int reg_index; 272 int bit_offset; 273 u8 status; 274 275 if (p_dev->manufacturer == MID_GIGADEV || 276 p_dev->manufacturer == MID_WINBOND) { 277 reg_index = p_dev->QE_bits >> 3; 278 bit_offset = p_dev->QE_bits & 0x7; 279 ret = snor_read_status(reg_index, &status); 280 if (ret != SFC_OK) 281 return ret; 282 283 if (status & (1 << bit_offset)) /* is QE bit set */ 284 return SFC_OK; 285 286 status |= (1 << bit_offset); 287 return p_dev->write_status(reg_index, status); 288 } 289 290 return ret; 291 } 292 293 #if (SNOR_4BIT_DATA_DETECT_EN) 294 static int snor_set_dlines(struct SFNOR_DEV *p_dev, enum SFC_DATA_LINES lines) 295 { 296 int ret; 297 u8 read_cmd[] = {CMD_FAST_READ_X1, CMD_FAST_READ_X2, CMD_FAST_READ_X4}; 298 299 if (lines == DATA_LINES_X4) { 300 ret = snor_enable_QE(p_dev); 301 if (ret != SFC_OK) 302 return ret; 303 } 304 305 p_dev->read_lines = lines; 306 p_dev->read_cmd = read_cmd[lines]; 307 308 if (p_dev->manufacturer == MID_GIGADEV || 309 p_dev->manufacturer == MID_WINBOND || 310 p_dev->manufacturer == MID_MACRONIX) { 311 p_dev->prog_lines = (lines != DATA_LINES_X2) ? 312 lines : DATA_LINES_X1; 313 if (lines == DATA_LINES_X1) { 314 p_dev->prog_cmd = CMD_PAGE_PROG; 315 } else { 316 if (p_dev->manufacturer == MID_GIGADEV || 317 p_dev->manufacturer == MID_WINBOND) 318 p_dev->prog_cmd = CMD_PAGE_PROG_X4; 319 else 320 p_dev->prog_cmd = CMD_PAGE_PROG_A4; 321 } 322 } 323 324 return SFC_OK; 325 } 326 #endif 327 328 static int snor_read_data(struct SFNOR_DEV *p_dev, 329 u32 addr, 330 void *p_data, 331 u32 size) 332 { 333 int ret; 334 union SFCCMD_DATA sfcmd; 335 union SFCCTRL_DATA sfctrl; 336 337 sfcmd.d32 = 0; 338 sfcmd.b.cmd = p_dev->read_cmd; 339 sfcmd.b.datasize = size; 340 sfcmd.b.addrbits = SFC_ADDR_24BITS; 341 342 sfctrl.d32 = 0; 343 sfctrl.b.datalines = p_dev->read_lines; 344 if (!(size & 0x3) && size >= 4) 345 sfctrl.b.enbledma = 0; 346 347 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 348 p_dev->read_cmd == CMD_FAST_READ_X4 || 349 p_dev->read_cmd == CMD_FAST_READ_X2 || 350 p_dev->read_cmd == CMD_FAST_4READ_X4) { 351 sfcmd.b.dummybits = 8; 352 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 353 sfcmd.b.addrbits = SFC_ADDR_32BITS; 354 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 355 sfcmd.b.dummybits = 4; 356 sfctrl.b.addrlines = SFC_4BITS_LINE; 357 } 358 359 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 360 sfcmd.b.addrbits = SFC_ADDR_32BITS; 361 362 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 363 364 return ret; 365 } 366 367 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 368 { 369 int ret = SFC_OK; 370 u32 addr, size, len; 371 u8 *p_buf = (u8 *)p_data; 372 373 if ((sec + n_sec) > p_dev->capacity) 374 return SFC_PARAM_ERR; 375 376 mutex_lock(&p_dev->lock); 377 addr = sec << 9; 378 size = n_sec << 9; 379 while (size) { 380 len = size < SFC_MAX_IOSIZE ? size : SFC_MAX_IOSIZE; 381 ret = snor_read_data(p_dev, addr, p_buf, len); 382 if (ret != SFC_OK) { 383 PRINT_SFC_E("snor_read_data %x ret= %x\n", 384 addr >> 9, ret); 385 goto out; 386 } 387 388 size -= len; 389 addr += len; 390 p_buf += len; 391 } 392 out: 393 mutex_unlock(&p_dev->lock); 394 if (!ret) 395 ret = n_sec; 396 397 return ret; 398 } 399 400 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, const void *p_data) 401 { 402 int ret = SFC_OK; 403 u32 len, blk_size, offset; 404 u8 *p_buf = (u8 *)p_data; 405 u32 total_sec = n_sec; 406 407 if ((sec + n_sec) > p_dev->capacity) 408 return SFC_PARAM_ERR; 409 410 mutex_lock(&p_dev->lock); 411 while (n_sec) { 412 if (sec < 512 || sec >= p_dev->capacity - 512) 413 blk_size = 8; 414 else 415 blk_size = p_dev->blk_size; 416 417 offset = (sec & (blk_size - 1)); 418 if (!offset) { 419 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 420 ERASE_SECTOR : ERASE_BLOCK64K); 421 if (ret != SFC_OK) { 422 PRINT_SFC_E("snor_erase %x ret= %x\n", 423 sec, ret); 424 goto out; 425 } 426 } 427 len = (blk_size - offset) < n_sec ? 428 (blk_size - offset) : n_sec; 429 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 430 if (ret != SFC_OK) { 431 PRINT_SFC_E("snor_prog %x ret= %x\n", sec, ret); 432 goto out; 433 } 434 n_sec -= len; 435 sec += len; 436 p_buf += len << 9; 437 } 438 out: 439 mutex_unlock(&p_dev->lock); 440 if (!ret) 441 ret = total_sec; 442 443 return ret; 444 } 445 446 static int snor_read_id(u8 *data) 447 { 448 int ret; 449 union SFCCMD_DATA sfcmd; 450 451 sfcmd.d32 = 0; 452 sfcmd.b.cmd = CMD_READ_JEDECID; 453 sfcmd.b.datasize = 3; 454 455 ret = sfc_request(sfcmd.d32, 0, 0, data); 456 457 return ret; 458 } 459 460 static int snor_read_parameter(u32 addr, u8 *data) 461 { 462 int ret; 463 union SFCCMD_DATA sfcmd; 464 465 sfcmd.d32 = 0; 466 sfcmd.b.cmd = CMD_READ_PARAMETER; 467 sfcmd.b.datasize = 1; 468 sfcmd.b.addrbits = SFC_ADDR_24BITS; 469 sfcmd.b.dummybits = 8; 470 471 ret = sfc_request(sfcmd.d32, 0, addr, data); 472 473 return ret; 474 } 475 476 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 477 { 478 return p_dev->capacity; 479 } 480 481 static void snor_print_spi_chip_info(struct SFNOR_DEV *p_dev) 482 { 483 PRINT_SFC_I("addr_mode: %x\n", p_dev->addr_mode); 484 PRINT_SFC_I("read_lines: %x\n", p_dev->read_lines); 485 PRINT_SFC_I("prog_lines: %x\n", p_dev->prog_lines); 486 PRINT_SFC_I("read_cmd: %x\n", p_dev->read_cmd); 487 PRINT_SFC_I("prog_cmd: %x\n", p_dev->prog_cmd); 488 PRINT_SFC_I("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 489 PRINT_SFC_I("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 490 } 491 492 static struct flash_info *snor_get_flash_info(u8 *flash_id) 493 { 494 u32 i; 495 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 496 497 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 498 if (spi_flash_tbl[i].id == id) 499 return &spi_flash_tbl[i]; 500 } 501 return NULL; 502 } 503 504 /* Adjust flash info in ram base on parameter */ 505 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 506 { 507 u32 addr; 508 u8 para_version; 509 510 if (spi_flash_info->id == 0xc84019) { 511 addr = 0x09; 512 snor_read_parameter(addr, ¶_version); 513 if (para_version == 0x06) { 514 spi_flash_info->QE_bits = 9; 515 spi_flash_info->prog_cmd_4 = 0x34; 516 } 517 } 518 return 0; 519 } 520 521 int snor_init(struct SFNOR_DEV *p_dev) 522 { 523 u32 i; 524 u8 id_byte[5]; 525 int err; 526 527 memset(p_dev, 0, sizeof(struct SFNOR_DEV)); 528 snor_read_id(id_byte); 529 PRINT_SFC_E("sfc nor id: %x %x %x\n", 530 id_byte[0], id_byte[1], id_byte[2]); 531 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) { 532 err = SFC_ERROR; 533 goto err_out; 534 } 535 536 p_dev->manufacturer = id_byte[0]; 537 p_dev->mem_type = id_byte[1]; 538 539 mutex_init(&p_dev->lock); 540 g_spi_flash_info = snor_get_flash_info(id_byte); 541 if (g_spi_flash_info) { 542 snor_flash_info_adjust(g_spi_flash_info); 543 p_dev->capacity = 1 << g_spi_flash_info->density; 544 p_dev->blk_size = g_spi_flash_info->block_size; 545 p_dev->page_size = NOR_SECS_PAGE; 546 p_dev->read_cmd = g_spi_flash_info->read_cmd; 547 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 548 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 549 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 550 p_dev->prog_lines = DATA_LINES_X1; 551 p_dev->read_lines = DATA_LINES_X1; 552 p_dev->QE_bits = g_spi_flash_info->QE_bits; 553 554 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 555 if (i == 0) 556 p_dev->write_status = snor_write_status; 557 else 558 p_dev->write_status = snor_write_status2; 559 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 560 if (snor_enable_QE(p_dev) == SFC_OK) { 561 p_dev->read_lines = DATA_LINES_X4; 562 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 563 } 564 } 565 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 566 p_dev->read_lines == DATA_LINES_X4) { 567 p_dev->prog_lines = DATA_LINES_X4; 568 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 569 } 570 571 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 572 p_dev->addr_mode = ADDR_MODE_4BYTE; 573 574 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 575 snor_enter_4byte_mode(); 576 577 goto normal_out; 578 } 579 580 for (i = 0; i < sizeof(sfnor_dev_code); i++) { 581 if (id_byte[2] == sfnor_dev_code[i]) { 582 p_dev->capacity = sfnor_capacity[i] >> 9; 583 break; 584 } 585 } 586 587 if (i >= sizeof(sfnor_dev_code)) { 588 err = SFC_ERROR; 589 goto err_out; 590 } 591 592 p_dev->QE_bits = 9; 593 p_dev->blk_size = NOR_SECS_BLK; 594 p_dev->page_size = NOR_SECS_PAGE; 595 p_dev->read_cmd = CMD_READ_DATA; 596 p_dev->prog_cmd = CMD_PAGE_PROG; 597 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 598 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 599 p_dev->write_status = snor_write_status2; 600 #if (SNOR_4BIT_DATA_DETECT_EN) 601 snor_set_dlines(p_dev, DATA_LINES_X4); 602 #endif 603 604 normal_out: 605 snor_print_spi_chip_info(p_dev); 606 607 return SFC_OK; 608 609 err_out: 610 return err; 611 } 612 613