1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C*/ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 25 /* GD25B512MEYIG */ 26 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 0, 0 }, 27 28 /* W25Q64JVSSIQ */ 29 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 30 /* W25Q128FV and W25Q128JV*/ 31 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 32 /* W25Q256F/J */ 33 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 34 /* W25Q256JWEQ*/ 35 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 36 /* W25Q64FWSSIG */ 37 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 38 /* W25Q128JVSIM */ 39 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 40 /* W25Q256JVEM */ 41 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 42 43 /* MX25L3233FM2I-08G */ 44 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 45 /* MX25L6433F */ 46 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 47 /* MX25L12835E/F MX25L12833FMI-10G */ 48 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 49 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 50 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 51 /* MX25L51245GMI */ 52 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 53 /* MX25U51245G */ 54 { 0xc2253a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 55 56 /* XM25QH32C */ 57 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 58 /* XM25QH64B */ 59 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 60 /* XM25QH128B */ 61 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 62 /* XM25QH(QU)256B */ 63 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 64 /* XM25QH64A */ 65 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 66 67 /* XT25F128A XM25QH128A */ 68 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 69 /* XT25F64BSSIGU-5 */ 70 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 71 /* XT25F128BSSIGU */ 72 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 73 74 /* EN25QH64A */ 75 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 76 /* EN25QH128A */ 77 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 78 /* EN25QH32B */ 79 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 80 /* EN25S32A */ 81 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 82 /* EN25S64A */ 83 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 84 /* EN25QH256A */ 85 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 86 87 /* ZB25VQ64 */ 88 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 89 /* ZB25VQ128 */ 90 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 91 /* ZB25LQ128 */ 92 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 93 94 /* BH25Q128AS */ 95 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 15, 9, 0 }, 96 /* BH25Q64BS */ 97 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 14, 9, 0 }, 98 99 /* FM25Q128A */ 100 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 101 /* FM25Q64-SOB-T-G */ 102 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 103 104 /* FM25Q64A */ 105 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 106 /* P25Q64H */ 107 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 108 }; 109 110 static int snor_write_en(void) 111 { 112 int ret; 113 struct rk_sfc_op op; 114 115 op.sfcmd.d32 = 0; 116 op.sfcmd.b.cmd = CMD_WRITE_EN; 117 118 op.sfctrl.d32 = 0; 119 120 ret = sfc_request(&op, 0, NULL, 0); 121 122 return ret; 123 } 124 125 int snor_reset_device(void) 126 { 127 struct rk_sfc_op op; 128 129 op.sfcmd.d32 = 0; 130 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 131 132 op.sfctrl.d32 = 0; 133 sfc_request(&op, 0, NULL, 0); 134 135 op.sfcmd.d32 = 0; 136 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 137 138 op.sfctrl.d32 = 0; 139 sfc_request(&op, 0, NULL, 0); 140 /* tRST=30us , delay 1ms here */ 141 sfc_delay(1000); 142 143 return SFC_OK; 144 } 145 146 static int snor_enter_4byte_mode(void) 147 { 148 int ret; 149 struct rk_sfc_op op; 150 151 op.sfcmd.d32 = 0; 152 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 153 154 op.sfctrl.d32 = 0; 155 156 ret = sfc_request(&op, 0, NULL, 0); 157 return ret; 158 } 159 160 static int snor_read_status(u32 reg_index, u8 *status) 161 { 162 int ret; 163 struct rk_sfc_op op; 164 u8 read_stat_cmd[] = {CMD_READ_STATUS, 165 CMD_READ_STATUS2, CMD_READ_STATUS3}; 166 op.sfcmd.d32 = 0; 167 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 168 169 op.sfctrl.d32 = 0; 170 ret = sfc_request(&op, 0, status, 1); 171 172 return ret; 173 } 174 175 static int snor_wait_busy(int timeout) 176 { 177 int ret; 178 struct rk_sfc_op op; 179 int i; 180 u32 status; 181 182 op.sfcmd.d32 = 0; 183 op.sfcmd.b.cmd = CMD_READ_STATUS; 184 185 op.sfctrl.d32 = 0; 186 187 for (i = 0; i < timeout; i++) { 188 ret = sfc_request(&op, 0, &status, 1); 189 if (ret != SFC_OK) 190 return ret; 191 192 if ((status & 0x01) == 0) 193 return SFC_OK; 194 195 sfc_delay(1); 196 } 197 rkflash_print_error("%s error %x\n", __func__, timeout); 198 199 return SFC_BUSY_TIMEOUT; 200 } 201 202 static int snor_write_status2(u32 reg_index, u8 status) 203 { 204 int ret; 205 struct rk_sfc_op op; 206 u8 status2[2]; 207 208 status2[reg_index] = status; 209 if (reg_index == 0) 210 ret = snor_read_status(2, &status2[1]); 211 else 212 ret = snor_read_status(0, &status2[0]); 213 if (ret != SFC_OK) 214 return ret; 215 216 snor_write_en(); 217 218 op.sfcmd.d32 = 0; 219 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 220 op.sfcmd.b.rw = SFC_WRITE; 221 222 op.sfctrl.d32 = 0; 223 224 ret = sfc_request(&op, 0, &status2[0], 2); 225 if (ret != SFC_OK) 226 return ret; 227 228 ret = snor_wait_busy(10000); /* 10ms */ 229 230 return ret; 231 } 232 233 static int snor_write_status1(u32 reg_index, u8 status) 234 { 235 int ret; 236 struct rk_sfc_op op; 237 u8 status2[2]; 238 u8 read_index; 239 240 status2[reg_index] = status; 241 read_index = (reg_index == 0) ? 1 : 0; 242 ret = snor_read_status(read_index, &status2[read_index]); 243 if (ret != SFC_OK) 244 return ret; 245 246 snor_write_en(); 247 248 op.sfcmd.d32 = 0; 249 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 250 op.sfcmd.b.rw = SFC_WRITE; 251 252 op.sfctrl.d32 = 0; 253 254 ret = sfc_request(&op, 0, &status2[0], 2); 255 if (ret != SFC_OK) 256 return ret; 257 258 ret = snor_wait_busy(10000); /* 10ms */ 259 260 return ret; 261 } 262 263 static int snor_write_status(u32 reg_index, u8 status) 264 { 265 int ret; 266 struct rk_sfc_op op; 267 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 268 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 269 snor_write_en(); 270 op.sfcmd.d32 = 0; 271 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 272 op.sfcmd.b.rw = SFC_WRITE; 273 274 op.sfctrl.d32 = 0; 275 276 ret = sfc_request(&op, 0, &status, 1); 277 if (ret != SFC_OK) 278 return ret; 279 280 ret = snor_wait_busy(10000); /* 10ms */ 281 282 return ret; 283 } 284 285 int snor_erase(struct SFNOR_DEV *p_dev, 286 u32 addr, 287 enum NOR_ERASE_TYPE erase_type) 288 { 289 int ret; 290 struct rk_sfc_op op; 291 int timeout[] = {400, 2000, 40000}; /* ms */ 292 293 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 294 295 if (erase_type > ERASE_CHIP) 296 return SFC_PARAM_ERR; 297 298 op.sfcmd.d32 = 0; 299 if (erase_type == ERASE_BLOCK64K) 300 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 301 else if (erase_type == ERASE_SECTOR) 302 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 303 else 304 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 305 306 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 307 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 308 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 309 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 310 311 op.sfctrl.d32 = 0; 312 313 snor_write_en(); 314 315 ret = sfc_request(&op, addr, NULL, 0); 316 if (ret != SFC_OK) 317 return ret; 318 319 ret = snor_wait_busy(timeout[erase_type] * 1000); 320 return ret; 321 } 322 323 int snor_prog_page(struct SFNOR_DEV *p_dev, 324 u32 addr, 325 void *p_data, 326 u32 size) 327 { 328 int ret; 329 struct rk_sfc_op op; 330 331 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 332 333 op.sfcmd.d32 = 0; 334 op.sfcmd.b.cmd = p_dev->prog_cmd; 335 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 336 op.sfcmd.b.rw = SFC_WRITE; 337 338 op.sfctrl.d32 = 0; 339 op.sfctrl.b.datalines = p_dev->prog_lines; 340 op.sfctrl.b.enbledma = 1; 341 if (p_dev->prog_lines == DATA_LINES_X4) 342 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 343 344 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 345 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 346 347 snor_write_en(); 348 349 ret = sfc_request(&op, addr, p_data, size); 350 if (ret != SFC_OK) 351 return ret; 352 353 ret = snor_wait_busy(10000); 354 355 return ret; 356 } 357 358 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 359 { 360 int ret = SFC_OK; 361 u32 page_size, len; 362 u8 *p_buf = (u8 *)p_data; 363 364 page_size = NOR_PAGE_SIZE; 365 while (size) { 366 len = page_size < size ? page_size : size; 367 ret = snor_prog_page(p_dev, addr, p_buf, len); 368 if (ret != SFC_OK) 369 return ret; 370 371 size -= len; 372 addr += len; 373 p_buf += len; 374 } 375 376 return ret; 377 } 378 379 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 380 { 381 int ret = SFC_OK; 382 int reg_index; 383 int bit_offset; 384 u8 status; 385 386 reg_index = p_dev->QE_bits >> 3; 387 bit_offset = p_dev->QE_bits & 0x7; 388 ret = snor_read_status(reg_index, &status); 389 if (ret != SFC_OK) 390 return ret; 391 392 if (status & (1 << bit_offset)) /* is QE bit set */ 393 return SFC_OK; 394 395 status |= (1 << bit_offset); 396 397 return p_dev->write_status(reg_index, status); 398 } 399 400 int snor_disable_QE(struct SFNOR_DEV *p_dev) 401 { 402 int ret = SFC_OK; 403 int reg_index; 404 int bit_offset; 405 u8 status; 406 407 reg_index = p_dev->QE_bits >> 3; 408 bit_offset = p_dev->QE_bits & 0x7; 409 ret = snor_read_status(reg_index, &status); 410 if (ret != SFC_OK) 411 return ret; 412 413 if (!(status & (1 << bit_offset))) 414 return SFC_OK; 415 416 status &= ~(1 << bit_offset); 417 418 return p_dev->write_status(reg_index, status); 419 } 420 421 int snor_read_data(struct SFNOR_DEV *p_dev, 422 u32 addr, 423 void *p_data, 424 u32 size) 425 { 426 int ret; 427 struct rk_sfc_op op; 428 429 op.sfcmd.d32 = 0; 430 op.sfcmd.b.cmd = p_dev->read_cmd; 431 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 432 433 op.sfctrl.d32 = 0; 434 op.sfctrl.b.datalines = p_dev->read_lines; 435 if (!(size & 0x3) && size >= 4) 436 op.sfctrl.b.enbledma = 1; 437 438 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 439 p_dev->read_cmd == CMD_FAST_READ_X4 || 440 p_dev->read_cmd == CMD_FAST_READ_X2 || 441 p_dev->read_cmd == CMD_FAST_4READ_X4) { 442 op.sfcmd.b.dummybits = 8; 443 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 444 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 445 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 446 op.sfcmd.b.dummybits = 4; 447 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 448 } 449 450 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 451 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 452 453 ret = sfc_request(&op, addr, p_data, size); 454 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 455 456 return ret; 457 } 458 459 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 460 { 461 int ret = SFC_OK; 462 u32 addr, size, len; 463 u8 *p_buf = (u8 *)p_data; 464 465 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 466 467 if ((sec + n_sec) > p_dev->capacity) 468 return SFC_PARAM_ERR; 469 470 addr = sec << 9; 471 size = n_sec << 9; 472 while (size) { 473 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 474 ret = snor_read_data(p_dev, addr, p_buf, len); 475 if (ret != SFC_OK) { 476 rkflash_print_error("snor_read_data %x ret= %x\n", 477 addr >> 9, ret); 478 goto out; 479 } 480 481 size -= len; 482 addr += len; 483 p_buf += len; 484 } 485 out: 486 if (!ret) 487 ret = n_sec; 488 489 return ret; 490 } 491 492 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 493 { 494 int ret = SFC_OK; 495 u32 len, blk_size, offset; 496 u8 *p_buf = (u8 *)p_data; 497 u32 total_sec = n_sec; 498 499 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 500 501 if ((sec + n_sec) > p_dev->capacity) 502 return SFC_PARAM_ERR; 503 504 while (n_sec) { 505 if (sec < 512 || sec >= p_dev->capacity - 512) 506 blk_size = 8; 507 else 508 blk_size = p_dev->blk_size; 509 510 offset = (sec & (blk_size - 1)); 511 if (!offset) { 512 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 513 ERASE_SECTOR : ERASE_BLOCK64K); 514 if (ret != SFC_OK) { 515 rkflash_print_error("snor_erase %x ret= %x\n", 516 sec, ret); 517 goto out; 518 } 519 } 520 len = (blk_size - offset) < n_sec ? 521 (blk_size - offset) : n_sec; 522 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 523 if (ret != SFC_OK) { 524 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 525 goto out; 526 } 527 n_sec -= len; 528 sec += len; 529 p_buf += len << 9; 530 } 531 out: 532 if (!ret) 533 ret = total_sec; 534 535 return ret; 536 } 537 538 int snor_read_id(u8 *data) 539 { 540 int ret; 541 struct rk_sfc_op op; 542 543 op.sfcmd.d32 = 0; 544 op.sfcmd.b.cmd = CMD_READ_JEDECID; 545 546 op.sfctrl.d32 = 0; 547 548 ret = sfc_request(&op, 0, data, 3); 549 550 return ret; 551 } 552 553 static int snor_read_parameter(u32 addr, u8 *data) 554 { 555 int ret; 556 struct rk_sfc_op op; 557 558 op.sfcmd.d32 = 0; 559 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 560 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 561 op.sfcmd.b.dummybits = 8; 562 563 op.sfctrl.d32 = 0; 564 565 ret = sfc_request(&op, addr, data, 1); 566 567 return ret; 568 } 569 570 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 571 { 572 return p_dev->capacity; 573 } 574 575 static struct flash_info *snor_get_flash_info(u8 *flash_id) 576 { 577 u32 i; 578 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 579 580 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 581 if (spi_flash_tbl[i].id == id) 582 return &spi_flash_tbl[i]; 583 } 584 return NULL; 585 } 586 587 /* Adjust flash info in ram base on parameter */ 588 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 589 { 590 u32 addr; 591 u8 para_version; 592 593 if (spi_flash_info->id == 0xc84019) { 594 addr = 0x09; 595 snor_read_parameter(addr, ¶_version); 596 if (para_version == 0x06) { 597 spi_flash_info->QE_bits = 9; 598 spi_flash_info->prog_cmd_4 = 0x34; 599 } 600 } 601 return 0; 602 } 603 604 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 605 struct flash_info *g_spi_flash_info) 606 { 607 int i, ret; 608 609 if (g_spi_flash_info) { 610 snor_flash_info_adjust(g_spi_flash_info); 611 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 612 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 613 p_dev->capacity = 1 << g_spi_flash_info->density; 614 p_dev->blk_size = g_spi_flash_info->block_size; 615 p_dev->page_size = NOR_SECS_PAGE; 616 p_dev->read_cmd = g_spi_flash_info->read_cmd; 617 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 618 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 619 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 620 p_dev->prog_lines = DATA_LINES_X1; 621 p_dev->read_lines = DATA_LINES_X1; 622 p_dev->QE_bits = g_spi_flash_info->QE_bits; 623 p_dev->addr_mode = ADDR_MODE_3BYTE; 624 625 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 626 if (i == 0) 627 p_dev->write_status = snor_write_status; 628 else if (i == 1) 629 p_dev->write_status = snor_write_status1; 630 else if (i == 2) 631 p_dev->write_status = snor_write_status2; 632 633 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 634 ret = SFC_OK; 635 if (g_spi_flash_info->QE_bits) 636 ret = snor_enable_QE(p_dev); 637 if (ret == SFC_OK) { 638 p_dev->read_lines = DATA_LINES_X4; 639 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 640 } 641 } 642 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 643 p_dev->read_lines == DATA_LINES_X4) { 644 p_dev->prog_lines = DATA_LINES_X4; 645 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 646 } 647 648 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 649 p_dev->addr_mode = ADDR_MODE_4BYTE; 650 651 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 652 snor_enter_4byte_mode(); 653 } 654 655 return SFC_OK; 656 } 657 658 int snor_init(struct SFNOR_DEV *p_dev) 659 { 660 struct flash_info *g_spi_flash_info; 661 u8 id_byte[5]; 662 663 if (!p_dev) 664 return SFC_PARAM_ERR; 665 666 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 667 p_dev->max_iosize = sfc_get_max_iosize(); 668 669 snor_read_id(id_byte); 670 rkflash_print_error("sfc nor id: %x %x %x\n", 671 id_byte[0], id_byte[1], id_byte[2]); 672 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 673 return SFC_ERROR; 674 675 g_spi_flash_info = snor_get_flash_info(id_byte); 676 if (g_spi_flash_info) { 677 snor_parse_flash_table(p_dev, g_spi_flash_info); 678 } else { 679 p_dev->manufacturer = id_byte[0]; 680 p_dev->mem_type = id_byte[1]; 681 p_dev->capacity = 1 << (id_byte[2] - 9); 682 p_dev->QE_bits = 0; 683 p_dev->blk_size = NOR_SECS_BLK; 684 p_dev->page_size = NOR_SECS_PAGE; 685 p_dev->read_cmd = CMD_READ_DATA; 686 p_dev->prog_cmd = CMD_PAGE_PROG; 687 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 688 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 689 p_dev->prog_lines = DATA_LINES_X1; 690 p_dev->read_lines = DATA_LINES_X1; 691 p_dev->write_status = snor_write_status; 692 snor_reset_device(); 693 } 694 695 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 696 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 697 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 698 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 699 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 700 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 701 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 702 rkflash_print_info("capacity: %x\n", p_dev->capacity); 703 704 return SFC_OK; 705 } 706 707 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 708 struct snor_info_packet *packet) 709 { 710 struct flash_info g_spi_flash_info; 711 u8 id_byte[5]; 712 int ret; 713 714 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 715 return SFC_PARAM_ERR; 716 717 snor_read_id(id_byte); 718 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 719 return SFC_ERROR; 720 721 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 722 g_spi_flash_info.block_size = NOR_SECS_BLK; 723 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 724 g_spi_flash_info.read_cmd = packet->read_cmd; 725 g_spi_flash_info.prog_cmd = packet->prog_cmd; 726 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 727 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 728 if (id_byte[2] >= 0x19) 729 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 730 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 731 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 732 g_spi_flash_info.feature = packet->feature; 733 g_spi_flash_info.density = id_byte[2] - 9; 734 g_spi_flash_info.QE_bits = packet->QE_bits; 735 736 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 737 738 return ret; 739 } 740 741