1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B/C/E */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C/E */ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D/E */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 25 /* GD25LQ64C */ 26 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 27 /* GD25LQ32E */ 28 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 29 /* GD25B512MEYIG */ 30 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 31 /* GD25LQ255E and GD25LQ256C */ 32 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 }, 33 /* GD25LB512MEYIG */ 34 { 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 35 36 /* W25Q32JV */ 37 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 38 /* W25Q64JVSSIQ */ 39 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 40 /* W25Q128FV and W25Q128JV*/ 41 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 42 /* W25Q256F/J */ 43 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 44 /* W25Q32JW */ 45 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 46 /* W25Q64FWSSIG */ 47 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 48 /* W25Q128JWSQ */ 49 { 0xef6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 50 /* W25Q256JWEQ*/ 51 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 52 /* W25Q128JVSIM */ 53 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 54 /* W25Q256JVEM */ 55 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 56 57 /* MX25L3233FM2I-08G */ 58 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 59 /* MX25L6433F */ 60 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 61 /* MX25L12835E/F MX25L12833FMI-10G */ 62 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 63 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */ 64 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 65 /* MX25L51245GMI */ 66 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 67 /* MX25U51245G */ 68 { 0xc2253a, 128, 8, 0x0C, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 69 /* MX25U3232F */ 70 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 71 /* MX25U6432F */ 72 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 73 /* MX25U12832F */ 74 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 75 /* MX25U25645GZ4I-00 */ 76 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 77 78 /* XM25QH32C */ 79 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 80 /* XM25QH64C */ 81 { 0x204017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 82 /* XM25QH128C */ 83 { 0x204018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 15, 9, 0 }, 84 /* XM25QH256C */ 85 { 0x204019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 86 /* XM25QH64B */ 87 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 88 /* XM25QH128B */ 89 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 90 /* XM25QH(QU)256B */ 91 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 92 /* XM25QH64A */ 93 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 94 /* XM25QU128C */ 95 { 0x204118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 96 /* XM25QU64C */ 97 { 0x204117, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 98 99 /* XT25F128A XM25QH128A */ 100 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 101 /* XT25F64BSSIGU-5 XT25F64F */ 102 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 103 /* XT25F128BSSIGU */ 104 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 105 /* XT25F256BSFIGU */ 106 { 0x0b4019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 107 /* XT25F32BS */ 108 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 109 /* XT25F16BS */ 110 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 111 112 /* EN25QH64A */ 113 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 114 /* EN25QH128A */ 115 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 116 /* EN25QH32B */ 117 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 118 /* EN25S32A */ 119 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 120 /* EN25S64A */ 121 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 122 /* EN25QH256A */ 123 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 124 125 /* P25Q64H */ 126 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 127 /* P25Q128H */ 128 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 129 /* P25Q16H-SUH-IT */ 130 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 131 /* P25Q32SL P25Q32SH-SSH-IT */ 132 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 133 /* PY25Q128H */ 134 { 0x852018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 135 136 /* ZB25VQ64 */ 137 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 138 /* ZB25VQ128 */ 139 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 140 /* ZB25LQ128 */ 141 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 142 143 /* BH25Q128AS */ 144 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 145 /* BH25Q64BS */ 146 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 147 148 /* FM25Q128A */ 149 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 150 /* FM25Q64-SOB-T-G */ 151 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 152 153 /* FM25Q64A */ 154 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 155 /* FM25M4AA */ 156 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 157 /* FM25M64C */ 158 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 159 160 /* DS25M4AB-1AIB4 */ 161 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 162 163 /* GM25Q128A */ 164 { 0x1c4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 165 }; 166 167 static int snor_write_en(void) 168 { 169 int ret; 170 struct rk_sfc_op op; 171 172 op.sfcmd.d32 = 0; 173 op.sfcmd.b.cmd = CMD_WRITE_EN; 174 175 op.sfctrl.d32 = 0; 176 177 ret = sfc_request(&op, 0, NULL, 0); 178 179 return ret; 180 } 181 182 int snor_reset_device(void) 183 { 184 struct rk_sfc_op op; 185 186 op.sfcmd.d32 = 0; 187 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 188 189 op.sfctrl.d32 = 0; 190 sfc_request(&op, 0, NULL, 0); 191 192 op.sfcmd.d32 = 0; 193 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 194 195 op.sfctrl.d32 = 0; 196 sfc_request(&op, 0, NULL, 0); 197 /* tRST=30us , delay 1ms here */ 198 sfc_delay(1000); 199 200 return SFC_OK; 201 } 202 203 static int snor_enter_4byte_mode(void) 204 { 205 int ret; 206 struct rk_sfc_op op; 207 208 op.sfcmd.d32 = 0; 209 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 210 211 op.sfctrl.d32 = 0; 212 213 ret = sfc_request(&op, 0, NULL, 0); 214 return ret; 215 } 216 217 static int snor_read_status(u32 reg_index, u8 *status) 218 { 219 int ret; 220 struct rk_sfc_op op; 221 u8 read_stat_cmd[] = {CMD_READ_STATUS, 222 CMD_READ_STATUS2, CMD_READ_STATUS3}; 223 op.sfcmd.d32 = 0; 224 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 225 226 op.sfctrl.d32 = 0; 227 ret = sfc_request(&op, 0, status, 1); 228 229 return ret; 230 } 231 232 static int snor_wait_busy(int timeout) 233 { 234 int ret; 235 struct rk_sfc_op op; 236 int i; 237 u32 status; 238 239 op.sfcmd.d32 = 0; 240 op.sfcmd.b.cmd = CMD_READ_STATUS; 241 242 op.sfctrl.d32 = 0; 243 244 for (i = 0; i < timeout; i++) { 245 ret = sfc_request(&op, 0, &status, 1); 246 if (ret != SFC_OK) 247 return ret; 248 249 if ((status & 0x01) == 0) 250 return SFC_OK; 251 252 sfc_delay(1); 253 } 254 rkflash_print_error("%s error %x\n", __func__, timeout); 255 256 return SFC_BUSY_TIMEOUT; 257 } 258 259 static int snor_write_status2(u32 reg_index, u8 status) 260 { 261 int ret; 262 struct rk_sfc_op op; 263 u8 status2[2]; 264 265 status2[reg_index] = status; 266 if (reg_index == 0) 267 ret = snor_read_status(2, &status2[1]); 268 else 269 ret = snor_read_status(0, &status2[0]); 270 if (ret != SFC_OK) 271 return ret; 272 273 snor_write_en(); 274 275 op.sfcmd.d32 = 0; 276 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 277 op.sfcmd.b.rw = SFC_WRITE; 278 279 op.sfctrl.d32 = 0; 280 281 ret = sfc_request(&op, 0, &status2[0], 2); 282 if (ret != SFC_OK) 283 return ret; 284 285 ret = snor_wait_busy(10000); /* 10ms */ 286 287 return ret; 288 } 289 290 static int snor_write_status1(u32 reg_index, u8 status) 291 { 292 int ret; 293 struct rk_sfc_op op; 294 u8 status2[2]; 295 u8 read_index; 296 297 status2[reg_index] = status; 298 read_index = (reg_index == 0) ? 1 : 0; 299 ret = snor_read_status(read_index, &status2[read_index]); 300 if (ret != SFC_OK) 301 return ret; 302 303 snor_write_en(); 304 305 op.sfcmd.d32 = 0; 306 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 307 op.sfcmd.b.rw = SFC_WRITE; 308 309 op.sfctrl.d32 = 0; 310 311 ret = sfc_request(&op, 0, &status2[0], 2); 312 if (ret != SFC_OK) 313 return ret; 314 315 ret = snor_wait_busy(10000); /* 10ms */ 316 317 return ret; 318 } 319 320 static int snor_write_status(u32 reg_index, u8 status) 321 { 322 int ret; 323 struct rk_sfc_op op; 324 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 325 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 326 snor_write_en(); 327 op.sfcmd.d32 = 0; 328 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 329 op.sfcmd.b.rw = SFC_WRITE; 330 331 op.sfctrl.d32 = 0; 332 333 ret = sfc_request(&op, 0, &status, 1); 334 if (ret != SFC_OK) 335 return ret; 336 337 ret = snor_wait_busy(10000); /* 10ms */ 338 339 return ret; 340 } 341 342 int snor_erase(struct SFNOR_DEV *p_dev, 343 u32 addr, 344 enum NOR_ERASE_TYPE erase_type) 345 { 346 int ret; 347 struct rk_sfc_op op; 348 int timeout[] = {400, 2000, 40000}; /* ms */ 349 350 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 351 352 if (erase_type > ERASE_CHIP) 353 return SFC_PARAM_ERR; 354 355 op.sfcmd.d32 = 0; 356 if (erase_type == ERASE_BLOCK64K) 357 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 358 else if (erase_type == ERASE_SECTOR) 359 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 360 else 361 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 362 363 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 364 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 365 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 366 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 367 368 op.sfctrl.d32 = 0; 369 370 snor_write_en(); 371 372 ret = sfc_request(&op, addr, NULL, 0); 373 if (ret != SFC_OK) 374 return ret; 375 376 ret = snor_wait_busy(timeout[erase_type] * 1000); 377 return ret; 378 } 379 380 int snor_prog_page(struct SFNOR_DEV *p_dev, 381 u32 addr, 382 void *p_data, 383 u32 size) 384 { 385 int ret; 386 struct rk_sfc_op op; 387 388 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 389 390 op.sfcmd.d32 = 0; 391 op.sfcmd.b.cmd = p_dev->prog_cmd; 392 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 393 op.sfcmd.b.rw = SFC_WRITE; 394 395 op.sfctrl.d32 = 0; 396 op.sfctrl.b.datalines = p_dev->prog_lines; 397 op.sfctrl.b.enbledma = 1; 398 op.sfctrl.b.addrlines = p_dev->prog_addr_lines; 399 400 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 401 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 402 403 snor_write_en(); 404 405 ret = sfc_request(&op, addr, p_data, size); 406 if (ret != SFC_OK) 407 return ret; 408 409 ret = snor_wait_busy(10000); 410 411 return ret; 412 } 413 414 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 415 { 416 int ret = SFC_OK; 417 u32 page_size, len; 418 u8 *p_buf = (u8 *)p_data; 419 420 page_size = NOR_PAGE_SIZE; 421 while (size) { 422 len = page_size < size ? page_size : size; 423 ret = snor_prog_page(p_dev, addr, p_buf, len); 424 if (ret != SFC_OK) 425 return ret; 426 427 size -= len; 428 addr += len; 429 p_buf += len; 430 } 431 432 return ret; 433 } 434 435 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 436 { 437 int ret = SFC_OK; 438 int reg_index; 439 int bit_offset; 440 u8 status; 441 442 reg_index = p_dev->QE_bits >> 3; 443 bit_offset = p_dev->QE_bits & 0x7; 444 ret = snor_read_status(reg_index, &status); 445 if (ret != SFC_OK) 446 return ret; 447 448 if (status & (1 << bit_offset)) /* is QE bit set */ 449 return SFC_OK; 450 451 status |= (1 << bit_offset); 452 453 return p_dev->write_status(reg_index, status); 454 } 455 456 int snor_disable_QE(struct SFNOR_DEV *p_dev) 457 { 458 int ret = SFC_OK; 459 int reg_index; 460 int bit_offset; 461 u8 status; 462 463 reg_index = p_dev->QE_bits >> 3; 464 bit_offset = p_dev->QE_bits & 0x7; 465 ret = snor_read_status(reg_index, &status); 466 if (ret != SFC_OK) 467 return ret; 468 469 if (!(status & (1 << bit_offset))) 470 return SFC_OK; 471 472 status &= ~(1 << bit_offset); 473 474 return p_dev->write_status(reg_index, status); 475 } 476 477 int snor_read_data(struct SFNOR_DEV *p_dev, 478 u32 addr, 479 void *p_data, 480 u32 size) 481 { 482 int ret; 483 struct rk_sfc_op op; 484 485 op.sfcmd.d32 = 0; 486 op.sfcmd.b.cmd = p_dev->read_cmd; 487 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 488 489 op.sfctrl.d32 = 0; 490 op.sfctrl.b.datalines = p_dev->read_lines; 491 if (!(size & 0x3) && size >= 4) 492 op.sfctrl.b.enbledma = 1; 493 494 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 495 p_dev->read_cmd == CMD_PAGE_FASTREAD4B || 496 p_dev->read_cmd == CMD_FAST_READ_X4 || 497 p_dev->read_cmd == CMD_FAST_READ_X2 || 498 p_dev->read_cmd == CMD_FAST_4READ_X4) { 499 op.sfcmd.b.dummybits = 8; 500 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 501 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 502 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 503 op.sfcmd.b.dummybits = 4; 504 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 505 } 506 507 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 508 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 509 510 ret = sfc_request(&op, addr, p_data, size); 511 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 512 513 return ret; 514 } 515 516 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 517 { 518 int ret = SFC_OK; 519 u32 addr, size, len; 520 u8 *p_buf = (u8 *)p_data; 521 522 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 523 524 if ((sec + n_sec) > p_dev->capacity) 525 return SFC_PARAM_ERR; 526 527 addr = sec << 9; 528 size = n_sec << 9; 529 while (size) { 530 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 531 ret = snor_read_data(p_dev, addr, p_buf, len); 532 if (ret != SFC_OK) { 533 rkflash_print_error("snor_read_data %x ret= %x\n", 534 addr >> 9, ret); 535 goto out; 536 } 537 538 size -= len; 539 addr += len; 540 p_buf += len; 541 } 542 out: 543 if (!ret) 544 ret = n_sec; 545 546 return ret; 547 } 548 549 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 550 { 551 int ret = SFC_OK; 552 u32 len, blk_size, offset; 553 u8 *p_buf = (u8 *)p_data; 554 u32 total_sec = n_sec; 555 556 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 557 558 if ((sec + n_sec) > p_dev->capacity) 559 return SFC_PARAM_ERR; 560 561 while (n_sec) { 562 if (sec < 512 || sec >= p_dev->capacity - 512) 563 blk_size = 8; 564 else 565 blk_size = p_dev->blk_size; 566 567 offset = (sec & (blk_size - 1)); 568 if (!offset) { 569 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 570 ERASE_SECTOR : ERASE_BLOCK64K); 571 if (ret != SFC_OK) { 572 rkflash_print_error("snor_erase %x ret= %x\n", 573 sec, ret); 574 goto out; 575 } 576 } 577 len = (blk_size - offset) < n_sec ? 578 (blk_size - offset) : n_sec; 579 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 580 if (ret != SFC_OK) { 581 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 582 goto out; 583 } 584 n_sec -= len; 585 sec += len; 586 p_buf += len << 9; 587 } 588 out: 589 if (!ret) 590 ret = total_sec; 591 592 return ret; 593 } 594 595 int snor_read_id(u8 *data) 596 { 597 int ret; 598 struct rk_sfc_op op; 599 600 op.sfcmd.d32 = 0; 601 op.sfcmd.b.cmd = CMD_READ_JEDECID; 602 603 op.sfctrl.d32 = 0; 604 605 ret = sfc_request(&op, 0, data, 3); 606 607 return ret; 608 } 609 610 static int snor_read_parameter(u32 addr, u8 *data) 611 { 612 int ret; 613 struct rk_sfc_op op; 614 615 op.sfcmd.d32 = 0; 616 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 617 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 618 op.sfcmd.b.dummybits = 8; 619 620 op.sfctrl.d32 = 0; 621 622 ret = sfc_request(&op, addr, data, 1); 623 624 return ret; 625 } 626 627 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 628 { 629 return p_dev->capacity; 630 } 631 632 static struct flash_info *snor_get_flash_info(u8 *flash_id) 633 { 634 u32 i; 635 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 636 637 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 638 if (spi_flash_tbl[i].id == id) 639 return &spi_flash_tbl[i]; 640 } 641 return NULL; 642 } 643 644 /* Adjust flash info in ram base on parameter */ 645 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 646 { 647 u32 addr; 648 u8 para_version; 649 650 if (spi_flash_info->id == 0xc84019) { 651 addr = 0x09; 652 snor_read_parameter(addr, ¶_version); 653 if (para_version == 0x06) { 654 spi_flash_info->QE_bits = 9; 655 spi_flash_info->prog_cmd_4 = 0x34; 656 } 657 } 658 return 0; 659 } 660 661 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 662 struct flash_info *g_spi_flash_info) 663 { 664 int i, ret; 665 666 if (g_spi_flash_info) { 667 snor_flash_info_adjust(g_spi_flash_info); 668 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 669 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 670 p_dev->capacity = 1 << g_spi_flash_info->density; 671 p_dev->blk_size = g_spi_flash_info->block_size; 672 p_dev->page_size = NOR_SECS_PAGE; 673 p_dev->read_cmd = g_spi_flash_info->read_cmd; 674 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 675 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 676 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 677 p_dev->prog_lines = DATA_LINES_X1; 678 p_dev->read_lines = DATA_LINES_X1; 679 p_dev->QE_bits = g_spi_flash_info->QE_bits; 680 p_dev->addr_mode = ADDR_MODE_3BYTE; 681 682 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 683 if (i == 0) 684 p_dev->write_status = snor_write_status; 685 else if (i == 1) 686 p_dev->write_status = snor_write_status1; 687 else if (i == 2) 688 p_dev->write_status = snor_write_status2; 689 690 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 691 ret = SFC_OK; 692 if (g_spi_flash_info->QE_bits) 693 ret = snor_enable_QE(p_dev); 694 if (ret == SFC_OK) { 695 p_dev->read_lines = DATA_LINES_X4; 696 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 697 } 698 } 699 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 700 p_dev->read_lines == DATA_LINES_X4) { 701 p_dev->prog_lines = DATA_LINES_X4; 702 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 703 if ((p_dev->manufacturer == MID_MACRONIX) && 704 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 || 705 p_dev->prog_cmd == CMD_PAGE_PROG_4PP)) 706 p_dev->prog_addr_lines = DATA_LINES_X4; 707 } 708 709 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 710 p_dev->addr_mode = ADDR_MODE_4BYTE; 711 712 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 713 snor_enter_4byte_mode(); 714 } 715 716 return SFC_OK; 717 } 718 719 int snor_init(struct SFNOR_DEV *p_dev) 720 { 721 struct flash_info *g_spi_flash_info; 722 u8 id_byte[5]; 723 724 if (!p_dev) 725 return SFC_PARAM_ERR; 726 727 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 728 p_dev->max_iosize = sfc_get_max_iosize(); 729 730 snor_read_id(id_byte); 731 rkflash_print_error("sfc nor id: %x %x %x\n", 732 id_byte[0], id_byte[1], id_byte[2]); 733 if (0xFF == id_byte[0] || 0x00 == id_byte[0] || 0xFF == id_byte[1] || 0x00 == id_byte[1]) 734 return SFC_ERROR; 735 736 g_spi_flash_info = snor_get_flash_info(id_byte); 737 if (g_spi_flash_info) { 738 snor_parse_flash_table(p_dev, g_spi_flash_info); 739 } else { 740 pr_err("The device not support yet!\n"); 741 742 p_dev->manufacturer = id_byte[0]; 743 p_dev->mem_type = id_byte[1]; 744 p_dev->capacity = 1 << (id_byte[2] - 9); 745 p_dev->QE_bits = 0; 746 p_dev->blk_size = NOR_SECS_BLK; 747 p_dev->page_size = NOR_SECS_PAGE; 748 p_dev->read_cmd = CMD_READ_DATA; 749 p_dev->prog_cmd = CMD_PAGE_PROG; 750 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 751 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 752 p_dev->prog_lines = DATA_LINES_X1; 753 p_dev->prog_addr_lines = DATA_LINES_X1; 754 p_dev->read_lines = DATA_LINES_X1; 755 p_dev->write_status = snor_write_status; 756 snor_reset_device(); 757 } 758 759 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 760 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 761 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 762 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 763 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 764 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 765 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 766 rkflash_print_info("capacity: %x\n", p_dev->capacity); 767 768 return SFC_OK; 769 } 770 771 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 772 struct snor_info_packet *packet) 773 { 774 struct flash_info g_spi_flash_info; 775 u8 id_byte[5]; 776 int ret; 777 778 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 779 return SFC_PARAM_ERR; 780 781 snor_read_id(id_byte); 782 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 783 return SFC_ERROR; 784 785 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 786 g_spi_flash_info.block_size = NOR_SECS_BLK; 787 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 788 g_spi_flash_info.read_cmd = packet->read_cmd; 789 g_spi_flash_info.prog_cmd = packet->prog_cmd; 790 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 791 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 792 if (id_byte[2] >= 0x19) 793 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 794 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 795 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 796 g_spi_flash_info.feature = packet->feature; 797 g_spi_flash_info.density = id_byte[2] - 9; 798 g_spi_flash_info.QE_bits = packet->QE_bits; 799 800 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 801 802 return ret; 803 } 804 805