1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7 #include <linux/delay.h> 8 #include <linux/compat.h> 9 #include <linux/string.h> 10 11 #include "sfc_nor.h" 12 #include "rkflash_debug.h" 13 #include "rkflash_blk.h" 14 15 static struct flash_info spi_flash_tbl[] = { 16 /* GD25Q32B */ 17 {0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0}, 18 /* GD25Q64B */ 19 {0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0}, 20 /* GD25Q127C and GD25Q128C*/ 21 {0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 22 /* GD25Q256B */ 23 {0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0}, 24 /* GD25Q512MC */ 25 {0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0}, 26 /* 25Q128FV */ 27 {0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 28 /* 25Q256FV */ 29 {0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0}, 30 /* XT25F128A */ 31 {0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0}, 32 /* MX25L25635E/F */ 33 {0xc22019, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x30, 16, 6, 0}, 34 }; 35 36 static const u8 sfnor_dev_code[] = { 37 0x11, 38 0x12, 39 0x13, 40 0x14, 41 0x15, 42 0x16, 43 0x17, 44 0x18, 45 0x19 46 }; 47 48 static const u32 sfnor_capacity[] = { 49 0x20000, /* 128k-byte */ 50 0x40000, /* 256k-byte */ 51 0x80000, /* 512k-byte */ 52 0x100000, /* 1M-byte */ 53 0x200000, /* 2M-byte */ 54 0x400000, /* 4M-byte */ 55 0x800000, /* 8M-byte */ 56 0x1000000, /* 16M-byte */ 57 0x2000000 /* 32M-byte */ 58 }; 59 60 static struct flash_info *g_spi_flash_info; 61 62 static int snor_write_en(void) 63 { 64 int ret; 65 union SFCCMD_DATA sfcmd; 66 67 sfcmd.d32 = 0; 68 sfcmd.b.cmd = CMD_WRITE_EN; 69 70 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 71 72 return ret; 73 } 74 75 static int snor_enter_4byte_mode(void) 76 { 77 int ret; 78 union SFCCMD_DATA sfcmd; 79 80 sfcmd.d32 = 0; 81 sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 82 83 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 84 return ret; 85 } 86 87 static int snor_read_status(u32 reg_index, u8 *status) 88 { 89 int ret; 90 union SFCCMD_DATA sfcmd; 91 u8 read_stat_cmd[] = {CMD_READ_STATUS, 92 CMD_READ_STATUS2, CMD_READ_STATUS3}; 93 sfcmd.d32 = 0; 94 sfcmd.b.cmd = read_stat_cmd[reg_index]; 95 sfcmd.b.datasize = 1; 96 97 ret = sfc_request(sfcmd.d32, 0, 0, status); 98 99 return ret; 100 } 101 102 static int snor_wait_busy(int timeout) 103 { 104 int ret; 105 union SFCCMD_DATA sfcmd; 106 u32 i, status; 107 108 sfcmd.d32 = 0; 109 sfcmd.b.cmd = CMD_READ_STATUS; 110 sfcmd.b.datasize = 1; 111 112 for (i = 0; i < timeout; i++) { 113 ret = sfc_request(sfcmd.d32, 0, 0, &status); 114 if (ret != SFC_OK) 115 return ret; 116 117 if ((status & 0x01) == 0) 118 return SFC_OK; 119 120 sfc_delay(1); 121 } 122 PRINT_SFC_E("%s error %x\n", __func__, timeout); 123 124 return SFC_BUSY_TIMEOUT; 125 } 126 127 static int snor_write_status2(u32 reg_index, u8 status) 128 { 129 int ret; 130 union SFCCMD_DATA sfcmd; 131 u8 status2[2]; 132 u8 read_index; 133 134 status2[reg_index] = status; 135 read_index = (reg_index == 0) ? 1 : 0; 136 ret = snor_read_status(read_index, &status2[read_index]); 137 if (ret != SFC_OK) 138 return ret; 139 140 snor_write_en(); 141 142 sfcmd.d32 = 0; 143 sfcmd.b.cmd = CMD_WRITE_STATUS; 144 sfcmd.b.datasize = 2; 145 sfcmd.b.rw = SFC_WRITE; 146 147 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 148 if (ret != SFC_OK) 149 return ret; 150 151 ret = snor_wait_busy(10000); /* 10ms */ 152 153 return ret; 154 } 155 156 static int snor_write_status(u32 reg_index, u8 status) 157 { 158 int ret; 159 union SFCCMD_DATA sfcmd; 160 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 161 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 162 snor_write_en(); 163 sfcmd.d32 = 0; 164 sfcmd.b.cmd = write_stat_cmd[reg_index]; 165 sfcmd.b.datasize = 1; 166 sfcmd.b.rw = SFC_WRITE; 167 168 ret = sfc_request(sfcmd.d32, 0, 0, &status); 169 if (ret != SFC_OK) 170 return ret; 171 172 ret = snor_wait_busy(10000); /* 10ms */ 173 174 return ret; 175 } 176 177 static int snor_erase(struct SFNOR_DEV *p_dev, 178 u32 addr, 179 enum NOR_ERASE_TYPE erase_type) 180 { 181 int ret; 182 union SFCCMD_DATA sfcmd; 183 int timeout[] = {400, 2000, 40000}; /* ms */ 184 185 if (erase_type > ERASE_CHIP) 186 return SFC_PARAM_ERR; 187 188 sfcmd.d32 = 0; 189 if (erase_type == ERASE_BLOCK64K) 190 sfcmd.b.cmd = p_dev->blk_erase_cmd; 191 else if (erase_type == ERASE_SECTOR) 192 sfcmd.b.cmd = p_dev->sec_erase_cmd; 193 else 194 sfcmd.b.cmd = CMD_CHIP_ERASE; 195 196 sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 197 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 198 if ((p_dev->addr_mode == ADDR_MODE_4BYTE) && (erase_type != ERASE_CHIP)) 199 sfcmd.b.addrbits = SFC_ADDR_32BITS; 200 201 snor_write_en(); 202 203 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 204 if (ret != SFC_OK) 205 return ret; 206 207 ret = snor_wait_busy(timeout[erase_type] * 1000); 208 return ret; 209 } 210 211 static int snor_prog_page(struct SFNOR_DEV *p_dev, 212 u32 addr, 213 void *p_data, 214 u32 size) 215 { 216 int ret; 217 union SFCCMD_DATA sfcmd; 218 union SFCCTRL_DATA sfctrl; 219 220 sfcmd.d32 = 0; 221 sfcmd.b.cmd = p_dev->prog_cmd; 222 sfcmd.b.addrbits = SFC_ADDR_24BITS; 223 sfcmd.b.datasize = size; 224 sfcmd.b.rw = SFC_WRITE; 225 226 sfctrl.d32 = 0; 227 sfctrl.b.datalines = p_dev->prog_lines; 228 sfctrl.b.enbledma = 0; 229 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 230 sfctrl.b.addrlines = SFC_4BITS_LINE; 231 232 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 233 sfcmd.b.addrbits = SFC_ADDR_32BITS; 234 235 snor_write_en(); 236 237 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 238 if (ret != SFC_OK) 239 return ret; 240 241 ret = snor_wait_busy(10000); 242 243 return ret; 244 } 245 246 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 247 { 248 int ret = SFC_OK; 249 u32 page_size, len; 250 u8 *p_buf = (u8 *)p_data; 251 252 page_size = NOR_PAGE_SIZE; 253 while (size) { 254 len = page_size < size ? page_size : size; 255 ret = snor_prog_page(p_dev, addr, p_buf, len); 256 if (ret != SFC_OK) 257 return ret; 258 259 size -= len; 260 addr += len; 261 p_buf += len; 262 } 263 264 return ret; 265 } 266 267 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 268 { 269 int ret = SFC_OK; 270 int reg_index; 271 int bit_offset; 272 u8 status; 273 274 if (p_dev->manufacturer == MID_GIGADEV || 275 p_dev->manufacturer == MID_WINBOND) { 276 reg_index = p_dev->QE_bits >> 3; 277 bit_offset = p_dev->QE_bits & 0x7; 278 ret = snor_read_status(reg_index, &status); 279 if (ret != SFC_OK) 280 return ret; 281 282 if (status & (1 << bit_offset)) /* is QE bit set */ 283 return SFC_OK; 284 285 status |= (1 << bit_offset); 286 return p_dev->write_status(reg_index, status); 287 } 288 289 return ret; 290 } 291 292 #if (SNOR_4BIT_DATA_DETECT_EN) 293 static int snor_set_dlines(struct SFNOR_DEV *p_dev, enum SFC_DATA_LINES lines) 294 { 295 int ret; 296 u8 read_cmd[] = {CMD_FAST_READ_X1, CMD_FAST_READ_X2, CMD_FAST_READ_X4}; 297 298 if (lines == DATA_LINES_X4) { 299 ret = snor_enable_QE(p_dev); 300 if (ret != SFC_OK) 301 return ret; 302 } 303 304 p_dev->read_lines = lines; 305 p_dev->read_cmd = read_cmd[lines]; 306 307 if (p_dev->manufacturer == MID_GIGADEV || 308 p_dev->manufacturer == MID_WINBOND || 309 p_dev->manufacturer == MID_MACRONIX) { 310 p_dev->prog_lines = (lines != DATA_LINES_X2) ? 311 lines : DATA_LINES_X1; 312 if (lines == DATA_LINES_X1) { 313 p_dev->prog_cmd = CMD_PAGE_PROG; 314 } else { 315 if (p_dev->manufacturer == MID_GIGADEV || 316 p_dev->manufacturer == MID_WINBOND) 317 p_dev->prog_cmd = CMD_PAGE_PROG_X4; 318 else 319 p_dev->prog_cmd = CMD_PAGE_PROG_A4; 320 } 321 } 322 323 return SFC_OK; 324 } 325 #endif 326 327 static int snor_read_data(struct SFNOR_DEV *p_dev, 328 u32 addr, 329 void *p_data, 330 u32 size) 331 { 332 int ret; 333 union SFCCMD_DATA sfcmd; 334 union SFCCTRL_DATA sfctrl; 335 336 sfcmd.d32 = 0; 337 sfcmd.b.cmd = p_dev->read_cmd; 338 sfcmd.b.datasize = size; 339 sfcmd.b.addrbits = SFC_ADDR_24BITS; 340 341 sfctrl.d32 = 0; 342 sfctrl.b.datalines = p_dev->read_lines; 343 if (!(size & 0x3) && size >= 4) 344 sfctrl.b.enbledma = 0; 345 346 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 347 p_dev->read_cmd == CMD_FAST_READ_X4 || 348 p_dev->read_cmd == CMD_FAST_READ_X2 || 349 p_dev->read_cmd == CMD_FAST_4READ_X4) { 350 sfcmd.b.dummybits = 8; 351 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 352 sfcmd.b.addrbits = SFC_ADDR_32BITS; 353 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 354 sfcmd.b.dummybits = 4; 355 sfctrl.b.addrlines = SFC_4BITS_LINE; 356 } 357 358 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 359 sfcmd.b.addrbits = SFC_ADDR_32BITS; 360 361 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 362 363 return ret; 364 } 365 366 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 367 { 368 int ret = SFC_OK; 369 u32 addr, size, len; 370 u8 *p_buf = (u8 *)p_data; 371 372 if ((sec + n_sec) > p_dev->capacity) 373 return SFC_PARAM_ERR; 374 375 mutex_lock(&p_dev->lock); 376 addr = sec << 9; 377 size = n_sec << 9; 378 while (size) { 379 len = size < SFC_MAX_IOSIZE ? size : SFC_MAX_IOSIZE; 380 ret = snor_read_data(p_dev, addr, p_buf, len); 381 if (ret != SFC_OK) { 382 PRINT_SFC_E("snor_read_data %x ret= %x\n", 383 addr >> 9, ret); 384 goto out; 385 } 386 387 size -= len; 388 addr += len; 389 p_buf += len; 390 } 391 out: 392 mutex_unlock(&p_dev->lock); 393 if (!ret) 394 ret = n_sec; 395 396 return ret; 397 } 398 399 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, const void *p_data) 400 { 401 int ret = SFC_OK; 402 u32 len, blk_size, offset; 403 u8 *p_buf = (u8 *)p_data; 404 405 if ((sec + n_sec) > p_dev->capacity) 406 return SFC_PARAM_ERR; 407 408 mutex_lock(&p_dev->lock); 409 while (n_sec) { 410 if (sec < 512 || sec >= p_dev->capacity - 512) 411 blk_size = 8; 412 else 413 blk_size = p_dev->blk_size; 414 415 offset = (sec & (blk_size - 1)); 416 if (!offset) { 417 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 418 ERASE_SECTOR : ERASE_BLOCK64K); 419 if (ret != SFC_OK) { 420 PRINT_SFC_E("snor_erase %x ret= %x\n", 421 sec, ret); 422 goto out; 423 } 424 } 425 len = (blk_size - offset) < n_sec ? 426 (blk_size - offset) : n_sec; 427 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 428 if (ret != SFC_OK) { 429 PRINT_SFC_E("snor_prog %x ret= %x\n", sec, ret); 430 goto out; 431 } 432 n_sec -= len; 433 sec += len; 434 p_buf += len << 9; 435 } 436 out: 437 mutex_unlock(&p_dev->lock); 438 if (!ret) 439 ret = n_sec; 440 441 return ret; 442 } 443 444 static int snor_read_id(u8 *data) 445 { 446 int ret; 447 union SFCCMD_DATA sfcmd; 448 449 sfcmd.d32 = 0; 450 sfcmd.b.cmd = CMD_READ_JEDECID; 451 sfcmd.b.datasize = 3; 452 453 ret = sfc_request(sfcmd.d32, 0, 0, data); 454 455 return ret; 456 } 457 458 static int snor_read_parameter(u32 addr, u8 *data) 459 { 460 int ret; 461 union SFCCMD_DATA sfcmd; 462 463 sfcmd.d32 = 0; 464 sfcmd.b.cmd = CMD_READ_PARAMETER; 465 sfcmd.b.datasize = 1; 466 sfcmd.b.addrbits = SFC_ADDR_24BITS; 467 sfcmd.b.dummybits = 8; 468 469 ret = sfc_request(sfcmd.d32, 0, addr, data); 470 471 return ret; 472 } 473 474 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 475 { 476 return p_dev->capacity; 477 } 478 479 static void snor_print_spi_chip_info(struct SFNOR_DEV *p_dev) 480 { 481 PRINT_SFC_I("addr_mode: %x\n", p_dev->addr_mode); 482 PRINT_SFC_I("read_lines: %x\n", p_dev->read_lines); 483 PRINT_SFC_I("prog_lines: %x\n", p_dev->prog_lines); 484 PRINT_SFC_I("read_cmd: %x\n", p_dev->read_cmd); 485 PRINT_SFC_I("prog_cmd: %x\n", p_dev->prog_cmd); 486 PRINT_SFC_I("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 487 PRINT_SFC_I("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 488 } 489 490 static struct flash_info *snor_get_flash_info(u8 *flash_id) 491 { 492 u32 i; 493 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 494 495 for (i = 0; 496 i < (sizeof(spi_flash_tbl) / sizeof(struct flash_info)); 497 i++) { 498 if (spi_flash_tbl[i].id == id) 499 return &spi_flash_tbl[i]; 500 } 501 return NULL; 502 } 503 504 /* Adjust flash info in ram base on parameter */ 505 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 506 { 507 u32 addr; 508 u8 para_version; 509 510 if (spi_flash_info->id == 0xc84019) { 511 addr = 0x09; 512 snor_read_parameter(addr, ¶_version); 513 if (para_version == 0x06) { 514 spi_flash_info->QE_bits = 9; 515 spi_flash_info->prog_cmd_4 = 0x34; 516 } 517 } 518 return 0; 519 } 520 521 int snor_init(struct SFNOR_DEV *p_dev) 522 { 523 int i; 524 u8 id_byte[5]; 525 int err; 526 527 memset(p_dev, 0, sizeof(struct SFNOR_DEV)); 528 snor_read_id(id_byte); 529 PRINT_SFC_E("sfc nor id: %x %x %x\n", 530 id_byte[0], id_byte[1], id_byte[2]); 531 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) { 532 err = SFC_ERROR; 533 goto err_out; 534 } 535 536 p_dev->manufacturer = id_byte[0]; 537 p_dev->mem_type = id_byte[1]; 538 539 mutex_init(&p_dev->lock); 540 g_spi_flash_info = snor_get_flash_info(id_byte); 541 if (g_spi_flash_info) { 542 snor_flash_info_adjust(g_spi_flash_info); 543 p_dev->capacity = 1 << g_spi_flash_info->density; 544 p_dev->blk_size = g_spi_flash_info->block_size; 545 p_dev->page_size = NOR_SECS_PAGE; 546 p_dev->read_cmd = g_spi_flash_info->read_cmd; 547 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 548 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 549 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 550 p_dev->prog_lines = DATA_LINES_X1; 551 p_dev->read_lines = DATA_LINES_X1; 552 p_dev->QE_bits = g_spi_flash_info->QE_bits; 553 554 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 555 if (i == 0) 556 p_dev->write_status = snor_write_status; 557 else 558 p_dev->write_status = snor_write_status2; 559 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 560 if (snor_enable_QE(p_dev) == SFC_OK) { 561 p_dev->read_lines = DATA_LINES_X4; 562 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 563 } 564 } 565 if ((g_spi_flash_info->feature & FEA_4BIT_PROG) && 566 (p_dev->read_lines == DATA_LINES_X4)) { 567 p_dev->prog_lines = DATA_LINES_X4; 568 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 569 } 570 571 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 572 p_dev->addr_mode = ADDR_MODE_4BYTE; 573 574 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 575 snor_enter_4byte_mode(); 576 577 goto normal_out; 578 } 579 580 for (i = 0; i < sizeof(sfnor_dev_code); i++) { 581 if (id_byte[2] == sfnor_dev_code[i]) { 582 p_dev->capacity = sfnor_capacity[i] >> 9; 583 break; 584 } 585 } 586 587 if (i >= sizeof(sfnor_dev_code)) { 588 err = SFC_ERROR; 589 goto err_out; 590 } 591 592 p_dev->QE_bits = 9; 593 p_dev->blk_size = NOR_SECS_BLK; 594 p_dev->page_size = NOR_SECS_PAGE; 595 p_dev->read_cmd = CMD_READ_DATA; 596 p_dev->prog_cmd = CMD_PAGE_PROG; 597 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 598 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 599 p_dev->write_status = snor_write_status2; 600 #if (SNOR_4BIT_DATA_DETECT_EN) 601 snor_set_dlines(p_dev, DATA_LINES_X4); 602 #endif 603 604 normal_out: 605 snor_print_spi_chip_info(p_dev); 606 607 return SFC_OK; 608 609 err_out: 610 return err; 611 } 612 613