1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "sfc_nor.h" 12 #include "rkflash_debug.h" 13 #include "rkflash_blk.h" 14 15 static struct flash_info spi_flash_tbl[] = { 16 /* GD25Q32B */ 17 {0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0}, 18 /* GD25Q64B */ 19 {0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0}, 20 /* GD25Q127C and GD25Q128C*/ 21 {0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 22 /* GD25Q256B */ 23 {0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0}, 24 /* GD25Q512MC */ 25 {0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0}, 26 /* 25Q64JVSSIQ */ 27 {0xef4017, 128, 8, 0x13, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0}, 28 /* 25Q128FV */ 29 {0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 30 /* 25Q256FV */ 31 {0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0}, 32 /* 25Q64FWSSIG */ 33 {0xef6017, 128, 8, 0x13, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0}, 34 /* XT25F128A */ 35 {0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0}, 36 /* MX25L25635E/F */ 37 {0xc22019, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x30, 16, 6, 0}, 38 }; 39 40 static const u8 sfnor_dev_code[] = { 41 0x11, 42 0x12, 43 0x13, 44 0x14, 45 0x15, 46 0x16, 47 0x17, 48 0x18, 49 0x19 50 }; 51 52 static const u32 sfnor_capacity[] = { 53 0x20000, /* 128k-byte */ 54 0x40000, /* 256k-byte */ 55 0x80000, /* 512k-byte */ 56 0x100000, /* 1M-byte */ 57 0x200000, /* 2M-byte */ 58 0x400000, /* 4M-byte */ 59 0x800000, /* 8M-byte */ 60 0x1000000, /* 16M-byte */ 61 0x2000000 /* 32M-byte */ 62 }; 63 64 static struct flash_info *g_spi_flash_info; 65 66 static int snor_write_en(void) 67 { 68 int ret; 69 union SFCCMD_DATA sfcmd; 70 71 sfcmd.d32 = 0; 72 sfcmd.b.cmd = CMD_WRITE_EN; 73 74 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 75 76 return ret; 77 } 78 79 static int snor_enter_4byte_mode(void) 80 { 81 int ret; 82 union SFCCMD_DATA sfcmd; 83 84 sfcmd.d32 = 0; 85 sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 86 87 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 88 return ret; 89 } 90 91 static int snor_read_status(u32 reg_index, u8 *status) 92 { 93 int ret; 94 union SFCCMD_DATA sfcmd; 95 u8 read_stat_cmd[] = {CMD_READ_STATUS, 96 CMD_READ_STATUS2, CMD_READ_STATUS3}; 97 sfcmd.d32 = 0; 98 sfcmd.b.cmd = read_stat_cmd[reg_index]; 99 sfcmd.b.datasize = 1; 100 101 ret = sfc_request(sfcmd.d32, 0, 0, status); 102 103 return ret; 104 } 105 106 static int snor_wait_busy(int timeout) 107 { 108 int ret; 109 union SFCCMD_DATA sfcmd; 110 int i; 111 u32 status; 112 113 sfcmd.d32 = 0; 114 sfcmd.b.cmd = CMD_READ_STATUS; 115 sfcmd.b.datasize = 1; 116 117 for (i = 0; i < timeout; i++) { 118 ret = sfc_request(sfcmd.d32, 0, 0, &status); 119 if (ret != SFC_OK) 120 return ret; 121 122 if ((status & 0x01) == 0) 123 return SFC_OK; 124 125 sfc_delay(1); 126 } 127 PRINT_SFC_E("%s error %x\n", __func__, timeout); 128 129 return SFC_BUSY_TIMEOUT; 130 } 131 132 static int snor_write_status2(u32 reg_index, u8 status) 133 { 134 int ret; 135 union SFCCMD_DATA sfcmd; 136 u8 status2[2]; 137 u8 read_index; 138 139 status2[reg_index] = status; 140 read_index = (reg_index == 0) ? 1 : 0; 141 ret = snor_read_status(read_index, &status2[read_index]); 142 if (ret != SFC_OK) 143 return ret; 144 145 snor_write_en(); 146 147 sfcmd.d32 = 0; 148 sfcmd.b.cmd = CMD_WRITE_STATUS; 149 sfcmd.b.datasize = 2; 150 sfcmd.b.rw = SFC_WRITE; 151 152 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 153 if (ret != SFC_OK) 154 return ret; 155 156 ret = snor_wait_busy(10000); /* 10ms */ 157 158 return ret; 159 } 160 161 static int snor_write_status(u32 reg_index, u8 status) 162 { 163 int ret; 164 union SFCCMD_DATA sfcmd; 165 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 166 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 167 snor_write_en(); 168 sfcmd.d32 = 0; 169 sfcmd.b.cmd = write_stat_cmd[reg_index]; 170 sfcmd.b.datasize = 1; 171 sfcmd.b.rw = SFC_WRITE; 172 173 ret = sfc_request(sfcmd.d32, 0, 0, &status); 174 if (ret != SFC_OK) 175 return ret; 176 177 ret = snor_wait_busy(10000); /* 10ms */ 178 179 return ret; 180 } 181 182 static int snor_erase(struct SFNOR_DEV *p_dev, 183 u32 addr, 184 enum NOR_ERASE_TYPE erase_type) 185 { 186 int ret; 187 union SFCCMD_DATA sfcmd; 188 int timeout[] = {400, 2000, 40000}; /* ms */ 189 190 if (erase_type > ERASE_CHIP) 191 return SFC_PARAM_ERR; 192 193 sfcmd.d32 = 0; 194 if (erase_type == ERASE_BLOCK64K) 195 sfcmd.b.cmd = p_dev->blk_erase_cmd; 196 else if (erase_type == ERASE_SECTOR) 197 sfcmd.b.cmd = p_dev->sec_erase_cmd; 198 else 199 sfcmd.b.cmd = CMD_CHIP_ERASE; 200 201 sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 202 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 203 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 204 sfcmd.b.addrbits = SFC_ADDR_32BITS; 205 206 snor_write_en(); 207 208 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 209 if (ret != SFC_OK) 210 return ret; 211 212 ret = snor_wait_busy(timeout[erase_type] * 1000); 213 return ret; 214 } 215 216 static int snor_prog_page(struct SFNOR_DEV *p_dev, 217 u32 addr, 218 void *p_data, 219 u32 size) 220 { 221 int ret; 222 union SFCCMD_DATA sfcmd; 223 union SFCCTRL_DATA sfctrl; 224 225 sfcmd.d32 = 0; 226 sfcmd.b.cmd = p_dev->prog_cmd; 227 sfcmd.b.addrbits = SFC_ADDR_24BITS; 228 sfcmd.b.datasize = size; 229 sfcmd.b.rw = SFC_WRITE; 230 231 sfctrl.d32 = 0; 232 sfctrl.b.datalines = p_dev->prog_lines; 233 sfctrl.b.enbledma = 0; 234 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 235 sfctrl.b.addrlines = SFC_4BITS_LINE; 236 237 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 238 sfcmd.b.addrbits = SFC_ADDR_32BITS; 239 240 snor_write_en(); 241 242 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 243 if (ret != SFC_OK) 244 return ret; 245 246 ret = snor_wait_busy(10000); 247 248 return ret; 249 } 250 251 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 252 { 253 int ret = SFC_OK; 254 u32 page_size, len; 255 u8 *p_buf = (u8 *)p_data; 256 257 page_size = NOR_PAGE_SIZE; 258 while (size) { 259 len = page_size < size ? page_size : size; 260 ret = snor_prog_page(p_dev, addr, p_buf, len); 261 if (ret != SFC_OK) 262 return ret; 263 264 size -= len; 265 addr += len; 266 p_buf += len; 267 } 268 269 return ret; 270 } 271 272 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 273 { 274 int ret = SFC_OK; 275 int reg_index; 276 int bit_offset; 277 u8 status; 278 279 if (p_dev->manufacturer == MID_GIGADEV || 280 p_dev->manufacturer == MID_WINBOND) { 281 reg_index = p_dev->QE_bits >> 3; 282 bit_offset = p_dev->QE_bits & 0x7; 283 ret = snor_read_status(reg_index, &status); 284 if (ret != SFC_OK) 285 return ret; 286 287 if (status & (1 << bit_offset)) /* is QE bit set */ 288 return SFC_OK; 289 290 status |= (1 << bit_offset); 291 return p_dev->write_status(reg_index, status); 292 } 293 294 return ret; 295 } 296 297 #if (SNOR_4BIT_DATA_DETECT_EN) 298 static int snor_set_dlines(struct SFNOR_DEV *p_dev, enum SFC_DATA_LINES lines) 299 { 300 int ret; 301 u8 read_cmd[] = {CMD_FAST_READ_X1, CMD_FAST_READ_X2, CMD_FAST_READ_X4}; 302 303 if (lines == DATA_LINES_X4) { 304 ret = snor_enable_QE(p_dev); 305 if (ret != SFC_OK) 306 return ret; 307 } 308 309 p_dev->read_lines = lines; 310 p_dev->read_cmd = read_cmd[lines]; 311 312 if (p_dev->manufacturer == MID_GIGADEV || 313 p_dev->manufacturer == MID_WINBOND || 314 p_dev->manufacturer == MID_MACRONIX) { 315 p_dev->prog_lines = (lines != DATA_LINES_X2) ? 316 lines : DATA_LINES_X1; 317 if (lines == DATA_LINES_X1) { 318 p_dev->prog_cmd = CMD_PAGE_PROG; 319 } else { 320 if (p_dev->manufacturer == MID_GIGADEV || 321 p_dev->manufacturer == MID_WINBOND) 322 p_dev->prog_cmd = CMD_PAGE_PROG_X4; 323 else 324 p_dev->prog_cmd = CMD_PAGE_PROG_A4; 325 } 326 } 327 328 return SFC_OK; 329 } 330 #endif 331 332 static int snor_read_data(struct SFNOR_DEV *p_dev, 333 u32 addr, 334 void *p_data, 335 u32 size) 336 { 337 int ret; 338 union SFCCMD_DATA sfcmd; 339 union SFCCTRL_DATA sfctrl; 340 341 sfcmd.d32 = 0; 342 sfcmd.b.cmd = p_dev->read_cmd; 343 sfcmd.b.datasize = size; 344 sfcmd.b.addrbits = SFC_ADDR_24BITS; 345 346 sfctrl.d32 = 0; 347 sfctrl.b.datalines = p_dev->read_lines; 348 if (!(size & 0x3) && size >= 4) 349 sfctrl.b.enbledma = 0; 350 351 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 352 p_dev->read_cmd == CMD_FAST_READ_X4 || 353 p_dev->read_cmd == CMD_FAST_READ_X2 || 354 p_dev->read_cmd == CMD_FAST_4READ_X4) { 355 sfcmd.b.dummybits = 8; 356 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 357 sfcmd.b.addrbits = SFC_ADDR_32BITS; 358 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 359 sfcmd.b.dummybits = 4; 360 sfctrl.b.addrlines = SFC_4BITS_LINE; 361 } 362 363 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 364 sfcmd.b.addrbits = SFC_ADDR_32BITS; 365 366 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 367 368 return ret; 369 } 370 371 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 372 { 373 int ret = SFC_OK; 374 u32 addr, size, len; 375 u8 *p_buf = (u8 *)p_data; 376 377 if ((sec + n_sec) > p_dev->capacity) 378 return SFC_PARAM_ERR; 379 380 mutex_lock(&p_dev->lock); 381 addr = sec << 9; 382 size = n_sec << 9; 383 while (size) { 384 len = size < SFC_MAX_IOSIZE ? size : SFC_MAX_IOSIZE; 385 ret = snor_read_data(p_dev, addr, p_buf, len); 386 if (ret != SFC_OK) { 387 PRINT_SFC_E("snor_read_data %x ret= %x\n", 388 addr >> 9, ret); 389 goto out; 390 } 391 392 size -= len; 393 addr += len; 394 p_buf += len; 395 } 396 out: 397 mutex_unlock(&p_dev->lock); 398 if (!ret) 399 ret = n_sec; 400 401 return ret; 402 } 403 404 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, const void *p_data) 405 { 406 int ret = SFC_OK; 407 u32 len, blk_size, offset; 408 u8 *p_buf = (u8 *)p_data; 409 u32 total_sec = n_sec; 410 411 if ((sec + n_sec) > p_dev->capacity) 412 return SFC_PARAM_ERR; 413 414 mutex_lock(&p_dev->lock); 415 while (n_sec) { 416 if (sec < 512 || sec >= p_dev->capacity - 512) 417 blk_size = 8; 418 else 419 blk_size = p_dev->blk_size; 420 421 offset = (sec & (blk_size - 1)); 422 if (!offset) { 423 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 424 ERASE_SECTOR : ERASE_BLOCK64K); 425 if (ret != SFC_OK) { 426 PRINT_SFC_E("snor_erase %x ret= %x\n", 427 sec, ret); 428 goto out; 429 } 430 } 431 len = (blk_size - offset) < n_sec ? 432 (blk_size - offset) : n_sec; 433 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 434 if (ret != SFC_OK) { 435 PRINT_SFC_E("snor_prog %x ret= %x\n", sec, ret); 436 goto out; 437 } 438 n_sec -= len; 439 sec += len; 440 p_buf += len << 9; 441 } 442 out: 443 mutex_unlock(&p_dev->lock); 444 if (!ret) 445 ret = total_sec; 446 447 return ret; 448 } 449 450 static int snor_read_id(u8 *data) 451 { 452 int ret; 453 union SFCCMD_DATA sfcmd; 454 455 sfcmd.d32 = 0; 456 sfcmd.b.cmd = CMD_READ_JEDECID; 457 sfcmd.b.datasize = 3; 458 459 ret = sfc_request(sfcmd.d32, 0, 0, data); 460 461 return ret; 462 } 463 464 static int snor_read_parameter(u32 addr, u8 *data) 465 { 466 int ret; 467 union SFCCMD_DATA sfcmd; 468 469 sfcmd.d32 = 0; 470 sfcmd.b.cmd = CMD_READ_PARAMETER; 471 sfcmd.b.datasize = 1; 472 sfcmd.b.addrbits = SFC_ADDR_24BITS; 473 sfcmd.b.dummybits = 8; 474 475 ret = sfc_request(sfcmd.d32, 0, addr, data); 476 477 return ret; 478 } 479 480 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 481 { 482 return p_dev->capacity; 483 } 484 485 static void snor_print_spi_chip_info(struct SFNOR_DEV *p_dev) 486 { 487 PRINT_SFC_I("addr_mode: %x\n", p_dev->addr_mode); 488 PRINT_SFC_I("read_lines: %x\n", p_dev->read_lines); 489 PRINT_SFC_I("prog_lines: %x\n", p_dev->prog_lines); 490 PRINT_SFC_I("read_cmd: %x\n", p_dev->read_cmd); 491 PRINT_SFC_I("prog_cmd: %x\n", p_dev->prog_cmd); 492 PRINT_SFC_I("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 493 PRINT_SFC_I("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 494 } 495 496 static struct flash_info *snor_get_flash_info(u8 *flash_id) 497 { 498 u32 i; 499 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 500 501 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 502 if (spi_flash_tbl[i].id == id) 503 return &spi_flash_tbl[i]; 504 } 505 return NULL; 506 } 507 508 /* Adjust flash info in ram base on parameter */ 509 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 510 { 511 u32 addr; 512 u8 para_version; 513 514 if (spi_flash_info->id == 0xc84019) { 515 addr = 0x09; 516 snor_read_parameter(addr, ¶_version); 517 if (para_version == 0x06) { 518 spi_flash_info->QE_bits = 9; 519 spi_flash_info->prog_cmd_4 = 0x34; 520 } 521 } 522 return 0; 523 } 524 525 int snor_init(struct SFNOR_DEV *p_dev) 526 { 527 u32 i; 528 u8 id_byte[5]; 529 int err; 530 531 memset(p_dev, 0, sizeof(struct SFNOR_DEV)); 532 snor_read_id(id_byte); 533 PRINT_SFC_I("sfc nor id: %x %x %x\n", 534 id_byte[0], id_byte[1], id_byte[2]); 535 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) { 536 err = SFC_ERROR; 537 goto err_out; 538 } 539 540 p_dev->manufacturer = id_byte[0]; 541 p_dev->mem_type = id_byte[1]; 542 543 mutex_init(&p_dev->lock); 544 g_spi_flash_info = snor_get_flash_info(id_byte); 545 if (g_spi_flash_info) { 546 snor_flash_info_adjust(g_spi_flash_info); 547 p_dev->capacity = 1 << g_spi_flash_info->density; 548 p_dev->blk_size = g_spi_flash_info->block_size; 549 p_dev->page_size = NOR_SECS_PAGE; 550 p_dev->read_cmd = g_spi_flash_info->read_cmd; 551 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 552 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 553 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 554 p_dev->prog_lines = DATA_LINES_X1; 555 p_dev->read_lines = DATA_LINES_X1; 556 p_dev->QE_bits = g_spi_flash_info->QE_bits; 557 558 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 559 if (i == 0) 560 p_dev->write_status = snor_write_status; 561 else 562 p_dev->write_status = snor_write_status2; 563 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 564 if (snor_enable_QE(p_dev) == SFC_OK) { 565 p_dev->read_lines = DATA_LINES_X4; 566 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 567 } 568 } 569 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 570 p_dev->read_lines == DATA_LINES_X4) { 571 p_dev->prog_lines = DATA_LINES_X4; 572 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 573 } 574 575 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 576 p_dev->addr_mode = ADDR_MODE_4BYTE; 577 578 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 579 snor_enter_4byte_mode(); 580 581 goto normal_out; 582 } 583 584 for (i = 0; i < sizeof(sfnor_dev_code); i++) { 585 if (id_byte[2] == sfnor_dev_code[i]) { 586 p_dev->capacity = sfnor_capacity[i] >> 9; 587 break; 588 } 589 } 590 591 if (i >= sizeof(sfnor_dev_code)) { 592 err = SFC_ERROR; 593 goto err_out; 594 } 595 596 p_dev->QE_bits = 9; 597 p_dev->blk_size = NOR_SECS_BLK; 598 p_dev->page_size = NOR_SECS_PAGE; 599 p_dev->read_cmd = CMD_READ_DATA; 600 p_dev->prog_cmd = CMD_PAGE_PROG; 601 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 602 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 603 p_dev->write_status = snor_write_status2; 604 #if (SNOR_4BIT_DATA_DETECT_EN) 605 snor_set_dlines(p_dev, DATA_LINES_X4); 606 #endif 607 608 normal_out: 609 snor_print_spi_chip_info(p_dev); 610 611 return SFC_OK; 612 613 err_out: 614 return err; 615 } 616 617