1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C*/ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 25 /* 25Q64JVSSIQ */ 26 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 27 /* 25Q128FV and 25Q128JV*/ 28 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 29 /* 25Q256F/J */ 30 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 31 /* 25Q64FWSSIG */ 32 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 33 /* MX25L6433F */ 34 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 35 /* MX25L12835E/F MX25L12833FMI-10G */ 36 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 37 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 38 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 39 /* MX25L51245GMI */ 40 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 41 /* XM25QH32C */ 42 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 43 /* XM25QH64B */ 44 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 45 /* XM25QH128B */ 46 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 47 /* XM25QH(QU)256B */ 48 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 49 /* XM25QH64A */ 50 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 51 /* XT25F128A XM25QH128A */ 52 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0 }, 53 /* XT25F64BSSIGU-5 */ 54 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 55 /* XT25F128BSSIGU */ 56 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 57 /* EN25QH128A */ 58 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 59 /* EN25S32A */ 60 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 61 /* EN25S64A */ 62 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 63 /* P25Q64H */ 64 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 65 /* EN25QH256A */ 66 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 67 /* FM25Q64A */ 68 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 69 /* ZB25VQ64 */ 70 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 71 /* ZB25VQ128 */ 72 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 73 }; 74 75 static int snor_write_en(void) 76 { 77 int ret; 78 union SFCCMD_DATA sfcmd; 79 80 sfcmd.d32 = 0; 81 sfcmd.b.cmd = CMD_WRITE_EN; 82 83 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 84 85 return ret; 86 } 87 88 int snor_reset_device(void) 89 { 90 int ret; 91 union SFCCMD_DATA sfcmd; 92 93 sfcmd.d32 = 0; 94 sfcmd.b.cmd = CMD_ENABLE_RESER; 95 sfc_request(sfcmd.d32, 0, 0, NULL); 96 97 sfcmd.d32 = 0; 98 sfcmd.b.cmd = CMD_RESET_DEVICE; 99 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 100 /* tRST=30us , delay 1ms here */ 101 mdelay(1); 102 return ret; 103 } 104 105 static int snor_enter_4byte_mode(void) 106 { 107 int ret; 108 union SFCCMD_DATA sfcmd; 109 110 sfcmd.d32 = 0; 111 sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 112 113 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 114 return ret; 115 } 116 117 static int snor_read_status(u32 reg_index, u8 *status) 118 { 119 int ret; 120 union SFCCMD_DATA sfcmd; 121 u8 read_stat_cmd[] = {CMD_READ_STATUS, 122 CMD_READ_STATUS2, CMD_READ_STATUS3}; 123 sfcmd.d32 = 0; 124 sfcmd.b.cmd = read_stat_cmd[reg_index]; 125 sfcmd.b.datasize = 1; 126 127 ret = sfc_request(sfcmd.d32, 0, 0, status); 128 129 return ret; 130 } 131 132 static int snor_wait_busy(int timeout) 133 { 134 int ret; 135 union SFCCMD_DATA sfcmd; 136 int i; 137 u32 status; 138 139 sfcmd.d32 = 0; 140 sfcmd.b.cmd = CMD_READ_STATUS; 141 sfcmd.b.datasize = 1; 142 143 for (i = 0; i < timeout; i++) { 144 ret = sfc_request(sfcmd.d32, 0, 0, &status); 145 if (ret != SFC_OK) 146 return ret; 147 148 if ((status & 0x01) == 0) 149 return SFC_OK; 150 151 sfc_delay(1); 152 } 153 rkflash_print_error("%s error %x\n", __func__, timeout); 154 155 return SFC_BUSY_TIMEOUT; 156 } 157 158 static int snor_write_status2(u32 reg_index, u8 status) 159 { 160 int ret; 161 union SFCCMD_DATA sfcmd; 162 u8 status2[2]; 163 u8 read_index; 164 165 status2[reg_index] = status; 166 read_index = (reg_index == 0) ? 2 : 0; 167 ret = snor_read_status(read_index, &status2[read_index]); 168 if (ret != SFC_OK) 169 return ret; 170 171 snor_write_en(); 172 173 sfcmd.d32 = 0; 174 sfcmd.b.cmd = CMD_WRITE_STATUS; 175 sfcmd.b.datasize = 2; 176 sfcmd.b.rw = SFC_WRITE; 177 178 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 179 if (ret != SFC_OK) 180 return ret; 181 182 ret = snor_wait_busy(10000); /* 10ms */ 183 184 return ret; 185 } 186 187 static int snor_write_status1(u32 reg_index, u8 status) 188 { 189 int ret; 190 union SFCCMD_DATA sfcmd; 191 u8 status2[2]; 192 u8 read_index; 193 194 status2[reg_index] = status; 195 read_index = (reg_index == 0) ? 1 : 0; 196 ret = snor_read_status(read_index, &status2[read_index]); 197 if (ret != SFC_OK) 198 return ret; 199 200 snor_write_en(); 201 202 sfcmd.d32 = 0; 203 sfcmd.b.cmd = CMD_WRITE_STATUS; 204 sfcmd.b.datasize = 2; 205 sfcmd.b.rw = SFC_WRITE; 206 207 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 208 if (ret != SFC_OK) 209 return ret; 210 211 ret = snor_wait_busy(10000); /* 10ms */ 212 213 return ret; 214 } 215 216 static int snor_write_status(u32 reg_index, u8 status) 217 { 218 int ret; 219 union SFCCMD_DATA sfcmd; 220 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 221 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 222 snor_write_en(); 223 sfcmd.d32 = 0; 224 sfcmd.b.cmd = write_stat_cmd[reg_index]; 225 sfcmd.b.datasize = 1; 226 sfcmd.b.rw = SFC_WRITE; 227 228 ret = sfc_request(sfcmd.d32, 0, 0, &status); 229 if (ret != SFC_OK) 230 return ret; 231 232 ret = snor_wait_busy(10000); /* 10ms */ 233 234 return ret; 235 } 236 237 int snor_erase(struct SFNOR_DEV *p_dev, 238 u32 addr, 239 enum NOR_ERASE_TYPE erase_type) 240 { 241 int ret; 242 union SFCCMD_DATA sfcmd; 243 int timeout[] = {400, 2000, 40000}; /* ms */ 244 245 if (erase_type > ERASE_CHIP) 246 return SFC_PARAM_ERR; 247 248 sfcmd.d32 = 0; 249 if (erase_type == ERASE_BLOCK64K) 250 sfcmd.b.cmd = p_dev->blk_erase_cmd; 251 else if (erase_type == ERASE_SECTOR) 252 sfcmd.b.cmd = p_dev->sec_erase_cmd; 253 else 254 sfcmd.b.cmd = CMD_CHIP_ERASE; 255 256 sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 257 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 258 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 259 sfcmd.b.addrbits = SFC_ADDR_32BITS; 260 261 snor_write_en(); 262 263 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 264 if (ret != SFC_OK) 265 return ret; 266 267 ret = snor_wait_busy(timeout[erase_type] * 1000); 268 return ret; 269 } 270 271 int snor_prog_page(struct SFNOR_DEV *p_dev, 272 u32 addr, 273 void *p_data, 274 u32 size) 275 { 276 int ret; 277 union SFCCMD_DATA sfcmd; 278 union SFCCTRL_DATA sfctrl; 279 280 sfcmd.d32 = 0; 281 sfcmd.b.cmd = p_dev->prog_cmd; 282 sfcmd.b.addrbits = SFC_ADDR_24BITS; 283 sfcmd.b.datasize = size; 284 sfcmd.b.rw = SFC_WRITE; 285 286 sfctrl.d32 = 0; 287 sfctrl.b.datalines = p_dev->prog_lines; 288 sfctrl.b.enbledma = 0; 289 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 290 sfctrl.b.addrlines = SFC_4BITS_LINE; 291 292 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 293 sfcmd.b.addrbits = SFC_ADDR_32BITS; 294 295 snor_write_en(); 296 297 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 298 if (ret != SFC_OK) 299 return ret; 300 301 ret = snor_wait_busy(10000); 302 303 return ret; 304 } 305 306 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 307 { 308 int ret = SFC_OK; 309 u32 page_size, len; 310 u8 *p_buf = (u8 *)p_data; 311 312 page_size = NOR_PAGE_SIZE; 313 while (size) { 314 len = page_size < size ? page_size : size; 315 ret = snor_prog_page(p_dev, addr, p_buf, len); 316 if (ret != SFC_OK) 317 return ret; 318 319 size -= len; 320 addr += len; 321 p_buf += len; 322 } 323 324 return ret; 325 } 326 327 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 328 { 329 int ret = SFC_OK; 330 int reg_index; 331 int bit_offset; 332 u8 status; 333 334 if (p_dev->manufacturer == MID_GIGADEV || 335 p_dev->manufacturer == MID_WINBOND || 336 p_dev->manufacturer == MID_XTX || 337 p_dev->manufacturer == MID_MACRONIX || 338 p_dev->manufacturer == MID_PUYA || 339 p_dev->manufacturer == MID_XMC || 340 p_dev->manufacturer == MID_DOSILICON || 341 p_dev->manufacturer == MID_ZBIT) { 342 reg_index = p_dev->QE_bits >> 3; 343 bit_offset = p_dev->QE_bits & 0x7; 344 ret = snor_read_status(reg_index, &status); 345 if (ret != SFC_OK) 346 return ret; 347 348 if (status & (1 << bit_offset)) /* is QE bit set */ 349 return SFC_OK; 350 351 status |= (1 << bit_offset); 352 return p_dev->write_status(reg_index, status); 353 } 354 355 return ret; 356 } 357 358 int snor_disable_QE(struct SFNOR_DEV *p_dev) 359 { 360 int ret = SFC_OK; 361 int reg_index; 362 int bit_offset; 363 u8 status; 364 365 if (p_dev->manufacturer == MID_GIGADEV || 366 p_dev->manufacturer == MID_WINBOND || 367 p_dev->manufacturer == MID_XTX || 368 p_dev->manufacturer == MID_MACRONIX || 369 p_dev->manufacturer == MID_PUYA || 370 p_dev->manufacturer == MID_XMC || 371 p_dev->manufacturer == MID_DOSILICON || 372 p_dev->manufacturer == MID_ZBIT) { 373 reg_index = p_dev->QE_bits >> 3; 374 bit_offset = p_dev->QE_bits & 0x7; 375 ret = snor_read_status(reg_index, &status); 376 if (ret != SFC_OK) 377 return ret; 378 379 if (!(status & (1 << bit_offset))) 380 return SFC_OK; 381 382 status &= ~(1 << bit_offset); 383 return p_dev->write_status(reg_index, status); 384 } 385 386 return ret; 387 } 388 389 int snor_read_data(struct SFNOR_DEV *p_dev, 390 u32 addr, 391 void *p_data, 392 u32 size) 393 { 394 int ret; 395 union SFCCMD_DATA sfcmd; 396 union SFCCTRL_DATA sfctrl; 397 398 sfcmd.d32 = 0; 399 sfcmd.b.cmd = p_dev->read_cmd; 400 sfcmd.b.datasize = size; 401 sfcmd.b.addrbits = SFC_ADDR_24BITS; 402 403 sfctrl.d32 = 0; 404 sfctrl.b.datalines = p_dev->read_lines; 405 if (!(size & 0x3) && size >= 4) 406 sfctrl.b.enbledma = 0; 407 408 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 409 p_dev->read_cmd == CMD_FAST_READ_X4 || 410 p_dev->read_cmd == CMD_FAST_READ_X2 || 411 p_dev->read_cmd == CMD_FAST_4READ_X4) { 412 sfcmd.b.dummybits = 8; 413 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 414 sfcmd.b.addrbits = SFC_ADDR_32BITS; 415 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 416 sfcmd.b.dummybits = 4; 417 sfctrl.b.addrlines = SFC_4BITS_LINE; 418 } 419 420 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 421 sfcmd.b.addrbits = SFC_ADDR_32BITS; 422 423 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 424 425 return ret; 426 } 427 428 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 429 { 430 int ret = SFC_OK; 431 u32 addr, size, len; 432 u8 *p_buf = (u8 *)p_data; 433 434 if ((sec + n_sec) > p_dev->capacity) 435 return SFC_PARAM_ERR; 436 437 addr = sec << 9; 438 size = n_sec << 9; 439 while (size) { 440 len = size < SFC_MAX_IOSIZE ? size : SFC_MAX_IOSIZE; 441 ret = snor_read_data(p_dev, addr, p_buf, len); 442 if (ret != SFC_OK) { 443 rkflash_print_error("snor_read_data %x ret= %x\n", 444 addr >> 9, ret); 445 goto out; 446 } 447 448 size -= len; 449 addr += len; 450 p_buf += len; 451 } 452 out: 453 if (!ret) 454 ret = n_sec; 455 456 return ret; 457 } 458 459 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 460 { 461 int ret = SFC_OK; 462 u32 len, blk_size, offset; 463 u8 *p_buf = (u8 *)p_data; 464 u32 total_sec = n_sec; 465 466 if ((sec + n_sec) > p_dev->capacity) 467 return SFC_PARAM_ERR; 468 469 while (n_sec) { 470 if (sec < 512 || sec >= p_dev->capacity - 512) 471 blk_size = 8; 472 else 473 blk_size = p_dev->blk_size; 474 475 offset = (sec & (blk_size - 1)); 476 if (!offset) { 477 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 478 ERASE_SECTOR : ERASE_BLOCK64K); 479 if (ret != SFC_OK) { 480 rkflash_print_error("snor_erase %x ret= %x\n", 481 sec, ret); 482 goto out; 483 } 484 } 485 len = (blk_size - offset) < n_sec ? 486 (blk_size - offset) : n_sec; 487 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 488 if (ret != SFC_OK) { 489 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 490 goto out; 491 } 492 n_sec -= len; 493 sec += len; 494 p_buf += len << 9; 495 } 496 out: 497 if (!ret) 498 ret = total_sec; 499 500 return ret; 501 } 502 503 int snor_read_id(u8 *data) 504 { 505 int ret; 506 union SFCCMD_DATA sfcmd; 507 508 sfcmd.d32 = 0; 509 sfcmd.b.cmd = CMD_READ_JEDECID; 510 sfcmd.b.datasize = 3; 511 512 ret = sfc_request(sfcmd.d32, 0, 0, data); 513 514 return ret; 515 } 516 517 static int snor_read_parameter(u32 addr, u8 *data) 518 { 519 int ret; 520 union SFCCMD_DATA sfcmd; 521 522 sfcmd.d32 = 0; 523 sfcmd.b.cmd = CMD_READ_PARAMETER; 524 sfcmd.b.datasize = 1; 525 sfcmd.b.addrbits = SFC_ADDR_24BITS; 526 sfcmd.b.dummybits = 8; 527 528 ret = sfc_request(sfcmd.d32, 0, addr, data); 529 530 return ret; 531 } 532 533 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 534 { 535 return p_dev->capacity; 536 } 537 538 static struct flash_info *snor_get_flash_info(u8 *flash_id) 539 { 540 u32 i; 541 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 542 543 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 544 if (spi_flash_tbl[i].id == id) 545 return &spi_flash_tbl[i]; 546 } 547 return NULL; 548 } 549 550 /* Adjust flash info in ram base on parameter */ 551 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 552 { 553 u32 addr; 554 u8 para_version; 555 556 if (spi_flash_info->id == 0xc84019) { 557 addr = 0x09; 558 snor_read_parameter(addr, ¶_version); 559 if (para_version == 0x06) { 560 spi_flash_info->QE_bits = 9; 561 spi_flash_info->prog_cmd_4 = 0x34; 562 } 563 } 564 return 0; 565 } 566 567 int snor_init(struct SFNOR_DEV *p_dev) 568 { 569 struct flash_info *g_spi_flash_info; 570 u32 i; 571 u8 id_byte[5]; 572 573 if (!p_dev) 574 return SFC_PARAM_ERR; 575 576 memset(p_dev, 0, sizeof(struct SFNOR_DEV)); 577 snor_read_id(id_byte); 578 rkflash_print_error("sfc nor id: %x %x %x\n", 579 id_byte[0], id_byte[1], id_byte[2]); 580 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 581 return SFC_ERROR; 582 583 p_dev->manufacturer = id_byte[0]; 584 p_dev->mem_type = id_byte[1]; 585 586 g_spi_flash_info = snor_get_flash_info(id_byte); 587 if (g_spi_flash_info) { 588 snor_flash_info_adjust(g_spi_flash_info); 589 p_dev->capacity = 1 << g_spi_flash_info->density; 590 p_dev->blk_size = g_spi_flash_info->block_size; 591 p_dev->page_size = NOR_SECS_PAGE; 592 p_dev->read_cmd = g_spi_flash_info->read_cmd; 593 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 594 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 595 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 596 p_dev->prog_lines = DATA_LINES_X1; 597 p_dev->read_lines = DATA_LINES_X1; 598 p_dev->QE_bits = g_spi_flash_info->QE_bits; 599 p_dev->addr_mode = ADDR_MODE_3BYTE; 600 601 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 602 if (i == 0) 603 p_dev->write_status = snor_write_status; 604 else if (i == 1) 605 p_dev->write_status = snor_write_status1; 606 else if (i == 2) 607 p_dev->write_status = snor_write_status2; 608 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 609 if (snor_enable_QE(p_dev) == SFC_OK) { 610 p_dev->read_lines = DATA_LINES_X4; 611 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 612 } 613 } 614 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 615 p_dev->read_lines == DATA_LINES_X4) { 616 p_dev->prog_lines = DATA_LINES_X4; 617 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 618 } 619 620 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 621 p_dev->addr_mode = ADDR_MODE_4BYTE; 622 623 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 624 snor_enter_4byte_mode(); 625 } else { 626 p_dev->capacity = 1 << id_byte[2] >> 3; 627 p_dev->QE_bits = 0; 628 p_dev->blk_size = NOR_SECS_BLK; 629 p_dev->page_size = NOR_SECS_PAGE; 630 p_dev->read_cmd = CMD_READ_DATA; 631 p_dev->prog_cmd = CMD_PAGE_PROG; 632 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 633 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 634 p_dev->prog_lines = DATA_LINES_X1; 635 p_dev->read_lines = DATA_LINES_X1; 636 p_dev->write_status = snor_write_status; 637 } 638 639 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 640 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 641 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 642 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 643 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 644 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 645 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 646 647 return SFC_OK; 648 } 649 650