1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C*/ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 25 /* GD25B512MEYIG */ 26 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 0, 0 }, 27 28 /* W25Q64JVSSIQ */ 29 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 30 /* W25Q128FV and W25Q128JV*/ 31 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 32 /* W25Q256F/J */ 33 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 34 /* W25Q256JWEQ*/ 35 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 36 /* W25Q64FWSSIG */ 37 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 38 /* W25Q128JVSIM */ 39 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 40 /* W25Q256JVEM */ 41 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 42 43 /* MX25L3233FM2I-08G */ 44 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 45 /* MX25L6433F */ 46 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 47 /* MX25L12835E/F MX25L12833FMI-10G */ 48 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 49 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 50 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 51 /* MX25L51245GMI */ 52 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 53 /* MX25U51245G */ 54 { 0xc2253a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 55 56 /* XM25QH32C */ 57 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 58 /* XM25QH64B */ 59 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 60 /* XM25QH128B */ 61 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 62 /* XM25QH(QU)256B */ 63 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 64 /* XM25QH64A */ 65 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 66 67 /* XT25F128A XM25QH128A */ 68 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 69 /* XT25F64BSSIGU-5 */ 70 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 71 /* XT25F128BSSIGU */ 72 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 73 74 /* EN25QH64A */ 75 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 76 /* EN25QH128A */ 77 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 78 /* EN25QH32B */ 79 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 80 /* EN25S32A */ 81 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 82 /* EN25S64A */ 83 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 84 /* EN25QH256A */ 85 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 86 87 /* ZB25VQ64 */ 88 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 89 /* ZB25VQ128 */ 90 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 91 /* ZB25LQ128 */ 92 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 93 94 /* BH25Q128AS */ 95 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 15, 9, 0 }, 96 /* BH25Q64BS */ 97 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 14, 9, 0 }, 98 99 /* FM25Q128A */ 100 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 101 /* FM25Q64-SOB-T-G */ 102 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 103 104 /* FM25Q64A */ 105 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 106 /* P25Q64H */ 107 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 108 }; 109 110 static int snor_write_en(void) 111 { 112 int ret; 113 struct rk_sfc_op op; 114 115 op.sfcmd.d32 = 0; 116 op.sfcmd.b.cmd = CMD_WRITE_EN; 117 118 op.sfctrl.d32 = 0; 119 120 ret = sfc_request(&op, 0, NULL, 0); 121 122 return ret; 123 } 124 125 int snor_reset_device(void) 126 { 127 struct rk_sfc_op op; 128 129 op.sfcmd.d32 = 0; 130 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 131 132 op.sfctrl.d32 = 0; 133 sfc_request(&op, 0, NULL, 0); 134 135 op.sfcmd.d32 = 0; 136 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 137 138 op.sfctrl.d32 = 0; 139 sfc_request(&op, 0, NULL, 0); 140 /* tRST=30us , delay 1ms here */ 141 sfc_delay(1000); 142 143 return SFC_OK; 144 } 145 146 static int snor_enter_4byte_mode(void) 147 { 148 int ret; 149 struct rk_sfc_op op; 150 151 op.sfcmd.d32 = 0; 152 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 153 154 op.sfctrl.d32 = 0; 155 156 ret = sfc_request(&op, 0, NULL, 0); 157 return ret; 158 } 159 160 static int snor_read_status(u32 reg_index, u8 *status) 161 { 162 int ret; 163 struct rk_sfc_op op; 164 u8 read_stat_cmd[] = {CMD_READ_STATUS, 165 CMD_READ_STATUS2, CMD_READ_STATUS3}; 166 op.sfcmd.d32 = 0; 167 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 168 169 op.sfctrl.d32 = 0; 170 ret = sfc_request(&op, 0, status, 1); 171 172 return ret; 173 } 174 175 static int snor_wait_busy(int timeout) 176 { 177 int ret; 178 struct rk_sfc_op op; 179 int i; 180 u32 status; 181 182 op.sfcmd.d32 = 0; 183 op.sfcmd.b.cmd = CMD_READ_STATUS; 184 185 op.sfctrl.d32 = 0; 186 187 for (i = 0; i < timeout; i++) { 188 ret = sfc_request(&op, 0, &status, 1); 189 if (ret != SFC_OK) 190 return ret; 191 192 if ((status & 0x01) == 0) 193 return SFC_OK; 194 195 sfc_delay(1); 196 } 197 rkflash_print_error("%s error %x\n", __func__, timeout); 198 199 return SFC_BUSY_TIMEOUT; 200 } 201 202 static int snor_write_status2(u32 reg_index, u8 status) 203 { 204 int ret; 205 struct rk_sfc_op op; 206 u8 status2[2]; 207 208 status2[reg_index] = status; 209 if (reg_index == 0) 210 ret = snor_read_status(2, &status2[1]); 211 else 212 ret = snor_read_status(0, &status2[0]); 213 if (ret != SFC_OK) 214 return ret; 215 216 snor_write_en(); 217 218 op.sfcmd.d32 = 0; 219 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 220 op.sfcmd.b.rw = SFC_WRITE; 221 222 op.sfctrl.d32 = 0; 223 224 ret = sfc_request(&op, 0, &status2[0], 2); 225 if (ret != SFC_OK) 226 return ret; 227 228 ret = snor_wait_busy(10000); /* 10ms */ 229 230 return ret; 231 } 232 233 static int snor_write_status1(u32 reg_index, u8 status) 234 { 235 int ret; 236 struct rk_sfc_op op; 237 u8 status2[2]; 238 u8 read_index; 239 240 status2[reg_index] = status; 241 read_index = (reg_index == 0) ? 1 : 0; 242 ret = snor_read_status(read_index, &status2[read_index]); 243 if (ret != SFC_OK) 244 return ret; 245 246 snor_write_en(); 247 248 op.sfcmd.d32 = 0; 249 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 250 op.sfcmd.b.rw = SFC_WRITE; 251 252 op.sfctrl.d32 = 0; 253 254 ret = sfc_request(&op, 0, &status2[0], 2); 255 if (ret != SFC_OK) 256 return ret; 257 258 ret = snor_wait_busy(10000); /* 10ms */ 259 260 return ret; 261 } 262 263 static int snor_write_status(u32 reg_index, u8 status) 264 { 265 int ret; 266 struct rk_sfc_op op; 267 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 268 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 269 snor_write_en(); 270 op.sfcmd.d32 = 0; 271 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 272 op.sfcmd.b.rw = SFC_WRITE; 273 274 op.sfctrl.d32 = 0; 275 276 ret = sfc_request(&op, 0, &status, 1); 277 if (ret != SFC_OK) 278 return ret; 279 280 ret = snor_wait_busy(10000); /* 10ms */ 281 282 return ret; 283 } 284 285 int snor_erase(struct SFNOR_DEV *p_dev, 286 u32 addr, 287 enum NOR_ERASE_TYPE erase_type) 288 { 289 int ret; 290 struct rk_sfc_op op; 291 int timeout[] = {400, 2000, 40000}; /* ms */ 292 293 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 294 295 if (erase_type > ERASE_CHIP) 296 return SFC_PARAM_ERR; 297 298 op.sfcmd.d32 = 0; 299 if (erase_type == ERASE_BLOCK64K) 300 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 301 else if (erase_type == ERASE_SECTOR) 302 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 303 else 304 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 305 306 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 307 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 308 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 309 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 310 311 op.sfctrl.d32 = 0; 312 313 snor_write_en(); 314 315 ret = sfc_request(&op, addr, NULL, 0); 316 if (ret != SFC_OK) 317 return ret; 318 319 ret = snor_wait_busy(timeout[erase_type] * 1000); 320 return ret; 321 } 322 323 int snor_prog_page(struct SFNOR_DEV *p_dev, 324 u32 addr, 325 void *p_data, 326 u32 size) 327 { 328 int ret; 329 struct rk_sfc_op op; 330 331 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 332 333 op.sfcmd.d32 = 0; 334 op.sfcmd.b.cmd = p_dev->prog_cmd; 335 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 336 op.sfcmd.b.rw = SFC_WRITE; 337 338 op.sfctrl.d32 = 0; 339 op.sfctrl.b.datalines = p_dev->prog_lines; 340 op.sfctrl.b.enbledma = 1; 341 op.sfctrl.b.addrlines = p_dev->prog_addr_lines; 342 343 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 344 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 345 346 snor_write_en(); 347 348 ret = sfc_request(&op, addr, p_data, size); 349 if (ret != SFC_OK) 350 return ret; 351 352 ret = snor_wait_busy(10000); 353 354 return ret; 355 } 356 357 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 358 { 359 int ret = SFC_OK; 360 u32 page_size, len; 361 u8 *p_buf = (u8 *)p_data; 362 363 page_size = NOR_PAGE_SIZE; 364 while (size) { 365 len = page_size < size ? page_size : size; 366 ret = snor_prog_page(p_dev, addr, p_buf, len); 367 if (ret != SFC_OK) 368 return ret; 369 370 size -= len; 371 addr += len; 372 p_buf += len; 373 } 374 375 return ret; 376 } 377 378 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 379 { 380 int ret = SFC_OK; 381 int reg_index; 382 int bit_offset; 383 u8 status; 384 385 reg_index = p_dev->QE_bits >> 3; 386 bit_offset = p_dev->QE_bits & 0x7; 387 ret = snor_read_status(reg_index, &status); 388 if (ret != SFC_OK) 389 return ret; 390 391 if (status & (1 << bit_offset)) /* is QE bit set */ 392 return SFC_OK; 393 394 status |= (1 << bit_offset); 395 396 return p_dev->write_status(reg_index, status); 397 } 398 399 int snor_disable_QE(struct SFNOR_DEV *p_dev) 400 { 401 int ret = SFC_OK; 402 int reg_index; 403 int bit_offset; 404 u8 status; 405 406 reg_index = p_dev->QE_bits >> 3; 407 bit_offset = p_dev->QE_bits & 0x7; 408 ret = snor_read_status(reg_index, &status); 409 if (ret != SFC_OK) 410 return ret; 411 412 if (!(status & (1 << bit_offset))) 413 return SFC_OK; 414 415 status &= ~(1 << bit_offset); 416 417 return p_dev->write_status(reg_index, status); 418 } 419 420 int snor_read_data(struct SFNOR_DEV *p_dev, 421 u32 addr, 422 void *p_data, 423 u32 size) 424 { 425 int ret; 426 struct rk_sfc_op op; 427 428 op.sfcmd.d32 = 0; 429 op.sfcmd.b.cmd = p_dev->read_cmd; 430 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 431 432 op.sfctrl.d32 = 0; 433 op.sfctrl.b.datalines = p_dev->read_lines; 434 if (!(size & 0x3) && size >= 4) 435 op.sfctrl.b.enbledma = 1; 436 437 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 438 p_dev->read_cmd == CMD_FAST_READ_X4 || 439 p_dev->read_cmd == CMD_FAST_READ_X2 || 440 p_dev->read_cmd == CMD_FAST_4READ_X4) { 441 op.sfcmd.b.dummybits = 8; 442 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 443 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 444 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 445 op.sfcmd.b.dummybits = 4; 446 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 447 } 448 449 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 450 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 451 452 ret = sfc_request(&op, addr, p_data, size); 453 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 454 455 return ret; 456 } 457 458 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 459 { 460 int ret = SFC_OK; 461 u32 addr, size, len; 462 u8 *p_buf = (u8 *)p_data; 463 464 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 465 466 if ((sec + n_sec) > p_dev->capacity) 467 return SFC_PARAM_ERR; 468 469 addr = sec << 9; 470 size = n_sec << 9; 471 while (size) { 472 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 473 ret = snor_read_data(p_dev, addr, p_buf, len); 474 if (ret != SFC_OK) { 475 rkflash_print_error("snor_read_data %x ret= %x\n", 476 addr >> 9, ret); 477 goto out; 478 } 479 480 size -= len; 481 addr += len; 482 p_buf += len; 483 } 484 out: 485 if (!ret) 486 ret = n_sec; 487 488 return ret; 489 } 490 491 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 492 { 493 int ret = SFC_OK; 494 u32 len, blk_size, offset; 495 u8 *p_buf = (u8 *)p_data; 496 u32 total_sec = n_sec; 497 498 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 499 500 if ((sec + n_sec) > p_dev->capacity) 501 return SFC_PARAM_ERR; 502 503 while (n_sec) { 504 if (sec < 512 || sec >= p_dev->capacity - 512) 505 blk_size = 8; 506 else 507 blk_size = p_dev->blk_size; 508 509 offset = (sec & (blk_size - 1)); 510 if (!offset) { 511 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 512 ERASE_SECTOR : ERASE_BLOCK64K); 513 if (ret != SFC_OK) { 514 rkflash_print_error("snor_erase %x ret= %x\n", 515 sec, ret); 516 goto out; 517 } 518 } 519 len = (blk_size - offset) < n_sec ? 520 (blk_size - offset) : n_sec; 521 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 522 if (ret != SFC_OK) { 523 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 524 goto out; 525 } 526 n_sec -= len; 527 sec += len; 528 p_buf += len << 9; 529 } 530 out: 531 if (!ret) 532 ret = total_sec; 533 534 return ret; 535 } 536 537 int snor_read_id(u8 *data) 538 { 539 int ret; 540 struct rk_sfc_op op; 541 542 op.sfcmd.d32 = 0; 543 op.sfcmd.b.cmd = CMD_READ_JEDECID; 544 545 op.sfctrl.d32 = 0; 546 547 ret = sfc_request(&op, 0, data, 3); 548 549 return ret; 550 } 551 552 static int snor_read_parameter(u32 addr, u8 *data) 553 { 554 int ret; 555 struct rk_sfc_op op; 556 557 op.sfcmd.d32 = 0; 558 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 559 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 560 op.sfcmd.b.dummybits = 8; 561 562 op.sfctrl.d32 = 0; 563 564 ret = sfc_request(&op, addr, data, 1); 565 566 return ret; 567 } 568 569 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 570 { 571 return p_dev->capacity; 572 } 573 574 static struct flash_info *snor_get_flash_info(u8 *flash_id) 575 { 576 u32 i; 577 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 578 579 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 580 if (spi_flash_tbl[i].id == id) 581 return &spi_flash_tbl[i]; 582 } 583 return NULL; 584 } 585 586 /* Adjust flash info in ram base on parameter */ 587 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 588 { 589 u32 addr; 590 u8 para_version; 591 592 if (spi_flash_info->id == 0xc84019) { 593 addr = 0x09; 594 snor_read_parameter(addr, ¶_version); 595 if (para_version == 0x06) { 596 spi_flash_info->QE_bits = 9; 597 spi_flash_info->prog_cmd_4 = 0x34; 598 } 599 } 600 return 0; 601 } 602 603 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 604 struct flash_info *g_spi_flash_info) 605 { 606 int i, ret; 607 608 if (g_spi_flash_info) { 609 snor_flash_info_adjust(g_spi_flash_info); 610 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 611 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 612 p_dev->capacity = 1 << g_spi_flash_info->density; 613 p_dev->blk_size = g_spi_flash_info->block_size; 614 p_dev->page_size = NOR_SECS_PAGE; 615 p_dev->read_cmd = g_spi_flash_info->read_cmd; 616 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 617 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 618 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 619 p_dev->prog_lines = DATA_LINES_X1; 620 p_dev->read_lines = DATA_LINES_X1; 621 p_dev->QE_bits = g_spi_flash_info->QE_bits; 622 p_dev->addr_mode = ADDR_MODE_3BYTE; 623 624 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 625 if (i == 0) 626 p_dev->write_status = snor_write_status; 627 else if (i == 1) 628 p_dev->write_status = snor_write_status1; 629 else if (i == 2) 630 p_dev->write_status = snor_write_status2; 631 632 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 633 ret = SFC_OK; 634 if (g_spi_flash_info->QE_bits) 635 ret = snor_enable_QE(p_dev); 636 if (ret == SFC_OK) { 637 p_dev->read_lines = DATA_LINES_X4; 638 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 639 } 640 } 641 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 642 p_dev->read_lines == DATA_LINES_X4) { 643 p_dev->prog_lines = DATA_LINES_X4; 644 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 645 if ((p_dev->manufacturer == MID_MACRONIX) && 646 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 || 647 p_dev->prog_cmd == CMD_PAGE_PROG_4PP)) 648 p_dev->prog_addr_lines = DATA_LINES_X4; 649 } 650 651 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 652 p_dev->addr_mode = ADDR_MODE_4BYTE; 653 654 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 655 snor_enter_4byte_mode(); 656 } 657 658 return SFC_OK; 659 } 660 661 int snor_init(struct SFNOR_DEV *p_dev) 662 { 663 struct flash_info *g_spi_flash_info; 664 u8 id_byte[5]; 665 666 if (!p_dev) 667 return SFC_PARAM_ERR; 668 669 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 670 p_dev->max_iosize = sfc_get_max_iosize(); 671 672 snor_read_id(id_byte); 673 rkflash_print_error("sfc nor id: %x %x %x\n", 674 id_byte[0], id_byte[1], id_byte[2]); 675 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 676 return SFC_ERROR; 677 678 g_spi_flash_info = snor_get_flash_info(id_byte); 679 if (g_spi_flash_info) { 680 snor_parse_flash_table(p_dev, g_spi_flash_info); 681 } else { 682 p_dev->manufacturer = id_byte[0]; 683 p_dev->mem_type = id_byte[1]; 684 p_dev->capacity = 1 << (id_byte[2] - 9); 685 p_dev->QE_bits = 0; 686 p_dev->blk_size = NOR_SECS_BLK; 687 p_dev->page_size = NOR_SECS_PAGE; 688 p_dev->read_cmd = CMD_READ_DATA; 689 p_dev->prog_cmd = CMD_PAGE_PROG; 690 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 691 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 692 p_dev->prog_lines = DATA_LINES_X1; 693 p_dev->prog_addr_lines = DATA_LINES_X1; 694 p_dev->read_lines = DATA_LINES_X1; 695 p_dev->write_status = snor_write_status; 696 snor_reset_device(); 697 } 698 699 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 700 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 701 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 702 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 703 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 704 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 705 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 706 rkflash_print_info("capacity: %x\n", p_dev->capacity); 707 708 return SFC_OK; 709 } 710 711 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 712 struct snor_info_packet *packet) 713 { 714 struct flash_info g_spi_flash_info; 715 u8 id_byte[5]; 716 int ret; 717 718 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 719 return SFC_PARAM_ERR; 720 721 snor_read_id(id_byte); 722 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 723 return SFC_ERROR; 724 725 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 726 g_spi_flash_info.block_size = NOR_SECS_BLK; 727 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 728 g_spi_flash_info.read_cmd = packet->read_cmd; 729 g_spi_flash_info.prog_cmd = packet->prog_cmd; 730 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 731 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 732 if (id_byte[2] >= 0x19) 733 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 734 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 735 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 736 g_spi_flash_info.feature = packet->feature; 737 g_spi_flash_info.density = id_byte[2] - 9; 738 g_spi_flash_info.QE_bits = packet->QE_bits; 739 740 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 741 742 return ret; 743 } 744 745