1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "sfc_nor.h" 12 #include "rkflash_debug.h" 13 #include "rkflash_blk.h" 14 15 static struct flash_info spi_flash_tbl[] = { 16 /* GD25Q32B */ 17 {0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0}, 18 /* GD25Q64B */ 19 {0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0}, 20 /* GD25Q127C and GD25Q128C*/ 21 {0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 22 /* GD25Q256B */ 23 {0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0}, 24 /* GD25Q512MC */ 25 {0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0}, 26 /* 25Q64JVSSIQ */ 27 {0xef4017, 128, 8, 0x13, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0}, 28 /* 25Q128FV */ 29 {0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0}, 30 /* 25Q256FV */ 31 {0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0}, 32 /* 25Q64FWSSIG */ 33 {0xef6017, 128, 8, 0x13, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0}, 34 /* XT25F128A */ 35 {0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0}, 36 /* MX25L25635E/F */ 37 {0xc22019, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x30, 16, 6, 0}, 38 /* XM25QH64A */ 39 {0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0}, 40 /* XM25QH128A */ 41 {0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0}, 42 /* EN25QH128A */ 43 {0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0}, 44 /* MX25L51245G08G */ 45 {0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x10, 17, 6, 0}, 46 }; 47 48 static const u8 sfnor_dev_code[] = { 49 0x11, 50 0x12, 51 0x13, 52 0x14, 53 0x15, 54 0x16, 55 0x17, 56 0x18, 57 0x19 58 }; 59 60 static const u32 sfnor_capacity[] = { 61 0x20000, /* 128k-byte */ 62 0x40000, /* 256k-byte */ 63 0x80000, /* 512k-byte */ 64 0x100000, /* 1M-byte */ 65 0x200000, /* 2M-byte */ 66 0x400000, /* 4M-byte */ 67 0x800000, /* 8M-byte */ 68 0x1000000, /* 16M-byte */ 69 0x2000000 /* 32M-byte */ 70 }; 71 72 static struct flash_info *g_spi_flash_info; 73 74 static int snor_write_en(void) 75 { 76 int ret; 77 union SFCCMD_DATA sfcmd; 78 79 sfcmd.d32 = 0; 80 sfcmd.b.cmd = CMD_WRITE_EN; 81 82 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 83 84 return ret; 85 } 86 87 static int snor_enter_4byte_mode(void) 88 { 89 int ret; 90 union SFCCMD_DATA sfcmd; 91 92 sfcmd.d32 = 0; 93 sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 94 95 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 96 return ret; 97 } 98 99 static int snor_read_status(u32 reg_index, u8 *status) 100 { 101 int ret; 102 union SFCCMD_DATA sfcmd; 103 u8 read_stat_cmd[] = {CMD_READ_STATUS, 104 CMD_READ_STATUS2, CMD_READ_STATUS3}; 105 sfcmd.d32 = 0; 106 sfcmd.b.cmd = read_stat_cmd[reg_index]; 107 sfcmd.b.datasize = 1; 108 109 ret = sfc_request(sfcmd.d32, 0, 0, status); 110 111 return ret; 112 } 113 114 static int snor_wait_busy(int timeout) 115 { 116 int ret; 117 union SFCCMD_DATA sfcmd; 118 int i; 119 u32 status; 120 121 sfcmd.d32 = 0; 122 sfcmd.b.cmd = CMD_READ_STATUS; 123 sfcmd.b.datasize = 1; 124 125 for (i = 0; i < timeout; i++) { 126 ret = sfc_request(sfcmd.d32, 0, 0, &status); 127 if (ret != SFC_OK) 128 return ret; 129 130 if ((status & 0x01) == 0) 131 return SFC_OK; 132 133 sfc_delay(1); 134 } 135 PRINT_SFC_E("%s error %x\n", __func__, timeout); 136 137 return SFC_BUSY_TIMEOUT; 138 } 139 140 static int snor_write_status2(u32 reg_index, u8 status) 141 { 142 int ret; 143 union SFCCMD_DATA sfcmd; 144 u8 status2[2]; 145 u8 read_index; 146 147 status2[reg_index] = status; 148 read_index = (reg_index == 0) ? 1 : 0; 149 ret = snor_read_status(read_index, &status2[read_index]); 150 if (ret != SFC_OK) 151 return ret; 152 153 snor_write_en(); 154 155 sfcmd.d32 = 0; 156 sfcmd.b.cmd = CMD_WRITE_STATUS; 157 sfcmd.b.datasize = 2; 158 sfcmd.b.rw = SFC_WRITE; 159 160 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 161 if (ret != SFC_OK) 162 return ret; 163 164 ret = snor_wait_busy(10000); /* 10ms */ 165 166 return ret; 167 } 168 169 static int snor_write_status(u32 reg_index, u8 status) 170 { 171 int ret; 172 union SFCCMD_DATA sfcmd; 173 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 174 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 175 snor_write_en(); 176 sfcmd.d32 = 0; 177 sfcmd.b.cmd = write_stat_cmd[reg_index]; 178 sfcmd.b.datasize = 1; 179 sfcmd.b.rw = SFC_WRITE; 180 181 ret = sfc_request(sfcmd.d32, 0, 0, &status); 182 if (ret != SFC_OK) 183 return ret; 184 185 ret = snor_wait_busy(10000); /* 10ms */ 186 187 return ret; 188 } 189 190 static int snor_erase(struct SFNOR_DEV *p_dev, 191 u32 addr, 192 enum NOR_ERASE_TYPE erase_type) 193 { 194 int ret; 195 union SFCCMD_DATA sfcmd; 196 int timeout[] = {400, 2000, 40000}; /* ms */ 197 198 if (erase_type > ERASE_CHIP) 199 return SFC_PARAM_ERR; 200 201 sfcmd.d32 = 0; 202 if (erase_type == ERASE_BLOCK64K) 203 sfcmd.b.cmd = p_dev->blk_erase_cmd; 204 else if (erase_type == ERASE_SECTOR) 205 sfcmd.b.cmd = p_dev->sec_erase_cmd; 206 else 207 sfcmd.b.cmd = CMD_CHIP_ERASE; 208 209 sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 210 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 211 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 212 sfcmd.b.addrbits = SFC_ADDR_32BITS; 213 214 snor_write_en(); 215 216 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 217 if (ret != SFC_OK) 218 return ret; 219 220 ret = snor_wait_busy(timeout[erase_type] * 1000); 221 return ret; 222 } 223 224 static int snor_prog_page(struct SFNOR_DEV *p_dev, 225 u32 addr, 226 void *p_data, 227 u32 size) 228 { 229 int ret; 230 union SFCCMD_DATA sfcmd; 231 union SFCCTRL_DATA sfctrl; 232 233 sfcmd.d32 = 0; 234 sfcmd.b.cmd = p_dev->prog_cmd; 235 sfcmd.b.addrbits = SFC_ADDR_24BITS; 236 sfcmd.b.datasize = size; 237 sfcmd.b.rw = SFC_WRITE; 238 239 sfctrl.d32 = 0; 240 sfctrl.b.datalines = p_dev->prog_lines; 241 sfctrl.b.enbledma = 0; 242 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 243 sfctrl.b.addrlines = SFC_4BITS_LINE; 244 245 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 246 sfcmd.b.addrbits = SFC_ADDR_32BITS; 247 248 snor_write_en(); 249 250 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 251 if (ret != SFC_OK) 252 return ret; 253 254 ret = snor_wait_busy(10000); 255 256 return ret; 257 } 258 259 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 260 { 261 int ret = SFC_OK; 262 u32 page_size, len; 263 u8 *p_buf = (u8 *)p_data; 264 265 page_size = NOR_PAGE_SIZE; 266 while (size) { 267 len = page_size < size ? page_size : size; 268 ret = snor_prog_page(p_dev, addr, p_buf, len); 269 if (ret != SFC_OK) 270 return ret; 271 272 size -= len; 273 addr += len; 274 p_buf += len; 275 } 276 277 return ret; 278 } 279 280 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 281 { 282 int ret = SFC_OK; 283 int reg_index; 284 int bit_offset; 285 u8 status; 286 287 if (p_dev->manufacturer == MID_GIGADEV || 288 p_dev->manufacturer == MID_WINBOND) { 289 reg_index = p_dev->QE_bits >> 3; 290 bit_offset = p_dev->QE_bits & 0x7; 291 ret = snor_read_status(reg_index, &status); 292 if (ret != SFC_OK) 293 return ret; 294 295 if (status & (1 << bit_offset)) /* is QE bit set */ 296 return SFC_OK; 297 298 status |= (1 << bit_offset); 299 return p_dev->write_status(reg_index, status); 300 } 301 302 return ret; 303 } 304 305 #if (SNOR_4BIT_DATA_DETECT_EN) 306 static int snor_set_dlines(struct SFNOR_DEV *p_dev, enum SFC_DATA_LINES lines) 307 { 308 int ret; 309 u8 read_cmd[] = {CMD_FAST_READ_X1, CMD_FAST_READ_X2, CMD_FAST_READ_X4}; 310 311 if (lines == DATA_LINES_X4) { 312 ret = snor_enable_QE(p_dev); 313 if (ret != SFC_OK) 314 return ret; 315 } 316 317 p_dev->read_lines = lines; 318 p_dev->read_cmd = read_cmd[lines]; 319 320 if (p_dev->manufacturer == MID_GIGADEV || 321 p_dev->manufacturer == MID_WINBOND || 322 p_dev->manufacturer == MID_MACRONIX) { 323 p_dev->prog_lines = (lines != DATA_LINES_X2) ? 324 lines : DATA_LINES_X1; 325 if (lines == DATA_LINES_X1) { 326 p_dev->prog_cmd = CMD_PAGE_PROG; 327 } else { 328 if (p_dev->manufacturer == MID_GIGADEV || 329 p_dev->manufacturer == MID_WINBOND) 330 p_dev->prog_cmd = CMD_PAGE_PROG_X4; 331 else 332 p_dev->prog_cmd = CMD_PAGE_PROG_A4; 333 } 334 } 335 336 return SFC_OK; 337 } 338 #endif 339 340 static int snor_read_data(struct SFNOR_DEV *p_dev, 341 u32 addr, 342 void *p_data, 343 u32 size) 344 { 345 int ret; 346 union SFCCMD_DATA sfcmd; 347 union SFCCTRL_DATA sfctrl; 348 349 sfcmd.d32 = 0; 350 sfcmd.b.cmd = p_dev->read_cmd; 351 sfcmd.b.datasize = size; 352 sfcmd.b.addrbits = SFC_ADDR_24BITS; 353 354 sfctrl.d32 = 0; 355 sfctrl.b.datalines = p_dev->read_lines; 356 if (!(size & 0x3) && size >= 4) 357 sfctrl.b.enbledma = 0; 358 359 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 360 p_dev->read_cmd == CMD_FAST_READ_X4 || 361 p_dev->read_cmd == CMD_FAST_READ_X2 || 362 p_dev->read_cmd == CMD_FAST_4READ_X4) { 363 sfcmd.b.dummybits = 8; 364 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 365 sfcmd.b.addrbits = SFC_ADDR_32BITS; 366 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 367 sfcmd.b.dummybits = 4; 368 sfctrl.b.addrlines = SFC_4BITS_LINE; 369 } 370 371 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 372 sfcmd.b.addrbits = SFC_ADDR_32BITS; 373 374 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 375 376 return ret; 377 } 378 379 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 380 { 381 int ret = SFC_OK; 382 u32 addr, size, len; 383 u8 *p_buf = (u8 *)p_data; 384 385 if ((sec + n_sec) > p_dev->capacity) 386 return SFC_PARAM_ERR; 387 388 mutex_lock(&p_dev->lock); 389 addr = sec << 9; 390 size = n_sec << 9; 391 while (size) { 392 len = size < SFC_MAX_IOSIZE ? size : SFC_MAX_IOSIZE; 393 ret = snor_read_data(p_dev, addr, p_buf, len); 394 if (ret != SFC_OK) { 395 PRINT_SFC_E("snor_read_data %x ret= %x\n", 396 addr >> 9, ret); 397 goto out; 398 } 399 400 size -= len; 401 addr += len; 402 p_buf += len; 403 } 404 out: 405 mutex_unlock(&p_dev->lock); 406 if (!ret) 407 ret = n_sec; 408 409 return ret; 410 } 411 412 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, const void *p_data) 413 { 414 int ret = SFC_OK; 415 u32 len, blk_size, offset; 416 u8 *p_buf = (u8 *)p_data; 417 u32 total_sec = n_sec; 418 419 if ((sec + n_sec) > p_dev->capacity) 420 return SFC_PARAM_ERR; 421 422 mutex_lock(&p_dev->lock); 423 while (n_sec) { 424 if (sec < 512 || sec >= p_dev->capacity - 512) 425 blk_size = 8; 426 else 427 blk_size = p_dev->blk_size; 428 429 offset = (sec & (blk_size - 1)); 430 if (!offset) { 431 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 432 ERASE_SECTOR : ERASE_BLOCK64K); 433 if (ret != SFC_OK) { 434 PRINT_SFC_E("snor_erase %x ret= %x\n", 435 sec, ret); 436 goto out; 437 } 438 } 439 len = (blk_size - offset) < n_sec ? 440 (blk_size - offset) : n_sec; 441 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 442 if (ret != SFC_OK) { 443 PRINT_SFC_E("snor_prog %x ret= %x\n", sec, ret); 444 goto out; 445 } 446 n_sec -= len; 447 sec += len; 448 p_buf += len << 9; 449 } 450 out: 451 mutex_unlock(&p_dev->lock); 452 if (!ret) 453 ret = total_sec; 454 455 return ret; 456 } 457 458 static int snor_read_id(u8 *data) 459 { 460 int ret; 461 union SFCCMD_DATA sfcmd; 462 463 sfcmd.d32 = 0; 464 sfcmd.b.cmd = CMD_READ_JEDECID; 465 sfcmd.b.datasize = 3; 466 467 ret = sfc_request(sfcmd.d32, 0, 0, data); 468 469 return ret; 470 } 471 472 static int snor_read_parameter(u32 addr, u8 *data) 473 { 474 int ret; 475 union SFCCMD_DATA sfcmd; 476 477 sfcmd.d32 = 0; 478 sfcmd.b.cmd = CMD_READ_PARAMETER; 479 sfcmd.b.datasize = 1; 480 sfcmd.b.addrbits = SFC_ADDR_24BITS; 481 sfcmd.b.dummybits = 8; 482 483 ret = sfc_request(sfcmd.d32, 0, addr, data); 484 485 return ret; 486 } 487 488 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 489 { 490 return p_dev->capacity; 491 } 492 493 static void snor_print_spi_chip_info(struct SFNOR_DEV *p_dev) 494 { 495 PRINT_SFC_I("addr_mode: %x\n", p_dev->addr_mode); 496 PRINT_SFC_I("read_lines: %x\n", p_dev->read_lines); 497 PRINT_SFC_I("prog_lines: %x\n", p_dev->prog_lines); 498 PRINT_SFC_I("read_cmd: %x\n", p_dev->read_cmd); 499 PRINT_SFC_I("prog_cmd: %x\n", p_dev->prog_cmd); 500 PRINT_SFC_I("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 501 PRINT_SFC_I("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 502 } 503 504 static struct flash_info *snor_get_flash_info(u8 *flash_id) 505 { 506 u32 i; 507 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 508 509 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 510 if (spi_flash_tbl[i].id == id) 511 return &spi_flash_tbl[i]; 512 } 513 return NULL; 514 } 515 516 /* Adjust flash info in ram base on parameter */ 517 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 518 { 519 u32 addr; 520 u8 para_version; 521 522 if (spi_flash_info->id == 0xc84019) { 523 addr = 0x09; 524 snor_read_parameter(addr, ¶_version); 525 if (para_version == 0x06) { 526 spi_flash_info->QE_bits = 9; 527 spi_flash_info->prog_cmd_4 = 0x34; 528 } 529 } 530 return 0; 531 } 532 533 int snor_init(struct SFNOR_DEV *p_dev) 534 { 535 u32 i; 536 u8 id_byte[5]; 537 int err; 538 539 memset(p_dev, 0, sizeof(struct SFNOR_DEV)); 540 snor_read_id(id_byte); 541 PRINT_SFC_E("sfc nor id: %x %x %x\n", 542 id_byte[0], id_byte[1], id_byte[2]); 543 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) { 544 err = SFC_ERROR; 545 goto err_out; 546 } 547 548 p_dev->manufacturer = id_byte[0]; 549 p_dev->mem_type = id_byte[1]; 550 551 mutex_init(&p_dev->lock); 552 g_spi_flash_info = snor_get_flash_info(id_byte); 553 if (g_spi_flash_info) { 554 snor_flash_info_adjust(g_spi_flash_info); 555 p_dev->capacity = 1 << g_spi_flash_info->density; 556 p_dev->blk_size = g_spi_flash_info->block_size; 557 p_dev->page_size = NOR_SECS_PAGE; 558 p_dev->read_cmd = g_spi_flash_info->read_cmd; 559 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 560 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 561 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 562 p_dev->prog_lines = DATA_LINES_X1; 563 p_dev->read_lines = DATA_LINES_X1; 564 p_dev->QE_bits = g_spi_flash_info->QE_bits; 565 566 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 567 if (i == 0) 568 p_dev->write_status = snor_write_status; 569 else 570 p_dev->write_status = snor_write_status2; 571 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 572 if (snor_enable_QE(p_dev) == SFC_OK) { 573 p_dev->read_lines = DATA_LINES_X4; 574 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 575 } 576 } 577 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 578 p_dev->read_lines == DATA_LINES_X4) { 579 p_dev->prog_lines = DATA_LINES_X4; 580 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 581 } 582 583 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 584 p_dev->addr_mode = ADDR_MODE_4BYTE; 585 586 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 587 snor_enter_4byte_mode(); 588 589 goto normal_out; 590 } 591 592 for (i = 0; i < sizeof(sfnor_dev_code); i++) { 593 if (id_byte[2] == sfnor_dev_code[i]) { 594 p_dev->capacity = sfnor_capacity[i] >> 9; 595 break; 596 } 597 } 598 599 if (i >= sizeof(sfnor_dev_code)) { 600 err = SFC_ERROR; 601 goto err_out; 602 } 603 604 p_dev->QE_bits = 9; 605 p_dev->blk_size = NOR_SECS_BLK; 606 p_dev->page_size = NOR_SECS_PAGE; 607 p_dev->read_cmd = CMD_READ_DATA; 608 p_dev->prog_cmd = CMD_PAGE_PROG; 609 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 610 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 611 p_dev->write_status = snor_write_status2; 612 #if (SNOR_4BIT_DATA_DETECT_EN) 613 snor_set_dlines(p_dev, DATA_LINES_X4); 614 #endif 615 616 normal_out: 617 snor_print_spi_chip_info(p_dev); 618 619 return SFC_OK; 620 621 err_out: 622 return err; 623 } 624 625