1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C/E */ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D/E */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 25 /* GD25LQ64C */ 26 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 27 /* GD25LQ32E */ 28 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 29 /* GD25B512MEYIG */ 30 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 31 32 /* W25Q32JV */ 33 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 34 /* W25Q64JVSSIQ */ 35 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 36 /* W25Q128FV and W25Q128JV*/ 37 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 38 /* W25Q256F/J */ 39 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 40 /* W25Q32JW */ 41 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 42 /* W25Q256JWEQ*/ 43 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 44 /* W25Q64FWSSIG */ 45 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 46 /* W25Q128JVSIM */ 47 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 48 /* W25Q256JVEM */ 49 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 50 51 /* MX25L3233FM2I-08G */ 52 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 53 /* MX25L6433F */ 54 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 55 /* MX25L12835E/F MX25L12833FMI-10G */ 56 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 57 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */ 58 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 59 /* MX25L51245GMI */ 60 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 61 /* MX25U51245G */ 62 { 0xc2253a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 63 /* MX25U3232F */ 64 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 65 /* MX25U6432F */ 66 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 67 /* MX25U12832F */ 68 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 69 /* MX25U25645GZ4I-00 */ 70 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 71 72 /* XM25QH32C */ 73 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 74 /* XM25QH64B */ 75 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 76 /* XM25QH128B */ 77 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 78 /* XM25QH(QU)256B */ 79 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 80 /* XM25QH64A */ 81 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 82 83 /* XT25F128A XM25QH128A */ 84 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 85 /* XT25F64BSSIGU-5 */ 86 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 87 /* XT25F128BSSIGU */ 88 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 89 /* XT25F256BSFIGU */ 90 { 0x0b4019, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 16, 9, 0 }, 91 /* XT25F32BS */ 92 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 93 /* XT25F16BS */ 94 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 95 96 /* EN25QH64A */ 97 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 98 /* EN25QH128A */ 99 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 100 /* EN25QH32B */ 101 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 102 /* EN25S32A */ 103 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 104 /* EN25S64A */ 105 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 106 /* EN25QH256A */ 107 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 108 109 /* P25Q64H */ 110 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 111 /* P25Q128H */ 112 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 113 /* P25Q16H-SUH-IT */ 114 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 115 /* FM25Q64A */ 116 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 117 /* FM25M64C */ 118 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 119 120 /* ZB25VQ64 */ 121 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 122 /* ZB25VQ128 */ 123 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 124 /* ZB25LQ128 */ 125 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 126 127 /* BH25Q128AS */ 128 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 129 /* BH25Q64BS */ 130 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 131 132 /* P25Q64H */ 133 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 134 /* P25Q32SH-SSH-IT */ 135 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 136 137 /* FM25Q128A */ 138 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 139 /* FM25Q64-SOB-T-G */ 140 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 141 142 /* FM25Q64A */ 143 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 144 /* FM25M4AA */ 145 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 146 /* DS25M4AB-1AIB4 */ 147 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 148 }; 149 150 static int snor_write_en(void) 151 { 152 int ret; 153 struct rk_sfc_op op; 154 155 op.sfcmd.d32 = 0; 156 op.sfcmd.b.cmd = CMD_WRITE_EN; 157 158 op.sfctrl.d32 = 0; 159 160 ret = sfc_request(&op, 0, NULL, 0); 161 162 return ret; 163 } 164 165 int snor_reset_device(void) 166 { 167 struct rk_sfc_op op; 168 169 op.sfcmd.d32 = 0; 170 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 171 172 op.sfctrl.d32 = 0; 173 sfc_request(&op, 0, NULL, 0); 174 175 op.sfcmd.d32 = 0; 176 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 177 178 op.sfctrl.d32 = 0; 179 sfc_request(&op, 0, NULL, 0); 180 /* tRST=30us , delay 1ms here */ 181 sfc_delay(1000); 182 183 return SFC_OK; 184 } 185 186 static int snor_enter_4byte_mode(void) 187 { 188 int ret; 189 struct rk_sfc_op op; 190 191 op.sfcmd.d32 = 0; 192 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 193 194 op.sfctrl.d32 = 0; 195 196 ret = sfc_request(&op, 0, NULL, 0); 197 return ret; 198 } 199 200 static int snor_read_status(u32 reg_index, u8 *status) 201 { 202 int ret; 203 struct rk_sfc_op op; 204 u8 read_stat_cmd[] = {CMD_READ_STATUS, 205 CMD_READ_STATUS2, CMD_READ_STATUS3}; 206 op.sfcmd.d32 = 0; 207 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 208 209 op.sfctrl.d32 = 0; 210 ret = sfc_request(&op, 0, status, 1); 211 212 return ret; 213 } 214 215 static int snor_wait_busy(int timeout) 216 { 217 int ret; 218 struct rk_sfc_op op; 219 int i; 220 u32 status; 221 222 op.sfcmd.d32 = 0; 223 op.sfcmd.b.cmd = CMD_READ_STATUS; 224 225 op.sfctrl.d32 = 0; 226 227 for (i = 0; i < timeout; i++) { 228 ret = sfc_request(&op, 0, &status, 1); 229 if (ret != SFC_OK) 230 return ret; 231 232 if ((status & 0x01) == 0) 233 return SFC_OK; 234 235 sfc_delay(1); 236 } 237 rkflash_print_error("%s error %x\n", __func__, timeout); 238 239 return SFC_BUSY_TIMEOUT; 240 } 241 242 static int snor_write_status2(u32 reg_index, u8 status) 243 { 244 int ret; 245 struct rk_sfc_op op; 246 u8 status2[2]; 247 248 status2[reg_index] = status; 249 if (reg_index == 0) 250 ret = snor_read_status(2, &status2[1]); 251 else 252 ret = snor_read_status(0, &status2[0]); 253 if (ret != SFC_OK) 254 return ret; 255 256 snor_write_en(); 257 258 op.sfcmd.d32 = 0; 259 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 260 op.sfcmd.b.rw = SFC_WRITE; 261 262 op.sfctrl.d32 = 0; 263 264 ret = sfc_request(&op, 0, &status2[0], 2); 265 if (ret != SFC_OK) 266 return ret; 267 268 ret = snor_wait_busy(10000); /* 10ms */ 269 270 return ret; 271 } 272 273 static int snor_write_status1(u32 reg_index, u8 status) 274 { 275 int ret; 276 struct rk_sfc_op op; 277 u8 status2[2]; 278 u8 read_index; 279 280 status2[reg_index] = status; 281 read_index = (reg_index == 0) ? 1 : 0; 282 ret = snor_read_status(read_index, &status2[read_index]); 283 if (ret != SFC_OK) 284 return ret; 285 286 snor_write_en(); 287 288 op.sfcmd.d32 = 0; 289 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 290 op.sfcmd.b.rw = SFC_WRITE; 291 292 op.sfctrl.d32 = 0; 293 294 ret = sfc_request(&op, 0, &status2[0], 2); 295 if (ret != SFC_OK) 296 return ret; 297 298 ret = snor_wait_busy(10000); /* 10ms */ 299 300 return ret; 301 } 302 303 static int snor_write_status(u32 reg_index, u8 status) 304 { 305 int ret; 306 struct rk_sfc_op op; 307 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 308 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 309 snor_write_en(); 310 op.sfcmd.d32 = 0; 311 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 312 op.sfcmd.b.rw = SFC_WRITE; 313 314 op.sfctrl.d32 = 0; 315 316 ret = sfc_request(&op, 0, &status, 1); 317 if (ret != SFC_OK) 318 return ret; 319 320 ret = snor_wait_busy(10000); /* 10ms */ 321 322 return ret; 323 } 324 325 int snor_erase(struct SFNOR_DEV *p_dev, 326 u32 addr, 327 enum NOR_ERASE_TYPE erase_type) 328 { 329 int ret; 330 struct rk_sfc_op op; 331 int timeout[] = {400, 2000, 40000}; /* ms */ 332 333 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 334 335 if (erase_type > ERASE_CHIP) 336 return SFC_PARAM_ERR; 337 338 op.sfcmd.d32 = 0; 339 if (erase_type == ERASE_BLOCK64K) 340 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 341 else if (erase_type == ERASE_SECTOR) 342 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 343 else 344 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 345 346 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 347 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 348 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 349 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 350 351 op.sfctrl.d32 = 0; 352 353 snor_write_en(); 354 355 ret = sfc_request(&op, addr, NULL, 0); 356 if (ret != SFC_OK) 357 return ret; 358 359 ret = snor_wait_busy(timeout[erase_type] * 1000); 360 return ret; 361 } 362 363 int snor_prog_page(struct SFNOR_DEV *p_dev, 364 u32 addr, 365 void *p_data, 366 u32 size) 367 { 368 int ret; 369 struct rk_sfc_op op; 370 371 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 372 373 op.sfcmd.d32 = 0; 374 op.sfcmd.b.cmd = p_dev->prog_cmd; 375 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 376 op.sfcmd.b.rw = SFC_WRITE; 377 378 op.sfctrl.d32 = 0; 379 op.sfctrl.b.datalines = p_dev->prog_lines; 380 op.sfctrl.b.enbledma = 1; 381 op.sfctrl.b.addrlines = p_dev->prog_addr_lines; 382 383 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 384 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 385 386 snor_write_en(); 387 388 ret = sfc_request(&op, addr, p_data, size); 389 if (ret != SFC_OK) 390 return ret; 391 392 ret = snor_wait_busy(10000); 393 394 return ret; 395 } 396 397 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 398 { 399 int ret = SFC_OK; 400 u32 page_size, len; 401 u8 *p_buf = (u8 *)p_data; 402 403 page_size = NOR_PAGE_SIZE; 404 while (size) { 405 len = page_size < size ? page_size : size; 406 ret = snor_prog_page(p_dev, addr, p_buf, len); 407 if (ret != SFC_OK) 408 return ret; 409 410 size -= len; 411 addr += len; 412 p_buf += len; 413 } 414 415 return ret; 416 } 417 418 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 419 { 420 int ret = SFC_OK; 421 int reg_index; 422 int bit_offset; 423 u8 status; 424 425 reg_index = p_dev->QE_bits >> 3; 426 bit_offset = p_dev->QE_bits & 0x7; 427 ret = snor_read_status(reg_index, &status); 428 if (ret != SFC_OK) 429 return ret; 430 431 if (status & (1 << bit_offset)) /* is QE bit set */ 432 return SFC_OK; 433 434 status |= (1 << bit_offset); 435 436 return p_dev->write_status(reg_index, status); 437 } 438 439 int snor_disable_QE(struct SFNOR_DEV *p_dev) 440 { 441 int ret = SFC_OK; 442 int reg_index; 443 int bit_offset; 444 u8 status; 445 446 reg_index = p_dev->QE_bits >> 3; 447 bit_offset = p_dev->QE_bits & 0x7; 448 ret = snor_read_status(reg_index, &status); 449 if (ret != SFC_OK) 450 return ret; 451 452 if (!(status & (1 << bit_offset))) 453 return SFC_OK; 454 455 status &= ~(1 << bit_offset); 456 457 return p_dev->write_status(reg_index, status); 458 } 459 460 int snor_read_data(struct SFNOR_DEV *p_dev, 461 u32 addr, 462 void *p_data, 463 u32 size) 464 { 465 int ret; 466 struct rk_sfc_op op; 467 468 op.sfcmd.d32 = 0; 469 op.sfcmd.b.cmd = p_dev->read_cmd; 470 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 471 472 op.sfctrl.d32 = 0; 473 op.sfctrl.b.datalines = p_dev->read_lines; 474 if (!(size & 0x3) && size >= 4) 475 op.sfctrl.b.enbledma = 1; 476 477 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 478 p_dev->read_cmd == CMD_FAST_READ_X4 || 479 p_dev->read_cmd == CMD_FAST_READ_X2 || 480 p_dev->read_cmd == CMD_FAST_4READ_X4) { 481 op.sfcmd.b.dummybits = 8; 482 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 483 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 484 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 485 op.sfcmd.b.dummybits = 4; 486 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 487 } 488 489 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 490 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 491 492 ret = sfc_request(&op, addr, p_data, size); 493 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 494 495 return ret; 496 } 497 498 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 499 { 500 int ret = SFC_OK; 501 u32 addr, size, len; 502 u8 *p_buf = (u8 *)p_data; 503 504 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 505 506 if ((sec + n_sec) > p_dev->capacity) 507 return SFC_PARAM_ERR; 508 509 addr = sec << 9; 510 size = n_sec << 9; 511 while (size) { 512 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 513 ret = snor_read_data(p_dev, addr, p_buf, len); 514 if (ret != SFC_OK) { 515 rkflash_print_error("snor_read_data %x ret= %x\n", 516 addr >> 9, ret); 517 goto out; 518 } 519 520 size -= len; 521 addr += len; 522 p_buf += len; 523 } 524 out: 525 if (!ret) 526 ret = n_sec; 527 528 return ret; 529 } 530 531 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 532 { 533 int ret = SFC_OK; 534 u32 len, blk_size, offset; 535 u8 *p_buf = (u8 *)p_data; 536 u32 total_sec = n_sec; 537 538 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 539 540 if ((sec + n_sec) > p_dev->capacity) 541 return SFC_PARAM_ERR; 542 543 while (n_sec) { 544 if (sec < 512 || sec >= p_dev->capacity - 512) 545 blk_size = 8; 546 else 547 blk_size = p_dev->blk_size; 548 549 offset = (sec & (blk_size - 1)); 550 if (!offset) { 551 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 552 ERASE_SECTOR : ERASE_BLOCK64K); 553 if (ret != SFC_OK) { 554 rkflash_print_error("snor_erase %x ret= %x\n", 555 sec, ret); 556 goto out; 557 } 558 } 559 len = (blk_size - offset) < n_sec ? 560 (blk_size - offset) : n_sec; 561 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 562 if (ret != SFC_OK) { 563 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 564 goto out; 565 } 566 n_sec -= len; 567 sec += len; 568 p_buf += len << 9; 569 } 570 out: 571 if (!ret) 572 ret = total_sec; 573 574 return ret; 575 } 576 577 int snor_read_id(u8 *data) 578 { 579 int ret; 580 struct rk_sfc_op op; 581 582 op.sfcmd.d32 = 0; 583 op.sfcmd.b.cmd = CMD_READ_JEDECID; 584 585 op.sfctrl.d32 = 0; 586 587 ret = sfc_request(&op, 0, data, 3); 588 589 return ret; 590 } 591 592 static int snor_read_parameter(u32 addr, u8 *data) 593 { 594 int ret; 595 struct rk_sfc_op op; 596 597 op.sfcmd.d32 = 0; 598 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 599 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 600 op.sfcmd.b.dummybits = 8; 601 602 op.sfctrl.d32 = 0; 603 604 ret = sfc_request(&op, addr, data, 1); 605 606 return ret; 607 } 608 609 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 610 { 611 return p_dev->capacity; 612 } 613 614 static struct flash_info *snor_get_flash_info(u8 *flash_id) 615 { 616 u32 i; 617 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 618 619 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 620 if (spi_flash_tbl[i].id == id) 621 return &spi_flash_tbl[i]; 622 } 623 return NULL; 624 } 625 626 /* Adjust flash info in ram base on parameter */ 627 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 628 { 629 u32 addr; 630 u8 para_version; 631 632 if (spi_flash_info->id == 0xc84019) { 633 addr = 0x09; 634 snor_read_parameter(addr, ¶_version); 635 if (para_version == 0x06) { 636 spi_flash_info->QE_bits = 9; 637 spi_flash_info->prog_cmd_4 = 0x34; 638 } 639 } 640 return 0; 641 } 642 643 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 644 struct flash_info *g_spi_flash_info) 645 { 646 int i, ret; 647 648 if (g_spi_flash_info) { 649 snor_flash_info_adjust(g_spi_flash_info); 650 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 651 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 652 p_dev->capacity = 1 << g_spi_flash_info->density; 653 p_dev->blk_size = g_spi_flash_info->block_size; 654 p_dev->page_size = NOR_SECS_PAGE; 655 p_dev->read_cmd = g_spi_flash_info->read_cmd; 656 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 657 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 658 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 659 p_dev->prog_lines = DATA_LINES_X1; 660 p_dev->read_lines = DATA_LINES_X1; 661 p_dev->QE_bits = g_spi_flash_info->QE_bits; 662 p_dev->addr_mode = ADDR_MODE_3BYTE; 663 664 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 665 if (i == 0) 666 p_dev->write_status = snor_write_status; 667 else if (i == 1) 668 p_dev->write_status = snor_write_status1; 669 else if (i == 2) 670 p_dev->write_status = snor_write_status2; 671 672 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 673 ret = SFC_OK; 674 if (g_spi_flash_info->QE_bits) 675 ret = snor_enable_QE(p_dev); 676 if (ret == SFC_OK) { 677 p_dev->read_lines = DATA_LINES_X4; 678 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 679 } 680 } 681 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 682 p_dev->read_lines == DATA_LINES_X4) { 683 p_dev->prog_lines = DATA_LINES_X4; 684 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 685 if ((p_dev->manufacturer == MID_MACRONIX) && 686 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 || 687 p_dev->prog_cmd == CMD_PAGE_PROG_4PP)) 688 p_dev->prog_addr_lines = DATA_LINES_X4; 689 } 690 691 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 692 p_dev->addr_mode = ADDR_MODE_4BYTE; 693 694 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 695 snor_enter_4byte_mode(); 696 } 697 698 return SFC_OK; 699 } 700 701 int snor_init(struct SFNOR_DEV *p_dev) 702 { 703 struct flash_info *g_spi_flash_info; 704 u8 id_byte[5]; 705 706 if (!p_dev) 707 return SFC_PARAM_ERR; 708 709 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 710 p_dev->max_iosize = sfc_get_max_iosize(); 711 712 snor_read_id(id_byte); 713 rkflash_print_error("sfc nor id: %x %x %x\n", 714 id_byte[0], id_byte[1], id_byte[2]); 715 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 716 return SFC_ERROR; 717 718 g_spi_flash_info = snor_get_flash_info(id_byte); 719 if (g_spi_flash_info) { 720 snor_parse_flash_table(p_dev, g_spi_flash_info); 721 } else { 722 p_dev->manufacturer = id_byte[0]; 723 p_dev->mem_type = id_byte[1]; 724 p_dev->capacity = 1 << (id_byte[2] - 9); 725 p_dev->QE_bits = 0; 726 p_dev->blk_size = NOR_SECS_BLK; 727 p_dev->page_size = NOR_SECS_PAGE; 728 p_dev->read_cmd = CMD_READ_DATA; 729 p_dev->prog_cmd = CMD_PAGE_PROG; 730 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 731 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 732 p_dev->prog_lines = DATA_LINES_X1; 733 p_dev->prog_addr_lines = DATA_LINES_X1; 734 p_dev->read_lines = DATA_LINES_X1; 735 p_dev->write_status = snor_write_status; 736 snor_reset_device(); 737 } 738 739 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 740 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 741 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 742 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 743 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 744 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 745 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 746 rkflash_print_info("capacity: %x\n", p_dev->capacity); 747 748 return SFC_OK; 749 } 750 751 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 752 struct snor_info_packet *packet) 753 { 754 struct flash_info g_spi_flash_info; 755 u8 id_byte[5]; 756 int ret; 757 758 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 759 return SFC_PARAM_ERR; 760 761 snor_read_id(id_byte); 762 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 763 return SFC_ERROR; 764 765 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 766 g_spi_flash_info.block_size = NOR_SECS_BLK; 767 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 768 g_spi_flash_info.read_cmd = packet->read_cmd; 769 g_spi_flash_info.prog_cmd = packet->prog_cmd; 770 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 771 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 772 if (id_byte[2] >= 0x19) 773 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 774 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 775 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 776 g_spi_flash_info.feature = packet->feature; 777 g_spi_flash_info.density = id_byte[2] - 9; 778 g_spi_flash_info.QE_bits = packet->QE_bits; 779 780 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 781 782 return ret; 783 } 784 785