1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C*/ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 25 /* 25Q64JVSSIQ */ 26 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 27 /* 25Q128FV and 25Q128JV*/ 28 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 29 /* 25Q256F/J */ 30 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 31 /* 25Q64FWSSIG */ 32 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 33 /* MX25L6433F */ 34 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 35 /* MX25L12835E/F MX25L12833FMI-10G */ 36 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 37 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 38 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 39 /* MX25L51245GMI */ 40 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 41 /* XM25QH32C */ 42 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 43 /* XM25QH64B */ 44 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 45 /* XM25QH128B */ 46 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 47 /* XM25QH(QU)256B */ 48 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 49 /* XM25QH64A */ 50 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 51 /* XT25F128A XM25QH128A */ 52 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0 }, 53 /* XT25F64BSSIGU-5 */ 54 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 55 /* XT25F128BSSIGU */ 56 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 57 /* EN25QH64A */ 58 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 59 /* EN25QH128A */ 60 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 61 /* EN25QH32B */ 62 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 63 /* EN25S32A */ 64 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 65 /* EN25S64A */ 66 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 67 /* P25Q64H */ 68 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 69 /* EN25QH256A */ 70 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 71 /* FM25Q64A */ 72 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 73 /* ZB25VQ64 */ 74 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 75 /* ZB25VQ128 */ 76 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 77 /* 25Q256JVEM */ 78 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 79 /* BH25Q128AS */ 80 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 15, 9, 0 }, 81 /* BH25Q64BS */ 82 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x04, 14, 9, 0 }, 83 }; 84 85 static int snor_write_en(void) 86 { 87 int ret; 88 struct rk_sfc_op op; 89 90 op.sfcmd.d32 = 0; 91 op.sfcmd.b.cmd = CMD_WRITE_EN; 92 93 op.sfctrl.d32 = 0; 94 95 ret = sfc_request(&op, 0, NULL, 0); 96 97 return ret; 98 } 99 100 int snor_reset_device(void) 101 { 102 struct rk_sfc_op op; 103 104 op.sfcmd.d32 = 0; 105 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 106 107 op.sfctrl.d32 = 0; 108 sfc_request(&op, 0, NULL, 0); 109 110 op.sfcmd.d32 = 0; 111 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 112 113 op.sfctrl.d32 = 0; 114 sfc_request(&op, 0, NULL, 0); 115 /* tRST=30us , delay 1ms here */ 116 sfc_delay(1000); 117 118 return SFC_OK; 119 } 120 121 static int snor_enter_4byte_mode(void) 122 { 123 int ret; 124 struct rk_sfc_op op; 125 126 op.sfcmd.d32 = 0; 127 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 128 129 op.sfctrl.d32 = 0; 130 131 ret = sfc_request(&op, 0, NULL, 0); 132 return ret; 133 } 134 135 static int snor_read_status(u32 reg_index, u8 *status) 136 { 137 int ret; 138 struct rk_sfc_op op; 139 u8 read_stat_cmd[] = {CMD_READ_STATUS, 140 CMD_READ_STATUS2, CMD_READ_STATUS3}; 141 op.sfcmd.d32 = 0; 142 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 143 144 op.sfctrl.d32 = 0; 145 ret = sfc_request(&op, 0, status, 1); 146 147 return ret; 148 } 149 150 static int snor_wait_busy(int timeout) 151 { 152 int ret; 153 struct rk_sfc_op op; 154 int i; 155 u32 status; 156 157 op.sfcmd.d32 = 0; 158 op.sfcmd.b.cmd = CMD_READ_STATUS; 159 160 op.sfctrl.d32 = 0; 161 162 for (i = 0; i < timeout; i++) { 163 ret = sfc_request(&op, 0, &status, 1); 164 if (ret != SFC_OK) 165 return ret; 166 167 if ((status & 0x01) == 0) 168 return SFC_OK; 169 170 sfc_delay(1); 171 } 172 rkflash_print_error("%s error %x\n", __func__, timeout); 173 174 return SFC_BUSY_TIMEOUT; 175 } 176 177 static int snor_write_status2(u32 reg_index, u8 status) 178 { 179 int ret; 180 struct rk_sfc_op op; 181 u8 status2[2]; 182 183 status2[reg_index] = status; 184 if (reg_index == 0) 185 ret = snor_read_status(2, &status2[1]); 186 else 187 ret = snor_read_status(0, &status2[0]); 188 if (ret != SFC_OK) 189 return ret; 190 191 snor_write_en(); 192 193 op.sfcmd.d32 = 0; 194 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 195 op.sfcmd.b.rw = SFC_WRITE; 196 197 op.sfctrl.d32 = 0; 198 199 ret = sfc_request(&op, 0, &status2[0], 2); 200 if (ret != SFC_OK) 201 return ret; 202 203 ret = snor_wait_busy(10000); /* 10ms */ 204 205 return ret; 206 } 207 208 static int snor_write_status1(u32 reg_index, u8 status) 209 { 210 int ret; 211 struct rk_sfc_op op; 212 u8 status2[2]; 213 u8 read_index; 214 215 status2[reg_index] = status; 216 read_index = (reg_index == 0) ? 1 : 0; 217 ret = snor_read_status(read_index, &status2[read_index]); 218 if (ret != SFC_OK) 219 return ret; 220 221 snor_write_en(); 222 223 op.sfcmd.d32 = 0; 224 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 225 op.sfcmd.b.rw = SFC_WRITE; 226 227 op.sfctrl.d32 = 0; 228 229 ret = sfc_request(&op, 0, &status2[0], 2); 230 if (ret != SFC_OK) 231 return ret; 232 233 ret = snor_wait_busy(10000); /* 10ms */ 234 235 return ret; 236 } 237 238 static int snor_write_status(u32 reg_index, u8 status) 239 { 240 int ret; 241 struct rk_sfc_op op; 242 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 243 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 244 snor_write_en(); 245 op.sfcmd.d32 = 0; 246 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 247 op.sfcmd.b.rw = SFC_WRITE; 248 249 op.sfctrl.d32 = 0; 250 251 ret = sfc_request(&op, 0, &status, 1); 252 if (ret != SFC_OK) 253 return ret; 254 255 ret = snor_wait_busy(10000); /* 10ms */ 256 257 return ret; 258 } 259 260 int snor_erase(struct SFNOR_DEV *p_dev, 261 u32 addr, 262 enum NOR_ERASE_TYPE erase_type) 263 { 264 int ret; 265 struct rk_sfc_op op; 266 int timeout[] = {400, 2000, 40000}; /* ms */ 267 268 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 269 270 if (erase_type > ERASE_CHIP) 271 return SFC_PARAM_ERR; 272 273 op.sfcmd.d32 = 0; 274 if (erase_type == ERASE_BLOCK64K) 275 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 276 else if (erase_type == ERASE_SECTOR) 277 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 278 else 279 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 280 281 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 282 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 283 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 284 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 285 286 op.sfctrl.d32 = 0; 287 288 snor_write_en(); 289 290 ret = sfc_request(&op, addr, NULL, 0); 291 if (ret != SFC_OK) 292 return ret; 293 294 ret = snor_wait_busy(timeout[erase_type] * 1000); 295 return ret; 296 } 297 298 int snor_prog_page(struct SFNOR_DEV *p_dev, 299 u32 addr, 300 void *p_data, 301 u32 size) 302 { 303 int ret; 304 struct rk_sfc_op op; 305 306 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 307 308 op.sfcmd.d32 = 0; 309 op.sfcmd.b.cmd = p_dev->prog_cmd; 310 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 311 op.sfcmd.b.rw = SFC_WRITE; 312 313 op.sfctrl.d32 = 0; 314 op.sfctrl.b.datalines = p_dev->prog_lines; 315 op.sfctrl.b.enbledma = 1; 316 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 317 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 318 319 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 320 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 321 322 snor_write_en(); 323 324 ret = sfc_request(&op, addr, p_data, size); 325 if (ret != SFC_OK) 326 return ret; 327 328 ret = snor_wait_busy(10000); 329 330 return ret; 331 } 332 333 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 334 { 335 int ret = SFC_OK; 336 u32 page_size, len; 337 u8 *p_buf = (u8 *)p_data; 338 339 page_size = NOR_PAGE_SIZE; 340 while (size) { 341 len = page_size < size ? page_size : size; 342 ret = snor_prog_page(p_dev, addr, p_buf, len); 343 if (ret != SFC_OK) 344 return ret; 345 346 size -= len; 347 addr += len; 348 p_buf += len; 349 } 350 351 return ret; 352 } 353 354 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 355 { 356 int ret = SFC_OK; 357 int reg_index; 358 int bit_offset; 359 u8 status; 360 361 reg_index = p_dev->QE_bits >> 3; 362 bit_offset = p_dev->QE_bits & 0x7; 363 ret = snor_read_status(reg_index, &status); 364 if (ret != SFC_OK) 365 return ret; 366 367 if (status & (1 << bit_offset)) /* is QE bit set */ 368 return SFC_OK; 369 370 status |= (1 << bit_offset); 371 372 return p_dev->write_status(reg_index, status); 373 } 374 375 int snor_disable_QE(struct SFNOR_DEV *p_dev) 376 { 377 int ret = SFC_OK; 378 int reg_index; 379 int bit_offset; 380 u8 status; 381 382 reg_index = p_dev->QE_bits >> 3; 383 bit_offset = p_dev->QE_bits & 0x7; 384 ret = snor_read_status(reg_index, &status); 385 if (ret != SFC_OK) 386 return ret; 387 388 if (!(status & (1 << bit_offset))) 389 return SFC_OK; 390 391 status &= ~(1 << bit_offset); 392 393 return p_dev->write_status(reg_index, status); 394 } 395 396 int snor_read_data(struct SFNOR_DEV *p_dev, 397 u32 addr, 398 void *p_data, 399 u32 size) 400 { 401 int ret; 402 struct rk_sfc_op op; 403 404 op.sfcmd.d32 = 0; 405 op.sfcmd.b.cmd = p_dev->read_cmd; 406 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 407 408 op.sfctrl.d32 = 0; 409 op.sfctrl.b.datalines = p_dev->read_lines; 410 if (!(size & 0x3) && size >= 4) 411 op.sfctrl.b.enbledma = 1; 412 413 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 414 p_dev->read_cmd == CMD_FAST_READ_X4 || 415 p_dev->read_cmd == CMD_FAST_READ_X2 || 416 p_dev->read_cmd == CMD_FAST_4READ_X4) { 417 op.sfcmd.b.dummybits = 8; 418 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 419 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 420 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 421 op.sfcmd.b.dummybits = 4; 422 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 423 } 424 425 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 426 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 427 428 ret = sfc_request(&op, addr, p_data, size); 429 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 430 431 return ret; 432 } 433 434 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 435 { 436 int ret = SFC_OK; 437 u32 addr, size, len; 438 u8 *p_buf = (u8 *)p_data; 439 440 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 441 442 if ((sec + n_sec) > p_dev->capacity) 443 return SFC_PARAM_ERR; 444 445 addr = sec << 9; 446 size = n_sec << 9; 447 while (size) { 448 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 449 ret = snor_read_data(p_dev, addr, p_buf, len); 450 if (ret != SFC_OK) { 451 rkflash_print_error("snor_read_data %x ret= %x\n", 452 addr >> 9, ret); 453 goto out; 454 } 455 456 size -= len; 457 addr += len; 458 p_buf += len; 459 } 460 out: 461 if (!ret) 462 ret = n_sec; 463 464 return ret; 465 } 466 467 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 468 { 469 int ret = SFC_OK; 470 u32 len, blk_size, offset; 471 u8 *p_buf = (u8 *)p_data; 472 u32 total_sec = n_sec; 473 474 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 475 476 if ((sec + n_sec) > p_dev->capacity) 477 return SFC_PARAM_ERR; 478 479 while (n_sec) { 480 if (sec < 512 || sec >= p_dev->capacity - 512) 481 blk_size = 8; 482 else 483 blk_size = p_dev->blk_size; 484 485 offset = (sec & (blk_size - 1)); 486 if (!offset) { 487 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 488 ERASE_SECTOR : ERASE_BLOCK64K); 489 if (ret != SFC_OK) { 490 rkflash_print_error("snor_erase %x ret= %x\n", 491 sec, ret); 492 goto out; 493 } 494 } 495 len = (blk_size - offset) < n_sec ? 496 (blk_size - offset) : n_sec; 497 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 498 if (ret != SFC_OK) { 499 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 500 goto out; 501 } 502 n_sec -= len; 503 sec += len; 504 p_buf += len << 9; 505 } 506 out: 507 if (!ret) 508 ret = total_sec; 509 510 return ret; 511 } 512 513 int snor_read_id(u8 *data) 514 { 515 int ret; 516 struct rk_sfc_op op; 517 518 op.sfcmd.d32 = 0; 519 op.sfcmd.b.cmd = CMD_READ_JEDECID; 520 521 op.sfctrl.d32 = 0; 522 523 ret = sfc_request(&op, 0, data, 3); 524 525 return ret; 526 } 527 528 static int snor_read_parameter(u32 addr, u8 *data) 529 { 530 int ret; 531 struct rk_sfc_op op; 532 533 op.sfcmd.d32 = 0; 534 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 535 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 536 op.sfcmd.b.dummybits = 8; 537 538 op.sfctrl.d32 = 0; 539 540 ret = sfc_request(&op, addr, data, 1); 541 542 return ret; 543 } 544 545 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 546 { 547 return p_dev->capacity; 548 } 549 550 static struct flash_info *snor_get_flash_info(u8 *flash_id) 551 { 552 u32 i; 553 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 554 555 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 556 if (spi_flash_tbl[i].id == id) 557 return &spi_flash_tbl[i]; 558 } 559 return NULL; 560 } 561 562 /* Adjust flash info in ram base on parameter */ 563 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 564 { 565 u32 addr; 566 u8 para_version; 567 568 if (spi_flash_info->id == 0xc84019) { 569 addr = 0x09; 570 snor_read_parameter(addr, ¶_version); 571 if (para_version == 0x06) { 572 spi_flash_info->QE_bits = 9; 573 spi_flash_info->prog_cmd_4 = 0x34; 574 } 575 } 576 return 0; 577 } 578 579 int snor_init(struct SFNOR_DEV *p_dev) 580 { 581 struct flash_info *g_spi_flash_info; 582 u32 i, ret; 583 u8 id_byte[5]; 584 585 if (!p_dev) 586 return SFC_PARAM_ERR; 587 588 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 589 p_dev->max_iosize = sfc_get_max_iosize(); 590 snor_read_id(id_byte); 591 rkflash_print_error("sfc nor id: %x %x %x\n", 592 id_byte[0], id_byte[1], id_byte[2]); 593 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 594 return SFC_ERROR; 595 596 p_dev->manufacturer = id_byte[0]; 597 p_dev->mem_type = id_byte[1]; 598 599 g_spi_flash_info = snor_get_flash_info(id_byte); 600 if (g_spi_flash_info) { 601 snor_flash_info_adjust(g_spi_flash_info); 602 p_dev->capacity = 1 << g_spi_flash_info->density; 603 p_dev->blk_size = g_spi_flash_info->block_size; 604 p_dev->page_size = NOR_SECS_PAGE; 605 p_dev->read_cmd = g_spi_flash_info->read_cmd; 606 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 607 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 608 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 609 p_dev->prog_lines = DATA_LINES_X1; 610 p_dev->read_lines = DATA_LINES_X1; 611 p_dev->QE_bits = g_spi_flash_info->QE_bits; 612 p_dev->addr_mode = ADDR_MODE_3BYTE; 613 614 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 615 if (i == 0) 616 p_dev->write_status = snor_write_status; 617 else if (i == 1) 618 p_dev->write_status = snor_write_status1; 619 else if (i == 2) 620 p_dev->write_status = snor_write_status2; 621 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 622 ret = SFC_OK; 623 if (g_spi_flash_info->QE_bits) 624 ret = snor_enable_QE(p_dev); 625 if (ret == SFC_OK) { 626 p_dev->read_lines = DATA_LINES_X4; 627 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 628 } 629 } 630 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 631 p_dev->read_lines == DATA_LINES_X4) { 632 p_dev->prog_lines = DATA_LINES_X4; 633 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 634 } 635 636 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 637 p_dev->addr_mode = ADDR_MODE_4BYTE; 638 639 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 640 snor_enter_4byte_mode(); 641 } else { 642 p_dev->capacity = 1 << (id_byte[2] - 9); 643 p_dev->QE_bits = 0; 644 p_dev->blk_size = NOR_SECS_BLK; 645 p_dev->page_size = NOR_SECS_PAGE; 646 p_dev->read_cmd = CMD_READ_DATA; 647 p_dev->prog_cmd = CMD_PAGE_PROG; 648 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 649 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 650 p_dev->prog_lines = DATA_LINES_X1; 651 p_dev->read_lines = DATA_LINES_X1; 652 p_dev->write_status = snor_write_status; 653 } 654 655 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 656 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 657 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 658 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 659 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 660 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 661 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 662 663 return SFC_OK; 664 } 665 666