1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B/C/E */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C/E */ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D/E */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 25 /* GD25LQ64C */ 26 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 27 /* GD25LQ32E */ 28 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 29 /* GD25B512MEYIG */ 30 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 31 /* GD25LQ255E and GD25LQ256C */ 32 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 }, 33 /* GD25LB512MEYIG */ 34 { 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 35 36 /* W25Q32JV */ 37 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 38 /* W25Q64JVSSIQ */ 39 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 40 /* W25Q128FV and W25Q128JV*/ 41 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 42 /* W25Q256F/J */ 43 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 44 /* W25Q32JW */ 45 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 46 /* W25Q64FWSSIG */ 47 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 48 /* W25Q128JWSQ */ 49 { 0xef6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 50 /* W25Q256JWEQ*/ 51 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 52 /* W25Q128JVSIM */ 53 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 54 /* W25Q256JVEM */ 55 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 56 57 /* MX25L3233FM2I-08G */ 58 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 59 /* MX25L6433F */ 60 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 61 /* MX25L12835E/F MX25L12833FMI-10G */ 62 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 63 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */ 64 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 65 /* MX25L51245GMI */ 66 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 67 /* MX25U51245G */ 68 { 0xc2253a, 128, 8, 0x0C, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 69 /* MX25U3232F */ 70 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 71 /* MX25U6432F */ 72 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 73 /* MX25U12832F */ 74 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 75 /* MX25U25645GZ4I-00 */ 76 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 77 78 /* XM25QH32C */ 79 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 80 /* XM25QH64C */ 81 { 0x204017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 82 /* XM25QH128C */ 83 { 0x204018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 15, 9, 0 }, 84 /* XM25QH256C */ 85 { 0x204019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 86 /* XM25QH64B */ 87 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 88 /* XM25QH128B */ 89 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 90 /* XM25QH(QU)256B */ 91 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 92 /* XM25QH64A */ 93 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 94 /* XM25QU128C */ 95 { 0x204118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 96 /* XM25QU64C */ 97 { 0x204117, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 98 99 /* XT25F128A XM25QH128A */ 100 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 101 /* XT25F64BSSIGU-5 XT25F64F */ 102 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 103 /* XT25F128BSSIGU */ 104 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 105 /* XT25F256BSFIGU */ 106 { 0x0b4019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 107 /* XT25F32BS */ 108 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 109 /* XT25F16BS */ 110 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 111 112 /* EN25QH64A */ 113 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 114 /* EN25QH128A */ 115 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 116 /* EN25QH32B */ 117 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 118 /* EN25S32A */ 119 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 120 /* EN25S64A */ 121 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 122 /* EN25QH256A */ 123 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 124 125 /* P25Q64H */ 126 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 127 /* P25Q128H */ 128 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 129 /* P25Q16H-SUH-IT */ 130 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 131 /* P25Q32SL P25Q32SH-SSH-IT */ 132 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 133 /* PY25Q128H */ 134 { 0x852018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 135 136 /* ZB25VQ64 */ 137 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 138 /* ZB25VQ128 */ 139 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 140 /* ZB25LQ128 */ 141 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 142 143 /* BH25Q128AS */ 144 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 145 /* BH25Q64BS */ 146 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 147 148 /* FM25Q128A */ 149 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 150 /* FM25Q64-SOB-T-G */ 151 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 152 153 /* FM25Q64A */ 154 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 155 /* FM25M4AA */ 156 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 157 /* FM25M64C */ 158 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 159 160 /* DS25M4AB-1AIB4 */ 161 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 162 163 /* GM25Q128A */ 164 { 0x1c4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 165 166 /* IS25LP512M */ 167 { 0x9D601A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 168 /* IS25WP512M */ 169 { 0x9D701A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 170 }; 171 172 static int snor_write_en(void) 173 { 174 int ret; 175 struct rk_sfc_op op; 176 177 op.sfcmd.d32 = 0; 178 op.sfcmd.b.cmd = CMD_WRITE_EN; 179 180 op.sfctrl.d32 = 0; 181 182 ret = sfc_request(&op, 0, NULL, 0); 183 184 return ret; 185 } 186 187 int snor_reset_device(void) 188 { 189 struct rk_sfc_op op; 190 191 op.sfcmd.d32 = 0; 192 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 193 194 op.sfctrl.d32 = 0; 195 sfc_request(&op, 0, NULL, 0); 196 197 op.sfcmd.d32 = 0; 198 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 199 200 op.sfctrl.d32 = 0; 201 sfc_request(&op, 0, NULL, 0); 202 /* tRST=30us , delay 1ms here */ 203 sfc_delay(1000); 204 205 return SFC_OK; 206 } 207 208 static int snor_enter_4byte_mode(void) 209 { 210 int ret; 211 struct rk_sfc_op op; 212 213 op.sfcmd.d32 = 0; 214 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 215 216 op.sfctrl.d32 = 0; 217 218 ret = sfc_request(&op, 0, NULL, 0); 219 return ret; 220 } 221 222 static int snor_read_status(u32 reg_index, u8 *status) 223 { 224 int ret; 225 struct rk_sfc_op op; 226 u8 read_stat_cmd[] = {CMD_READ_STATUS, 227 CMD_READ_STATUS2, CMD_READ_STATUS3}; 228 op.sfcmd.d32 = 0; 229 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 230 231 op.sfctrl.d32 = 0; 232 ret = sfc_request(&op, 0, status, 1); 233 234 return ret; 235 } 236 237 static int snor_wait_busy(int timeout) 238 { 239 int ret; 240 struct rk_sfc_op op; 241 int i; 242 u32 status; 243 244 op.sfcmd.d32 = 0; 245 op.sfcmd.b.cmd = CMD_READ_STATUS; 246 247 op.sfctrl.d32 = 0; 248 249 for (i = 0; i < timeout; i++) { 250 ret = sfc_request(&op, 0, &status, 1); 251 if (ret != SFC_OK) 252 return ret; 253 254 if ((status & 0x01) == 0) 255 return SFC_OK; 256 257 sfc_delay(1); 258 } 259 rkflash_print_error("%s error %x\n", __func__, timeout); 260 261 return SFC_BUSY_TIMEOUT; 262 } 263 264 static int snor_write_status2(u32 reg_index, u8 status) 265 { 266 int ret; 267 struct rk_sfc_op op; 268 u8 status2[2]; 269 270 status2[reg_index] = status; 271 if (reg_index == 0) 272 ret = snor_read_status(2, &status2[1]); 273 else 274 ret = snor_read_status(0, &status2[0]); 275 if (ret != SFC_OK) 276 return ret; 277 278 snor_write_en(); 279 280 op.sfcmd.d32 = 0; 281 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 282 op.sfcmd.b.rw = SFC_WRITE; 283 284 op.sfctrl.d32 = 0; 285 286 ret = sfc_request(&op, 0, &status2[0], 2); 287 if (ret != SFC_OK) 288 return ret; 289 290 ret = snor_wait_busy(10000); /* 10ms */ 291 292 return ret; 293 } 294 295 static int snor_write_status1(u32 reg_index, u8 status) 296 { 297 int ret; 298 struct rk_sfc_op op; 299 u8 status2[2]; 300 u8 read_index; 301 302 status2[reg_index] = status; 303 read_index = (reg_index == 0) ? 1 : 0; 304 ret = snor_read_status(read_index, &status2[read_index]); 305 if (ret != SFC_OK) 306 return ret; 307 308 snor_write_en(); 309 310 op.sfcmd.d32 = 0; 311 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 312 op.sfcmd.b.rw = SFC_WRITE; 313 314 op.sfctrl.d32 = 0; 315 316 ret = sfc_request(&op, 0, &status2[0], 2); 317 if (ret != SFC_OK) 318 return ret; 319 320 ret = snor_wait_busy(10000); /* 10ms */ 321 322 return ret; 323 } 324 325 static int snor_write_status(u32 reg_index, u8 status) 326 { 327 int ret; 328 struct rk_sfc_op op; 329 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 330 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 331 snor_write_en(); 332 op.sfcmd.d32 = 0; 333 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 334 op.sfcmd.b.rw = SFC_WRITE; 335 336 op.sfctrl.d32 = 0; 337 338 ret = sfc_request(&op, 0, &status, 1); 339 if (ret != SFC_OK) 340 return ret; 341 342 ret = snor_wait_busy(10000); /* 10ms */ 343 344 return ret; 345 } 346 347 int snor_erase(struct SFNOR_DEV *p_dev, 348 u32 addr, 349 enum NOR_ERASE_TYPE erase_type) 350 { 351 int ret; 352 struct rk_sfc_op op; 353 int timeout[] = {400, 2000, 40000}; /* ms */ 354 355 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 356 357 if (erase_type > ERASE_CHIP) 358 return SFC_PARAM_ERR; 359 360 op.sfcmd.d32 = 0; 361 if (erase_type == ERASE_BLOCK64K) 362 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 363 else if (erase_type == ERASE_SECTOR) 364 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 365 else 366 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 367 368 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 369 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 370 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 371 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 372 373 op.sfctrl.d32 = 0; 374 375 snor_write_en(); 376 377 ret = sfc_request(&op, addr, NULL, 0); 378 if (ret != SFC_OK) 379 return ret; 380 381 ret = snor_wait_busy(timeout[erase_type] * 1000); 382 return ret; 383 } 384 385 int snor_prog_page(struct SFNOR_DEV *p_dev, 386 u32 addr, 387 void *p_data, 388 u32 size) 389 { 390 int ret; 391 struct rk_sfc_op op; 392 393 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 394 395 op.sfcmd.d32 = 0; 396 op.sfcmd.b.cmd = p_dev->prog_cmd; 397 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 398 op.sfcmd.b.rw = SFC_WRITE; 399 400 op.sfctrl.d32 = 0; 401 op.sfctrl.b.datalines = p_dev->prog_lines; 402 op.sfctrl.b.enbledma = 1; 403 op.sfctrl.b.addrlines = p_dev->prog_addr_lines; 404 405 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 406 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 407 408 snor_write_en(); 409 410 ret = sfc_request(&op, addr, p_data, size); 411 if (ret != SFC_OK) 412 return ret; 413 414 ret = snor_wait_busy(10000); 415 416 return ret; 417 } 418 419 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 420 { 421 int ret = SFC_OK; 422 u32 page_size, len; 423 u8 *p_buf = (u8 *)p_data; 424 425 page_size = NOR_PAGE_SIZE; 426 while (size) { 427 len = page_size < size ? page_size : size; 428 ret = snor_prog_page(p_dev, addr, p_buf, len); 429 if (ret != SFC_OK) 430 return ret; 431 432 size -= len; 433 addr += len; 434 p_buf += len; 435 } 436 437 return ret; 438 } 439 440 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 441 { 442 int ret = SFC_OK; 443 int reg_index; 444 int bit_offset; 445 u8 status; 446 447 reg_index = p_dev->QE_bits >> 3; 448 bit_offset = p_dev->QE_bits & 0x7; 449 ret = snor_read_status(reg_index, &status); 450 if (ret != SFC_OK) 451 return ret; 452 453 if (status & (1 << bit_offset)) /* is QE bit set */ 454 return SFC_OK; 455 456 status |= (1 << bit_offset); 457 458 return p_dev->write_status(reg_index, status); 459 } 460 461 int snor_disable_QE(struct SFNOR_DEV *p_dev) 462 { 463 int ret = SFC_OK; 464 int reg_index; 465 int bit_offset; 466 u8 status; 467 468 reg_index = p_dev->QE_bits >> 3; 469 bit_offset = p_dev->QE_bits & 0x7; 470 ret = snor_read_status(reg_index, &status); 471 if (ret != SFC_OK) 472 return ret; 473 474 if (!(status & (1 << bit_offset))) 475 return SFC_OK; 476 477 status &= ~(1 << bit_offset); 478 479 return p_dev->write_status(reg_index, status); 480 } 481 482 int snor_read_data(struct SFNOR_DEV *p_dev, 483 u32 addr, 484 void *p_data, 485 u32 size) 486 { 487 int ret; 488 struct rk_sfc_op op; 489 490 op.sfcmd.d32 = 0; 491 op.sfcmd.b.cmd = p_dev->read_cmd; 492 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 493 494 op.sfctrl.d32 = 0; 495 op.sfctrl.b.datalines = p_dev->read_lines; 496 if (!(size & 0x3) && size >= 4) 497 op.sfctrl.b.enbledma = 1; 498 499 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 500 p_dev->read_cmd == CMD_PAGE_FASTREAD4B || 501 p_dev->read_cmd == CMD_FAST_READ_X4 || 502 p_dev->read_cmd == CMD_FAST_READ_X2 || 503 p_dev->read_cmd == CMD_FAST_4READ_X4) { 504 op.sfcmd.b.dummybits = 8; 505 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 506 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 507 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 508 op.sfcmd.b.dummybits = 4; 509 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 510 } 511 512 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 513 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 514 515 ret = sfc_request(&op, addr, p_data, size); 516 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 517 518 return ret; 519 } 520 521 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 522 { 523 int ret = SFC_OK; 524 u32 addr, size, len; 525 u8 *p_buf = (u8 *)p_data; 526 527 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 528 529 if ((sec + n_sec) > p_dev->capacity) 530 return SFC_PARAM_ERR; 531 532 addr = sec << 9; 533 size = n_sec << 9; 534 while (size) { 535 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 536 ret = snor_read_data(p_dev, addr, p_buf, len); 537 if (ret != SFC_OK) { 538 rkflash_print_error("snor_read_data %x ret= %x\n", 539 addr >> 9, ret); 540 goto out; 541 } 542 543 size -= len; 544 addr += len; 545 p_buf += len; 546 } 547 out: 548 if (!ret) 549 ret = n_sec; 550 551 return ret; 552 } 553 554 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 555 { 556 int ret = SFC_OK; 557 u32 len, blk_size, offset; 558 u8 *p_buf = (u8 *)p_data; 559 u32 total_sec = n_sec; 560 561 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 562 563 if ((sec + n_sec) > p_dev->capacity) 564 return SFC_PARAM_ERR; 565 566 while (n_sec) { 567 if (sec < 512 || sec >= p_dev->capacity - 512) 568 blk_size = 8; 569 else 570 blk_size = p_dev->blk_size; 571 572 offset = (sec & (blk_size - 1)); 573 if (!offset) { 574 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 575 ERASE_SECTOR : ERASE_BLOCK64K); 576 if (ret != SFC_OK) { 577 rkflash_print_error("snor_erase %x ret= %x\n", 578 sec, ret); 579 goto out; 580 } 581 } 582 len = (blk_size - offset) < n_sec ? 583 (blk_size - offset) : n_sec; 584 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 585 if (ret != SFC_OK) { 586 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 587 goto out; 588 } 589 n_sec -= len; 590 sec += len; 591 p_buf += len << 9; 592 } 593 out: 594 if (!ret) 595 ret = total_sec; 596 597 return ret; 598 } 599 600 int snor_read_id(u8 *data) 601 { 602 int ret; 603 struct rk_sfc_op op; 604 605 op.sfcmd.d32 = 0; 606 op.sfcmd.b.cmd = CMD_READ_JEDECID; 607 608 op.sfctrl.d32 = 0; 609 610 ret = sfc_request(&op, 0, data, 3); 611 612 return ret; 613 } 614 615 static int snor_read_parameter(u32 addr, u8 *data) 616 { 617 int ret; 618 struct rk_sfc_op op; 619 620 op.sfcmd.d32 = 0; 621 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 622 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 623 op.sfcmd.b.dummybits = 8; 624 625 op.sfctrl.d32 = 0; 626 627 ret = sfc_request(&op, addr, data, 1); 628 629 return ret; 630 } 631 632 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 633 { 634 return p_dev->capacity; 635 } 636 637 static struct flash_info *snor_get_flash_info(u8 *flash_id) 638 { 639 u32 i; 640 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 641 642 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 643 if (spi_flash_tbl[i].id == id) 644 return &spi_flash_tbl[i]; 645 } 646 return NULL; 647 } 648 649 /* Adjust flash info in ram base on parameter */ 650 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 651 { 652 u32 addr; 653 u8 para_version; 654 655 if (spi_flash_info->id == 0xc84019) { 656 addr = 0x09; 657 snor_read_parameter(addr, ¶_version); 658 if (para_version == 0x06) { 659 spi_flash_info->QE_bits = 9; 660 spi_flash_info->prog_cmd_4 = 0x34; 661 } 662 } 663 return 0; 664 } 665 666 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 667 struct flash_info *g_spi_flash_info) 668 { 669 int i, ret; 670 671 if (g_spi_flash_info) { 672 snor_flash_info_adjust(g_spi_flash_info); 673 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 674 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 675 p_dev->capacity = 1 << g_spi_flash_info->density; 676 p_dev->blk_size = g_spi_flash_info->block_size; 677 p_dev->page_size = NOR_SECS_PAGE; 678 p_dev->read_cmd = g_spi_flash_info->read_cmd; 679 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 680 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 681 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 682 p_dev->prog_lines = DATA_LINES_X1; 683 p_dev->read_lines = DATA_LINES_X1; 684 p_dev->QE_bits = g_spi_flash_info->QE_bits; 685 p_dev->addr_mode = ADDR_MODE_3BYTE; 686 687 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 688 if (i == 0) 689 p_dev->write_status = snor_write_status; 690 else if (i == 1) 691 p_dev->write_status = snor_write_status1; 692 else if (i == 2) 693 p_dev->write_status = snor_write_status2; 694 695 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 696 ret = SFC_OK; 697 if (g_spi_flash_info->QE_bits) 698 ret = snor_enable_QE(p_dev); 699 if (ret == SFC_OK) { 700 p_dev->read_lines = DATA_LINES_X4; 701 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 702 } 703 } 704 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 705 p_dev->read_lines == DATA_LINES_X4) { 706 p_dev->prog_lines = DATA_LINES_X4; 707 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 708 if ((p_dev->manufacturer == MID_MACRONIX) && 709 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 || 710 p_dev->prog_cmd == CMD_PAGE_PROG_4PP)) 711 p_dev->prog_addr_lines = DATA_LINES_X4; 712 } 713 714 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 715 p_dev->addr_mode = ADDR_MODE_4BYTE; 716 717 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 718 snor_enter_4byte_mode(); 719 } 720 721 return SFC_OK; 722 } 723 724 int snor_init(struct SFNOR_DEV *p_dev) 725 { 726 struct flash_info *g_spi_flash_info; 727 u8 id_byte[5]; 728 729 if (!p_dev) 730 return SFC_PARAM_ERR; 731 732 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 733 p_dev->max_iosize = sfc_get_max_iosize(); 734 735 snor_read_id(id_byte); 736 rkflash_print_error("sfc nor id: %x %x %x\n", 737 id_byte[0], id_byte[1], id_byte[2]); 738 if (0xFF == id_byte[0] || 0x00 == id_byte[0] || 0xFF == id_byte[1] || 0x00 == id_byte[1]) 739 return SFC_ERROR; 740 741 g_spi_flash_info = snor_get_flash_info(id_byte); 742 if (g_spi_flash_info) { 743 snor_parse_flash_table(p_dev, g_spi_flash_info); 744 } else { 745 pr_err("The device not support yet!\n"); 746 747 p_dev->manufacturer = id_byte[0]; 748 p_dev->mem_type = id_byte[1]; 749 p_dev->capacity = 1 << (id_byte[2] - 9); 750 p_dev->QE_bits = 0; 751 p_dev->blk_size = NOR_SECS_BLK; 752 p_dev->page_size = NOR_SECS_PAGE; 753 p_dev->read_cmd = CMD_READ_DATA; 754 p_dev->prog_cmd = CMD_PAGE_PROG; 755 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 756 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 757 p_dev->prog_lines = DATA_LINES_X1; 758 p_dev->prog_addr_lines = DATA_LINES_X1; 759 p_dev->read_lines = DATA_LINES_X1; 760 p_dev->write_status = snor_write_status; 761 snor_reset_device(); 762 } 763 764 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 765 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 766 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 767 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 768 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 769 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 770 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 771 rkflash_print_info("capacity: %x\n", p_dev->capacity); 772 773 return SFC_OK; 774 } 775 776 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 777 struct snor_info_packet *packet) 778 { 779 struct flash_info g_spi_flash_info; 780 u8 id_byte[5]; 781 int ret; 782 783 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 784 return SFC_PARAM_ERR; 785 786 snor_read_id(id_byte); 787 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 788 return SFC_ERROR; 789 790 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 791 g_spi_flash_info.block_size = NOR_SECS_BLK; 792 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 793 g_spi_flash_info.read_cmd = packet->read_cmd; 794 g_spi_flash_info.prog_cmd = packet->prog_cmd; 795 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 796 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 797 if (id_byte[2] >= 0x19) 798 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 799 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 800 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 801 g_spi_flash_info.feature = packet->feature; 802 g_spi_flash_info.density = id_byte[2] - 9; 803 g_spi_flash_info.QE_bits = packet->QE_bits; 804 805 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 806 807 return ret; 808 } 809 810