1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q40B */ 16 { 0xc84013, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 10, 9, 0 }, 17 /* GD25Q32B */ 18 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 19 /* GD25Q64B/C/E */ 20 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 21 /* GD25Q127C and GD25Q128C/E */ 22 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 23 /* GD25Q256B/C/D/E */ 24 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 25 /* GD25Q512MC */ 26 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 27 /* GD25LQ64C */ 28 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 29 /* GD25LQ128 */ 30 { 0xc86018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 31 /* GD25LQ32E */ 32 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 33 /* GD25B512MEYIG */ 34 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 35 /* GD25LQ255E and GD25LQ256C */ 36 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 }, 37 /* GD25LB512MEYIG */ 38 { 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 39 40 /* W25Q32JV */ 41 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 42 /* W25Q64JVSSIQ */ 43 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 44 /* W25Q128FV and W25Q128JV*/ 45 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 46 /* W25Q256F/J */ 47 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 48 /* W25Q32JW */ 49 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 50 /* W25Q64FWSSIG */ 51 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 52 /* W25Q128JWSQ */ 53 { 0xef6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 54 /* W25Q256JWEQ*/ 55 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 56 /* W25Q128JVSIM */ 57 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 58 /* W25Q256JVEM */ 59 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 60 61 /* MX25L3233FM2I-08G */ 62 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 63 /* MX25L6433F */ 64 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 65 /* MX25L12835E/F MX25L12833FMI-10G */ 66 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 67 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */ 68 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 69 /* MX25L51245GMI */ 70 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 71 /* MX25U51245G */ 72 { 0xc2253a, 128, 8, 0x0C, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 73 /* MX25U3232F */ 74 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 75 /* MX25U6432F */ 76 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 77 /* MX25U12832F */ 78 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 79 /* MX25U25645GZ4I-00 */ 80 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 81 82 /* XM25QH32C */ 83 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 84 /* XM25QH64C */ 85 { 0x204017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 86 /* XM25QH128C */ 87 { 0x204018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x05, 15, 9, 0 }, 88 /* XM25QH256C */ 89 { 0x204019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 90 /* XM25QH64B */ 91 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 92 /* XM25QH128B */ 93 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 94 /* XM25QH(QU)256B */ 95 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 96 /* XM25QH64A */ 97 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 98 /* XM25QU128C */ 99 { 0x204118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 100 /* XM25QU64C */ 101 { 0x204117, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 102 103 /* XT25F128A XM25QH128A */ 104 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 105 /* XT25F64BSSIGU-5 XT25F64F */ 106 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 107 /* XT25F128BSSIGU */ 108 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 109 /* XT25F256BSFIGU */ 110 { 0x0b4019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 111 /* XT25F32BS XT25F32F */ 112 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 113 /* XT25F16BS */ 114 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 115 116 /* EN25QH64A */ 117 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 118 /* EN25QH128A */ 119 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 120 /* EN25QH32B */ 121 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 122 /* EN25S32A */ 123 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 124 /* EN25S64A */ 125 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 126 /* EN25QH256A */ 127 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 128 129 /* P25Q64H */ 130 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 131 /* P25Q128H */ 132 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 133 /* P25Q16H-SUH-IT */ 134 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 135 /* P25Q32SL P25Q32SH-SSH-IT */ 136 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 137 /* PY25Q128H */ 138 { 0x852018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 139 140 /* ZB25VQ64 */ 141 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 142 /* ZB25VQ128 */ 143 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 144 /* ZB25LQ128 */ 145 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 146 147 /* BH25Q128AS */ 148 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 149 /* BH25Q64BS */ 150 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 151 152 /* FM25Q128A */ 153 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 154 /* FM25Q64-SOB-T-G */ 155 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 156 157 /* FM25Q64A */ 158 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 159 /* FM25M4AA */ 160 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 161 /* FM25M64C */ 162 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 163 164 /* DS25M4AB-1AIB4 */ 165 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 166 167 /* GM25Q128A */ 168 { 0x1c4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 169 170 /* IS25LP512M */ 171 { 0x9D601A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 172 /* IS25WP512M */ 173 { 0x9D701A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 174 175 /* BY25Q256FSEIG */ 176 { 0x684919, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 177 }; 178 179 static int snor_write_en(void) 180 { 181 int ret; 182 struct rk_sfc_op op; 183 184 op.sfcmd.d32 = 0; 185 op.sfcmd.b.cmd = CMD_WRITE_EN; 186 187 op.sfctrl.d32 = 0; 188 189 ret = sfc_request(&op, 0, NULL, 0); 190 191 return ret; 192 } 193 194 int snor_reset_device(void) 195 { 196 struct rk_sfc_op op; 197 198 op.sfcmd.d32 = 0; 199 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 200 201 op.sfctrl.d32 = 0; 202 sfc_request(&op, 0, NULL, 0); 203 204 op.sfcmd.d32 = 0; 205 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 206 207 op.sfctrl.d32 = 0; 208 sfc_request(&op, 0, NULL, 0); 209 /* tRST=30us , delay 1ms here */ 210 sfc_delay(1000); 211 212 return SFC_OK; 213 } 214 215 static int snor_enter_4byte_mode(void) 216 { 217 int ret; 218 struct rk_sfc_op op; 219 220 op.sfcmd.d32 = 0; 221 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 222 223 op.sfctrl.d32 = 0; 224 225 ret = sfc_request(&op, 0, NULL, 0); 226 return ret; 227 } 228 229 static int snor_read_status(u32 reg_index, u8 *status) 230 { 231 int ret; 232 struct rk_sfc_op op; 233 u8 read_stat_cmd[] = {CMD_READ_STATUS, 234 CMD_READ_STATUS2, CMD_READ_STATUS3}; 235 op.sfcmd.d32 = 0; 236 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 237 238 op.sfctrl.d32 = 0; 239 ret = sfc_request(&op, 0, status, 1); 240 241 return ret; 242 } 243 244 static int snor_wait_busy(int timeout) 245 { 246 int ret; 247 struct rk_sfc_op op; 248 int i; 249 u32 status; 250 251 op.sfcmd.d32 = 0; 252 op.sfcmd.b.cmd = CMD_READ_STATUS; 253 254 op.sfctrl.d32 = 0; 255 256 for (i = 0; i < timeout; i++) { 257 ret = sfc_request(&op, 0, &status, 1); 258 if (ret != SFC_OK) 259 return ret; 260 261 if ((status & 0x01) == 0) 262 return SFC_OK; 263 264 sfc_delay(1); 265 } 266 rkflash_print_error("%s error %x\n", __func__, timeout); 267 268 return SFC_BUSY_TIMEOUT; 269 } 270 271 static int snor_write_status2(u32 reg_index, u8 status) 272 { 273 int ret; 274 struct rk_sfc_op op; 275 u8 status2[2]; 276 277 status2[reg_index] = status; 278 if (reg_index == 0) 279 ret = snor_read_status(2, &status2[1]); 280 else 281 ret = snor_read_status(0, &status2[0]); 282 if (ret != SFC_OK) 283 return ret; 284 285 snor_write_en(); 286 287 op.sfcmd.d32 = 0; 288 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 289 op.sfcmd.b.rw = SFC_WRITE; 290 291 op.sfctrl.d32 = 0; 292 293 ret = sfc_request(&op, 0, &status2[0], 2); 294 if (ret != SFC_OK) 295 return ret; 296 297 ret = snor_wait_busy(10000); /* 10ms */ 298 299 return ret; 300 } 301 302 static int snor_write_status1(u32 reg_index, u8 status) 303 { 304 int ret; 305 struct rk_sfc_op op; 306 u8 status2[2]; 307 u8 read_index; 308 309 status2[reg_index] = status; 310 read_index = (reg_index == 0) ? 1 : 0; 311 ret = snor_read_status(read_index, &status2[read_index]); 312 if (ret != SFC_OK) 313 return ret; 314 315 snor_write_en(); 316 317 op.sfcmd.d32 = 0; 318 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 319 op.sfcmd.b.rw = SFC_WRITE; 320 321 op.sfctrl.d32 = 0; 322 323 ret = sfc_request(&op, 0, &status2[0], 2); 324 if (ret != SFC_OK) 325 return ret; 326 327 ret = snor_wait_busy(10000); /* 10ms */ 328 329 return ret; 330 } 331 332 static int snor_write_status(u32 reg_index, u8 status) 333 { 334 int ret; 335 struct rk_sfc_op op; 336 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 337 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 338 snor_write_en(); 339 op.sfcmd.d32 = 0; 340 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 341 op.sfcmd.b.rw = SFC_WRITE; 342 343 op.sfctrl.d32 = 0; 344 345 ret = sfc_request(&op, 0, &status, 1); 346 if (ret != SFC_OK) 347 return ret; 348 349 ret = snor_wait_busy(10000); /* 10ms */ 350 351 return ret; 352 } 353 354 int snor_erase(struct SFNOR_DEV *p_dev, 355 u32 addr, 356 enum NOR_ERASE_TYPE erase_type) 357 { 358 int ret; 359 struct rk_sfc_op op; 360 int timeout[] = {400, 2000, 40000}; /* ms */ 361 362 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 363 364 if (erase_type > ERASE_CHIP) 365 return SFC_PARAM_ERR; 366 367 op.sfcmd.d32 = 0; 368 if (erase_type == ERASE_BLOCK64K) 369 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 370 else if (erase_type == ERASE_SECTOR) 371 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 372 else 373 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 374 375 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 376 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 377 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 378 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 379 op.sfcmd.b.rw = SFC_WRITE; 380 381 op.sfctrl.d32 = 0; 382 383 snor_write_en(); 384 385 ret = sfc_request(&op, addr, NULL, 0); 386 if (ret != SFC_OK) 387 return ret; 388 389 ret = snor_wait_busy(timeout[erase_type] * 1000); 390 return ret; 391 } 392 393 int snor_prog_page(struct SFNOR_DEV *p_dev, 394 u32 addr, 395 void *p_data, 396 u32 size) 397 { 398 int ret; 399 struct rk_sfc_op op; 400 401 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 402 403 op.sfcmd.d32 = 0; 404 op.sfcmd.b.cmd = p_dev->prog_cmd; 405 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 406 op.sfcmd.b.rw = SFC_WRITE; 407 408 op.sfctrl.d32 = 0; 409 op.sfctrl.b.datalines = p_dev->prog_lines; 410 op.sfctrl.b.enbledma = 1; 411 op.sfctrl.b.addrlines = p_dev->prog_addr_lines; 412 413 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 414 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 415 416 snor_write_en(); 417 418 ret = sfc_request(&op, addr, p_data, size); 419 if (ret != SFC_OK) 420 return ret; 421 422 ret = snor_wait_busy(10000); 423 424 return ret; 425 } 426 427 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 428 { 429 int ret = SFC_OK; 430 u32 page_size, len; 431 u8 *p_buf = (u8 *)p_data; 432 433 page_size = NOR_PAGE_SIZE; 434 while (size) { 435 len = page_size < size ? page_size : size; 436 ret = snor_prog_page(p_dev, addr, p_buf, len); 437 if (ret != SFC_OK) 438 return ret; 439 440 size -= len; 441 addr += len; 442 p_buf += len; 443 } 444 445 return ret; 446 } 447 448 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 449 { 450 int ret = SFC_OK; 451 int reg_index; 452 int bit_offset; 453 u8 status; 454 455 reg_index = p_dev->QE_bits >> 3; 456 bit_offset = p_dev->QE_bits & 0x7; 457 ret = snor_read_status(reg_index, &status); 458 if (ret != SFC_OK) 459 return ret; 460 461 if (status & (1 << bit_offset)) /* is QE bit set */ 462 return SFC_OK; 463 464 status |= (1 << bit_offset); 465 466 return p_dev->write_status(reg_index, status); 467 } 468 469 int snor_disable_QE(struct SFNOR_DEV *p_dev) 470 { 471 int ret = SFC_OK; 472 int reg_index; 473 int bit_offset; 474 u8 status; 475 476 reg_index = p_dev->QE_bits >> 3; 477 bit_offset = p_dev->QE_bits & 0x7; 478 ret = snor_read_status(reg_index, &status); 479 if (ret != SFC_OK) 480 return ret; 481 482 if (!(status & (1 << bit_offset))) 483 return SFC_OK; 484 485 status &= ~(1 << bit_offset); 486 487 return p_dev->write_status(reg_index, status); 488 } 489 490 int snor_read_data(struct SFNOR_DEV *p_dev, 491 u32 addr, 492 void *p_data, 493 u32 size) 494 { 495 int ret; 496 struct rk_sfc_op op; 497 498 op.sfcmd.d32 = 0; 499 op.sfcmd.b.cmd = p_dev->read_cmd; 500 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 501 502 op.sfctrl.d32 = 0; 503 op.sfctrl.b.datalines = p_dev->read_lines; 504 if (!(size & 0x3) && size >= 4) 505 op.sfctrl.b.enbledma = 1; 506 507 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 508 p_dev->read_cmd == CMD_PAGE_FASTREAD4B || 509 p_dev->read_cmd == CMD_FAST_READ_X4 || 510 p_dev->read_cmd == CMD_FAST_READ_X2 || 511 p_dev->read_cmd == CMD_FAST_4READ_X4) { 512 op.sfcmd.b.dummybits = 8; 513 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 514 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 515 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 516 op.sfcmd.b.dummybits = 4; 517 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 518 } 519 520 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 521 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 522 523 ret = sfc_request(&op, addr, p_data, size); 524 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 525 526 return ret; 527 } 528 529 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 530 { 531 int ret = SFC_OK; 532 u32 addr, size, len; 533 u8 *p_buf = (u8 *)p_data; 534 535 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 536 537 if ((sec + n_sec) > p_dev->capacity) 538 return SFC_PARAM_ERR; 539 540 addr = sec << 9; 541 size = n_sec << 9; 542 while (size) { 543 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 544 ret = snor_read_data(p_dev, addr, p_buf, len); 545 if (ret != SFC_OK) { 546 rkflash_print_error("snor_read_data %x ret= %x\n", 547 addr >> 9, ret); 548 goto out; 549 } 550 551 size -= len; 552 addr += len; 553 p_buf += len; 554 } 555 out: 556 if (!ret) 557 ret = n_sec; 558 559 return ret; 560 } 561 562 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 563 { 564 int ret = SFC_OK; 565 u32 len, blk_size, offset; 566 u8 *p_buf = (u8 *)p_data; 567 u32 total_sec = n_sec; 568 569 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 570 571 if ((sec + n_sec) > p_dev->capacity) 572 return SFC_PARAM_ERR; 573 574 while (n_sec) { 575 if (sec < 512 || sec >= p_dev->capacity - 512) 576 blk_size = 8; 577 else 578 blk_size = p_dev->blk_size; 579 580 offset = (sec & (blk_size - 1)); 581 if (!offset) { 582 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 583 ERASE_SECTOR : ERASE_BLOCK64K); 584 if (ret != SFC_OK) { 585 rkflash_print_error("snor_erase %x ret= %x\n", 586 sec, ret); 587 goto out; 588 } 589 } 590 len = (blk_size - offset) < n_sec ? 591 (blk_size - offset) : n_sec; 592 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 593 if (ret != SFC_OK) { 594 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 595 goto out; 596 } 597 n_sec -= len; 598 sec += len; 599 p_buf += len << 9; 600 } 601 out: 602 if (!ret) 603 ret = total_sec; 604 605 return ret; 606 } 607 608 int snor_read_id(u8 *data) 609 { 610 int ret; 611 struct rk_sfc_op op; 612 613 op.sfcmd.d32 = 0; 614 op.sfcmd.b.cmd = CMD_READ_JEDECID; 615 616 op.sfctrl.d32 = 0; 617 618 ret = sfc_request(&op, 0, data, 3); 619 620 return ret; 621 } 622 623 static int snor_read_parameter(u32 addr, u8 *data) 624 { 625 int ret; 626 struct rk_sfc_op op; 627 628 op.sfcmd.d32 = 0; 629 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 630 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 631 op.sfcmd.b.dummybits = 8; 632 633 op.sfctrl.d32 = 0; 634 635 ret = sfc_request(&op, addr, data, 1); 636 637 return ret; 638 } 639 640 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 641 { 642 return p_dev->capacity; 643 } 644 645 static struct flash_info *snor_get_flash_info(u8 *flash_id) 646 { 647 u32 i; 648 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 649 650 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 651 if (spi_flash_tbl[i].id == id) 652 return &spi_flash_tbl[i]; 653 } 654 return NULL; 655 } 656 657 /* Adjust flash info in ram base on parameter */ 658 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 659 { 660 u32 addr; 661 u8 para_version; 662 663 if (spi_flash_info->id == 0xc84019) { 664 addr = 0x09; 665 snor_read_parameter(addr, ¶_version); 666 if (para_version == 0x06) { 667 spi_flash_info->QE_bits = 9; 668 spi_flash_info->prog_cmd_4 = 0x34; 669 } 670 } 671 return 0; 672 } 673 674 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 675 struct flash_info *g_spi_flash_info) 676 { 677 int i, ret; 678 679 if (g_spi_flash_info) { 680 snor_flash_info_adjust(g_spi_flash_info); 681 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 682 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 683 p_dev->capacity = 1 << g_spi_flash_info->density; 684 p_dev->blk_size = g_spi_flash_info->block_size; 685 p_dev->page_size = NOR_SECS_PAGE; 686 p_dev->read_cmd = g_spi_flash_info->read_cmd; 687 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 688 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 689 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 690 p_dev->prog_lines = DATA_LINES_X1; 691 p_dev->read_lines = DATA_LINES_X1; 692 p_dev->QE_bits = g_spi_flash_info->QE_bits; 693 p_dev->addr_mode = ADDR_MODE_3BYTE; 694 695 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 696 if (i == 0) 697 p_dev->write_status = snor_write_status; 698 else if (i == 1) 699 p_dev->write_status = snor_write_status1; 700 else if (i == 2) 701 p_dev->write_status = snor_write_status2; 702 703 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 704 ret = SFC_OK; 705 if (g_spi_flash_info->QE_bits) 706 ret = snor_enable_QE(p_dev); 707 if (ret == SFC_OK) { 708 p_dev->read_lines = DATA_LINES_X4; 709 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 710 } 711 } 712 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 713 p_dev->read_lines == DATA_LINES_X4) { 714 p_dev->prog_lines = DATA_LINES_X4; 715 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 716 if ((p_dev->manufacturer == MID_MACRONIX) && 717 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 || 718 p_dev->prog_cmd == CMD_PAGE_PROG_4PP)) 719 p_dev->prog_addr_lines = DATA_LINES_X4; 720 } 721 722 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 723 p_dev->addr_mode = ADDR_MODE_4BYTE; 724 725 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 726 snor_enter_4byte_mode(); 727 } 728 729 return SFC_OK; 730 } 731 732 int snor_init(struct SFNOR_DEV *p_dev) 733 { 734 struct flash_info *g_spi_flash_info; 735 u8 id_byte[5]; 736 737 if (!p_dev) 738 return SFC_PARAM_ERR; 739 740 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 741 p_dev->max_iosize = sfc_get_max_iosize(); 742 743 snor_read_id(id_byte); 744 rkflash_print_error("sfc nor id: %x %x %x\n", 745 id_byte[0], id_byte[1], id_byte[2]); 746 if (0xFF == id_byte[0] || 0x00 == id_byte[0] || 0xFF == id_byte[1] || 0x00 == id_byte[1]) 747 return SFC_ERROR; 748 749 g_spi_flash_info = snor_get_flash_info(id_byte); 750 if (g_spi_flash_info) { 751 snor_parse_flash_table(p_dev, g_spi_flash_info); 752 } else { 753 pr_err("The device not support yet!\n"); 754 755 p_dev->manufacturer = id_byte[0]; 756 p_dev->mem_type = id_byte[1]; 757 p_dev->capacity = 1 << (id_byte[2] - 9); 758 p_dev->QE_bits = 0; 759 p_dev->blk_size = NOR_SECS_BLK; 760 p_dev->page_size = NOR_SECS_PAGE; 761 p_dev->read_cmd = CMD_READ_DATA; 762 p_dev->prog_cmd = CMD_PAGE_PROG; 763 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 764 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 765 p_dev->prog_lines = DATA_LINES_X1; 766 p_dev->prog_addr_lines = DATA_LINES_X1; 767 p_dev->read_lines = DATA_LINES_X1; 768 p_dev->write_status = snor_write_status; 769 snor_reset_device(); 770 } 771 772 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 773 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 774 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 775 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 776 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 777 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 778 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 779 rkflash_print_info("capacity: %x\n", p_dev->capacity); 780 781 return SFC_OK; 782 } 783 784 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 785 struct snor_info_packet *packet) 786 { 787 struct flash_info g_spi_flash_info; 788 u8 id_byte[5]; 789 int ret; 790 791 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 792 return SFC_PARAM_ERR; 793 794 snor_read_id(id_byte); 795 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 796 return SFC_ERROR; 797 798 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 799 g_spi_flash_info.block_size = NOR_SECS_BLK; 800 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 801 g_spi_flash_info.read_cmd = packet->read_cmd; 802 g_spi_flash_info.prog_cmd = packet->prog_cmd; 803 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 804 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 805 if (id_byte[2] >= 0x19) 806 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 807 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 808 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 809 g_spi_flash_info.feature = packet->feature; 810 g_spi_flash_info.density = id_byte[2] - 9; 811 g_spi_flash_info.QE_bits = packet->QE_bits; 812 813 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 814 815 return ret; 816 } 817 818