1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C*/ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 6, 0 }, 25 /* GD25B512MEYIG */ 26 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x3C, 17, 0, 0 }, 27 28 /* W25Q64JVSSIQ */ 29 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 30 /* W25Q128FV and W25Q128JV*/ 31 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 32 /* W25Q256F/J */ 33 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 34 /* W25Q256JWEQ*/ 35 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 36 /* W25Q64FWSSIG */ 37 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 38 /* W25Q128JVSIM */ 39 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 40 /* W25Q256JVEM */ 41 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 42 43 /* MX25L3233FM2I-08G */ 44 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 45 /* MX25L6433F */ 46 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 47 /* MX25L12835E/F MX25L12833FMI-10G */ 48 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 49 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 50 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 51 /* MX25L51245GMI */ 52 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 53 /* MX25U51245G */ 54 { 0xc2253a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 55 56 /* XM25QH32C */ 57 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 58 /* XM25QH64B */ 59 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 60 /* XM25QH128B */ 61 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 62 /* XM25QH(QU)256B */ 63 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 64 /* XM25QH64A */ 65 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 66 67 /* XT25F128A XM25QH128A */ 68 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 69 /* XT25F64BSSIGU-5 */ 70 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 71 /* XT25F128BSSIGU */ 72 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 73 /* XT25F256BSFIGU */ 74 { 0x0b4019, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 16, 9, 0 }, 75 76 /* EN25QH64A */ 77 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 78 /* EN25QH128A */ 79 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 80 /* EN25QH32B */ 81 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 82 /* EN25S32A */ 83 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 84 /* EN25S64A */ 85 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 86 /* EN25QH256A */ 87 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 88 89 /* ZB25VQ64 */ 90 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 91 /* ZB25VQ128 */ 92 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 93 /* ZB25LQ128 */ 94 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 95 96 /* BH25Q128AS */ 97 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 98 /* BH25Q64BS */ 99 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 100 /* P25Q64H */ 101 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 102 /* P25Q32SH-SSH-IT */ 103 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 104 105 /* FM25Q128A */ 106 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 107 /* FM25Q64-SOB-T-G */ 108 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 109 110 /* FM25Q64A */ 111 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 112 }; 113 114 static int snor_write_en(void) 115 { 116 int ret; 117 struct rk_sfc_op op; 118 119 op.sfcmd.d32 = 0; 120 op.sfcmd.b.cmd = CMD_WRITE_EN; 121 122 op.sfctrl.d32 = 0; 123 124 ret = sfc_request(&op, 0, NULL, 0); 125 126 return ret; 127 } 128 129 int snor_reset_device(void) 130 { 131 struct rk_sfc_op op; 132 133 op.sfcmd.d32 = 0; 134 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 135 136 op.sfctrl.d32 = 0; 137 sfc_request(&op, 0, NULL, 0); 138 139 op.sfcmd.d32 = 0; 140 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 141 142 op.sfctrl.d32 = 0; 143 sfc_request(&op, 0, NULL, 0); 144 /* tRST=30us , delay 1ms here */ 145 sfc_delay(1000); 146 147 return SFC_OK; 148 } 149 150 static int snor_enter_4byte_mode(void) 151 { 152 int ret; 153 struct rk_sfc_op op; 154 155 op.sfcmd.d32 = 0; 156 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 157 158 op.sfctrl.d32 = 0; 159 160 ret = sfc_request(&op, 0, NULL, 0); 161 return ret; 162 } 163 164 static int snor_read_status(u32 reg_index, u8 *status) 165 { 166 int ret; 167 struct rk_sfc_op op; 168 u8 read_stat_cmd[] = {CMD_READ_STATUS, 169 CMD_READ_STATUS2, CMD_READ_STATUS3}; 170 op.sfcmd.d32 = 0; 171 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 172 173 op.sfctrl.d32 = 0; 174 ret = sfc_request(&op, 0, status, 1); 175 176 return ret; 177 } 178 179 static int snor_wait_busy(int timeout) 180 { 181 int ret; 182 struct rk_sfc_op op; 183 int i; 184 u32 status; 185 186 op.sfcmd.d32 = 0; 187 op.sfcmd.b.cmd = CMD_READ_STATUS; 188 189 op.sfctrl.d32 = 0; 190 191 for (i = 0; i < timeout; i++) { 192 ret = sfc_request(&op, 0, &status, 1); 193 if (ret != SFC_OK) 194 return ret; 195 196 if ((status & 0x01) == 0) 197 return SFC_OK; 198 199 sfc_delay(1); 200 } 201 rkflash_print_error("%s error %x\n", __func__, timeout); 202 203 return SFC_BUSY_TIMEOUT; 204 } 205 206 static int snor_write_status2(u32 reg_index, u8 status) 207 { 208 int ret; 209 struct rk_sfc_op op; 210 u8 status2[2]; 211 212 status2[reg_index] = status; 213 if (reg_index == 0) 214 ret = snor_read_status(2, &status2[1]); 215 else 216 ret = snor_read_status(0, &status2[0]); 217 if (ret != SFC_OK) 218 return ret; 219 220 snor_write_en(); 221 222 op.sfcmd.d32 = 0; 223 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 224 op.sfcmd.b.rw = SFC_WRITE; 225 226 op.sfctrl.d32 = 0; 227 228 ret = sfc_request(&op, 0, &status2[0], 2); 229 if (ret != SFC_OK) 230 return ret; 231 232 ret = snor_wait_busy(10000); /* 10ms */ 233 234 return ret; 235 } 236 237 static int snor_write_status1(u32 reg_index, u8 status) 238 { 239 int ret; 240 struct rk_sfc_op op; 241 u8 status2[2]; 242 u8 read_index; 243 244 status2[reg_index] = status; 245 read_index = (reg_index == 0) ? 1 : 0; 246 ret = snor_read_status(read_index, &status2[read_index]); 247 if (ret != SFC_OK) 248 return ret; 249 250 snor_write_en(); 251 252 op.sfcmd.d32 = 0; 253 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 254 op.sfcmd.b.rw = SFC_WRITE; 255 256 op.sfctrl.d32 = 0; 257 258 ret = sfc_request(&op, 0, &status2[0], 2); 259 if (ret != SFC_OK) 260 return ret; 261 262 ret = snor_wait_busy(10000); /* 10ms */ 263 264 return ret; 265 } 266 267 static int snor_write_status(u32 reg_index, u8 status) 268 { 269 int ret; 270 struct rk_sfc_op op; 271 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 272 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 273 snor_write_en(); 274 op.sfcmd.d32 = 0; 275 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 276 op.sfcmd.b.rw = SFC_WRITE; 277 278 op.sfctrl.d32 = 0; 279 280 ret = sfc_request(&op, 0, &status, 1); 281 if (ret != SFC_OK) 282 return ret; 283 284 ret = snor_wait_busy(10000); /* 10ms */ 285 286 return ret; 287 } 288 289 int snor_erase(struct SFNOR_DEV *p_dev, 290 u32 addr, 291 enum NOR_ERASE_TYPE erase_type) 292 { 293 int ret; 294 struct rk_sfc_op op; 295 int timeout[] = {400, 2000, 40000}; /* ms */ 296 297 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 298 299 if (erase_type > ERASE_CHIP) 300 return SFC_PARAM_ERR; 301 302 op.sfcmd.d32 = 0; 303 if (erase_type == ERASE_BLOCK64K) 304 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 305 else if (erase_type == ERASE_SECTOR) 306 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 307 else 308 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 309 310 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 311 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 312 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 313 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 314 315 op.sfctrl.d32 = 0; 316 317 snor_write_en(); 318 319 ret = sfc_request(&op, addr, NULL, 0); 320 if (ret != SFC_OK) 321 return ret; 322 323 ret = snor_wait_busy(timeout[erase_type] * 1000); 324 return ret; 325 } 326 327 int snor_prog_page(struct SFNOR_DEV *p_dev, 328 u32 addr, 329 void *p_data, 330 u32 size) 331 { 332 int ret; 333 struct rk_sfc_op op; 334 335 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 336 337 op.sfcmd.d32 = 0; 338 op.sfcmd.b.cmd = p_dev->prog_cmd; 339 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 340 op.sfcmd.b.rw = SFC_WRITE; 341 342 op.sfctrl.d32 = 0; 343 op.sfctrl.b.datalines = p_dev->prog_lines; 344 op.sfctrl.b.enbledma = 1; 345 op.sfctrl.b.addrlines = p_dev->prog_addr_lines; 346 347 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 348 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 349 350 snor_write_en(); 351 352 ret = sfc_request(&op, addr, p_data, size); 353 if (ret != SFC_OK) 354 return ret; 355 356 ret = snor_wait_busy(10000); 357 358 return ret; 359 } 360 361 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 362 { 363 int ret = SFC_OK; 364 u32 page_size, len; 365 u8 *p_buf = (u8 *)p_data; 366 367 page_size = NOR_PAGE_SIZE; 368 while (size) { 369 len = page_size < size ? page_size : size; 370 ret = snor_prog_page(p_dev, addr, p_buf, len); 371 if (ret != SFC_OK) 372 return ret; 373 374 size -= len; 375 addr += len; 376 p_buf += len; 377 } 378 379 return ret; 380 } 381 382 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 383 { 384 int ret = SFC_OK; 385 int reg_index; 386 int bit_offset; 387 u8 status; 388 389 reg_index = p_dev->QE_bits >> 3; 390 bit_offset = p_dev->QE_bits & 0x7; 391 ret = snor_read_status(reg_index, &status); 392 if (ret != SFC_OK) 393 return ret; 394 395 if (status & (1 << bit_offset)) /* is QE bit set */ 396 return SFC_OK; 397 398 status |= (1 << bit_offset); 399 400 return p_dev->write_status(reg_index, status); 401 } 402 403 int snor_disable_QE(struct SFNOR_DEV *p_dev) 404 { 405 int ret = SFC_OK; 406 int reg_index; 407 int bit_offset; 408 u8 status; 409 410 reg_index = p_dev->QE_bits >> 3; 411 bit_offset = p_dev->QE_bits & 0x7; 412 ret = snor_read_status(reg_index, &status); 413 if (ret != SFC_OK) 414 return ret; 415 416 if (!(status & (1 << bit_offset))) 417 return SFC_OK; 418 419 status &= ~(1 << bit_offset); 420 421 return p_dev->write_status(reg_index, status); 422 } 423 424 int snor_read_data(struct SFNOR_DEV *p_dev, 425 u32 addr, 426 void *p_data, 427 u32 size) 428 { 429 int ret; 430 struct rk_sfc_op op; 431 432 op.sfcmd.d32 = 0; 433 op.sfcmd.b.cmd = p_dev->read_cmd; 434 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 435 436 op.sfctrl.d32 = 0; 437 op.sfctrl.b.datalines = p_dev->read_lines; 438 if (!(size & 0x3) && size >= 4) 439 op.sfctrl.b.enbledma = 1; 440 441 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 442 p_dev->read_cmd == CMD_FAST_READ_X4 || 443 p_dev->read_cmd == CMD_FAST_READ_X2 || 444 p_dev->read_cmd == CMD_FAST_4READ_X4) { 445 op.sfcmd.b.dummybits = 8; 446 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 447 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 448 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 449 op.sfcmd.b.dummybits = 4; 450 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 451 } 452 453 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 454 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 455 456 ret = sfc_request(&op, addr, p_data, size); 457 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 458 459 return ret; 460 } 461 462 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 463 { 464 int ret = SFC_OK; 465 u32 addr, size, len; 466 u8 *p_buf = (u8 *)p_data; 467 468 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 469 470 if ((sec + n_sec) > p_dev->capacity) 471 return SFC_PARAM_ERR; 472 473 addr = sec << 9; 474 size = n_sec << 9; 475 while (size) { 476 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 477 ret = snor_read_data(p_dev, addr, p_buf, len); 478 if (ret != SFC_OK) { 479 rkflash_print_error("snor_read_data %x ret= %x\n", 480 addr >> 9, ret); 481 goto out; 482 } 483 484 size -= len; 485 addr += len; 486 p_buf += len; 487 } 488 out: 489 if (!ret) 490 ret = n_sec; 491 492 return ret; 493 } 494 495 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 496 { 497 int ret = SFC_OK; 498 u32 len, blk_size, offset; 499 u8 *p_buf = (u8 *)p_data; 500 u32 total_sec = n_sec; 501 502 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 503 504 if ((sec + n_sec) > p_dev->capacity) 505 return SFC_PARAM_ERR; 506 507 while (n_sec) { 508 if (sec < 512 || sec >= p_dev->capacity - 512) 509 blk_size = 8; 510 else 511 blk_size = p_dev->blk_size; 512 513 offset = (sec & (blk_size - 1)); 514 if (!offset) { 515 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 516 ERASE_SECTOR : ERASE_BLOCK64K); 517 if (ret != SFC_OK) { 518 rkflash_print_error("snor_erase %x ret= %x\n", 519 sec, ret); 520 goto out; 521 } 522 } 523 len = (blk_size - offset) < n_sec ? 524 (blk_size - offset) : n_sec; 525 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 526 if (ret != SFC_OK) { 527 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 528 goto out; 529 } 530 n_sec -= len; 531 sec += len; 532 p_buf += len << 9; 533 } 534 out: 535 if (!ret) 536 ret = total_sec; 537 538 return ret; 539 } 540 541 int snor_read_id(u8 *data) 542 { 543 int ret; 544 struct rk_sfc_op op; 545 546 op.sfcmd.d32 = 0; 547 op.sfcmd.b.cmd = CMD_READ_JEDECID; 548 549 op.sfctrl.d32 = 0; 550 551 ret = sfc_request(&op, 0, data, 3); 552 553 return ret; 554 } 555 556 static int snor_read_parameter(u32 addr, u8 *data) 557 { 558 int ret; 559 struct rk_sfc_op op; 560 561 op.sfcmd.d32 = 0; 562 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 563 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 564 op.sfcmd.b.dummybits = 8; 565 566 op.sfctrl.d32 = 0; 567 568 ret = sfc_request(&op, addr, data, 1); 569 570 return ret; 571 } 572 573 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 574 { 575 return p_dev->capacity; 576 } 577 578 static struct flash_info *snor_get_flash_info(u8 *flash_id) 579 { 580 u32 i; 581 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 582 583 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 584 if (spi_flash_tbl[i].id == id) 585 return &spi_flash_tbl[i]; 586 } 587 return NULL; 588 } 589 590 /* Adjust flash info in ram base on parameter */ 591 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 592 { 593 u32 addr; 594 u8 para_version; 595 596 if (spi_flash_info->id == 0xc84019) { 597 addr = 0x09; 598 snor_read_parameter(addr, ¶_version); 599 if (para_version == 0x06) { 600 spi_flash_info->QE_bits = 9; 601 spi_flash_info->prog_cmd_4 = 0x34; 602 } 603 } 604 return 0; 605 } 606 607 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 608 struct flash_info *g_spi_flash_info) 609 { 610 int i, ret; 611 612 if (g_spi_flash_info) { 613 snor_flash_info_adjust(g_spi_flash_info); 614 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 615 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 616 p_dev->capacity = 1 << g_spi_flash_info->density; 617 p_dev->blk_size = g_spi_flash_info->block_size; 618 p_dev->page_size = NOR_SECS_PAGE; 619 p_dev->read_cmd = g_spi_flash_info->read_cmd; 620 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 621 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 622 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 623 p_dev->prog_lines = DATA_LINES_X1; 624 p_dev->read_lines = DATA_LINES_X1; 625 p_dev->QE_bits = g_spi_flash_info->QE_bits; 626 p_dev->addr_mode = ADDR_MODE_3BYTE; 627 628 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 629 if (i == 0) 630 p_dev->write_status = snor_write_status; 631 else if (i == 1) 632 p_dev->write_status = snor_write_status1; 633 else if (i == 2) 634 p_dev->write_status = snor_write_status2; 635 636 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 637 ret = SFC_OK; 638 if (g_spi_flash_info->QE_bits) 639 ret = snor_enable_QE(p_dev); 640 if (ret == SFC_OK) { 641 p_dev->read_lines = DATA_LINES_X4; 642 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 643 } 644 } 645 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 646 p_dev->read_lines == DATA_LINES_X4) { 647 p_dev->prog_lines = DATA_LINES_X4; 648 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 649 if ((p_dev->manufacturer == MID_MACRONIX) && 650 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 || 651 p_dev->prog_cmd == CMD_PAGE_PROG_4PP)) 652 p_dev->prog_addr_lines = DATA_LINES_X4; 653 } 654 655 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 656 p_dev->addr_mode = ADDR_MODE_4BYTE; 657 658 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 659 snor_enter_4byte_mode(); 660 } 661 662 return SFC_OK; 663 } 664 665 int snor_init(struct SFNOR_DEV *p_dev) 666 { 667 struct flash_info *g_spi_flash_info; 668 u8 id_byte[5]; 669 670 if (!p_dev) 671 return SFC_PARAM_ERR; 672 673 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 674 p_dev->max_iosize = sfc_get_max_iosize(); 675 676 snor_read_id(id_byte); 677 rkflash_print_error("sfc nor id: %x %x %x\n", 678 id_byte[0], id_byte[1], id_byte[2]); 679 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 680 return SFC_ERROR; 681 682 g_spi_flash_info = snor_get_flash_info(id_byte); 683 if (g_spi_flash_info) { 684 snor_parse_flash_table(p_dev, g_spi_flash_info); 685 } else { 686 p_dev->manufacturer = id_byte[0]; 687 p_dev->mem_type = id_byte[1]; 688 p_dev->capacity = 1 << (id_byte[2] - 9); 689 p_dev->QE_bits = 0; 690 p_dev->blk_size = NOR_SECS_BLK; 691 p_dev->page_size = NOR_SECS_PAGE; 692 p_dev->read_cmd = CMD_READ_DATA; 693 p_dev->prog_cmd = CMD_PAGE_PROG; 694 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 695 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 696 p_dev->prog_lines = DATA_LINES_X1; 697 p_dev->prog_addr_lines = DATA_LINES_X1; 698 p_dev->read_lines = DATA_LINES_X1; 699 p_dev->write_status = snor_write_status; 700 snor_reset_device(); 701 } 702 703 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 704 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 705 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 706 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 707 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 708 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 709 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 710 rkflash_print_info("capacity: %x\n", p_dev->capacity); 711 712 return SFC_OK; 713 } 714 715 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 716 struct snor_info_packet *packet) 717 { 718 struct flash_info g_spi_flash_info; 719 u8 id_byte[5]; 720 int ret; 721 722 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 723 return SFC_PARAM_ERR; 724 725 snor_read_id(id_byte); 726 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 727 return SFC_ERROR; 728 729 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 730 g_spi_flash_info.block_size = NOR_SECS_BLK; 731 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 732 g_spi_flash_info.read_cmd = packet->read_cmd; 733 g_spi_flash_info.prog_cmd = packet->prog_cmd; 734 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 735 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 736 if (id_byte[2] >= 0x19) 737 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 738 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 739 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 740 g_spi_flash_info.feature = packet->feature; 741 g_spi_flash_info.density = id_byte[2] - 9; 742 g_spi_flash_info.QE_bits = packet->QE_bits; 743 744 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 745 746 return ret; 747 } 748 749