1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C*/ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 25 /* 25Q64JVSSIQ */ 26 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 27 /* 25Q128FV and 25Q128JV*/ 28 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 29 /* 25Q256F/J */ 30 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 31 /* 25Q64FWSSIG */ 32 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 33 /* MX25L6433F */ 34 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 35 /* MX25L12835E/F MX25L12833FMI-10G */ 36 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 37 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G*/ 38 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 16, 6, 0 }, 39 /* MX25L51245GMI */ 40 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x38, 0x21, 0xDC, 0x3E, 17, 6, 0 }, 41 /* XM25QH32C */ 42 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 43 /* XM25QH64B */ 44 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 45 /* XM25QH128B */ 46 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 47 /* XM25QH(QU)256B */ 48 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 49 /* XM25QH64A */ 50 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 51 /* XT25F128A XM25QH128A */ 52 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x00, 15, 0, 0 }, 53 /* XT25F64BSSIGU-5 */ 54 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 55 /* XT25F128BSSIGU */ 56 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 57 /* EN25QH128A */ 58 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 59 /* EN25S32A */ 60 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 61 /* EN25S64A */ 62 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 63 /* P25Q64H */ 64 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 65 /* EN25QH256A */ 66 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 67 /* FM25Q64A */ 68 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 69 /* ZB25VQ64 */ 70 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 71 /* ZB25VQ128 */ 72 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 73 }; 74 75 static int snor_write_en(void) 76 { 77 int ret; 78 union SFCCMD_DATA sfcmd; 79 80 sfcmd.d32 = 0; 81 sfcmd.b.cmd = CMD_WRITE_EN; 82 83 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 84 85 return ret; 86 } 87 88 int snor_reset_device(void) 89 { 90 int ret; 91 union SFCCMD_DATA sfcmd; 92 93 sfcmd.d32 = 0; 94 sfcmd.b.cmd = CMD_ENABLE_RESER; 95 sfc_request(sfcmd.d32, 0, 0, NULL); 96 97 sfcmd.d32 = 0; 98 sfcmd.b.cmd = CMD_RESET_DEVICE; 99 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 100 /* tRST=30us , delay 1ms here */ 101 mdelay(1); 102 return ret; 103 } 104 105 static int snor_enter_4byte_mode(void) 106 { 107 int ret; 108 union SFCCMD_DATA sfcmd; 109 110 sfcmd.d32 = 0; 111 sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 112 113 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 114 return ret; 115 } 116 117 static int snor_read_status(u32 reg_index, u8 *status) 118 { 119 int ret; 120 union SFCCMD_DATA sfcmd; 121 u8 read_stat_cmd[] = {CMD_READ_STATUS, 122 CMD_READ_STATUS2, CMD_READ_STATUS3}; 123 sfcmd.d32 = 0; 124 sfcmd.b.cmd = read_stat_cmd[reg_index]; 125 sfcmd.b.datasize = 1; 126 127 ret = sfc_request(sfcmd.d32, 0, 0, status); 128 129 return ret; 130 } 131 132 static int snor_wait_busy(int timeout) 133 { 134 int ret; 135 union SFCCMD_DATA sfcmd; 136 int i; 137 u32 status; 138 139 sfcmd.d32 = 0; 140 sfcmd.b.cmd = CMD_READ_STATUS; 141 sfcmd.b.datasize = 1; 142 143 for (i = 0; i < timeout; i++) { 144 ret = sfc_request(sfcmd.d32, 0, 0, &status); 145 if (ret != SFC_OK) 146 return ret; 147 148 if ((status & 0x01) == 0) 149 return SFC_OK; 150 151 sfc_delay(1); 152 } 153 rkflash_print_error("%s error %x\n", __func__, timeout); 154 155 return SFC_BUSY_TIMEOUT; 156 } 157 158 static int snor_write_status2(u32 reg_index, u8 status) 159 { 160 int ret; 161 union SFCCMD_DATA sfcmd; 162 u8 status2[2]; 163 u8 read_index; 164 165 status2[reg_index] = status; 166 read_index = (reg_index == 0) ? 2 : 0; 167 ret = snor_read_status(read_index, &status2[read_index]); 168 if (ret != SFC_OK) 169 return ret; 170 171 snor_write_en(); 172 173 sfcmd.d32 = 0; 174 sfcmd.b.cmd = CMD_WRITE_STATUS; 175 sfcmd.b.datasize = 2; 176 sfcmd.b.rw = SFC_WRITE; 177 178 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 179 if (ret != SFC_OK) 180 return ret; 181 182 ret = snor_wait_busy(10000); /* 10ms */ 183 184 return ret; 185 } 186 187 static int snor_write_status1(u32 reg_index, u8 status) 188 { 189 int ret; 190 union SFCCMD_DATA sfcmd; 191 u8 status2[2]; 192 u8 read_index; 193 194 status2[reg_index] = status; 195 read_index = (reg_index == 0) ? 1 : 0; 196 ret = snor_read_status(read_index, &status2[read_index]); 197 if (ret != SFC_OK) 198 return ret; 199 200 snor_write_en(); 201 202 sfcmd.d32 = 0; 203 sfcmd.b.cmd = CMD_WRITE_STATUS; 204 sfcmd.b.datasize = 2; 205 sfcmd.b.rw = SFC_WRITE; 206 207 ret = sfc_request(sfcmd.d32, 0, 0, &status2[0]); 208 if (ret != SFC_OK) 209 return ret; 210 211 ret = snor_wait_busy(10000); /* 10ms */ 212 213 return ret; 214 } 215 216 static int snor_write_status(u32 reg_index, u8 status) 217 { 218 int ret; 219 union SFCCMD_DATA sfcmd; 220 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 221 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 222 snor_write_en(); 223 sfcmd.d32 = 0; 224 sfcmd.b.cmd = write_stat_cmd[reg_index]; 225 sfcmd.b.datasize = 1; 226 sfcmd.b.rw = SFC_WRITE; 227 228 ret = sfc_request(sfcmd.d32, 0, 0, &status); 229 if (ret != SFC_OK) 230 return ret; 231 232 ret = snor_wait_busy(10000); /* 10ms */ 233 234 return ret; 235 } 236 237 int snor_erase(struct SFNOR_DEV *p_dev, 238 u32 addr, 239 enum NOR_ERASE_TYPE erase_type) 240 { 241 int ret; 242 union SFCCMD_DATA sfcmd; 243 int timeout[] = {400, 2000, 40000}; /* ms */ 244 245 rkflash_print_dio("%s %x\n", __func__, addr); 246 247 if (erase_type > ERASE_CHIP) 248 return SFC_PARAM_ERR; 249 250 sfcmd.d32 = 0; 251 if (erase_type == ERASE_BLOCK64K) 252 sfcmd.b.cmd = p_dev->blk_erase_cmd; 253 else if (erase_type == ERASE_SECTOR) 254 sfcmd.b.cmd = p_dev->sec_erase_cmd; 255 else 256 sfcmd.b.cmd = CMD_CHIP_ERASE; 257 258 sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 259 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 260 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 261 sfcmd.b.addrbits = SFC_ADDR_32BITS; 262 263 snor_write_en(); 264 265 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 266 if (ret != SFC_OK) 267 return ret; 268 269 ret = snor_wait_busy(timeout[erase_type] * 1000); 270 return ret; 271 } 272 273 int snor_prog_page(struct SFNOR_DEV *p_dev, 274 u32 addr, 275 void *p_data, 276 u32 size) 277 { 278 int ret; 279 union SFCCMD_DATA sfcmd; 280 union SFCCTRL_DATA sfctrl; 281 282 sfcmd.d32 = 0; 283 sfcmd.b.cmd = p_dev->prog_cmd; 284 sfcmd.b.addrbits = SFC_ADDR_24BITS; 285 sfcmd.b.datasize = size; 286 sfcmd.b.rw = SFC_WRITE; 287 288 sfctrl.d32 = 0; 289 sfctrl.b.datalines = p_dev->prog_lines; 290 sfctrl.b.enbledma = 0; 291 if (p_dev->prog_cmd == CMD_PAGE_PROG_A4) 292 sfctrl.b.addrlines = SFC_4BITS_LINE; 293 294 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 295 sfcmd.b.addrbits = SFC_ADDR_32BITS; 296 297 snor_write_en(); 298 299 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 300 if (ret != SFC_OK) 301 return ret; 302 303 ret = snor_wait_busy(10000); 304 305 return ret; 306 } 307 308 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 309 { 310 int ret = SFC_OK; 311 u32 page_size, len; 312 u8 *p_buf = (u8 *)p_data; 313 314 page_size = NOR_PAGE_SIZE; 315 while (size) { 316 len = page_size < size ? page_size : size; 317 ret = snor_prog_page(p_dev, addr, p_buf, len); 318 if (ret != SFC_OK) 319 return ret; 320 321 size -= len; 322 addr += len; 323 p_buf += len; 324 } 325 326 return ret; 327 } 328 329 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 330 { 331 int ret = SFC_OK; 332 int reg_index; 333 int bit_offset; 334 u8 status; 335 336 if (p_dev->manufacturer == MID_GIGADEV || 337 p_dev->manufacturer == MID_WINBOND || 338 p_dev->manufacturer == MID_XTX || 339 p_dev->manufacturer == MID_MACRONIX || 340 p_dev->manufacturer == MID_PUYA || 341 p_dev->manufacturer == MID_XMC || 342 p_dev->manufacturer == MID_DOSILICON || 343 p_dev->manufacturer == MID_ZBIT) { 344 reg_index = p_dev->QE_bits >> 3; 345 bit_offset = p_dev->QE_bits & 0x7; 346 ret = snor_read_status(reg_index, &status); 347 if (ret != SFC_OK) 348 return ret; 349 350 if (status & (1 << bit_offset)) /* is QE bit set */ 351 return SFC_OK; 352 353 status |= (1 << bit_offset); 354 return p_dev->write_status(reg_index, status); 355 } 356 357 return ret; 358 } 359 360 int snor_disable_QE(struct SFNOR_DEV *p_dev) 361 { 362 int ret = SFC_OK; 363 int reg_index; 364 int bit_offset; 365 u8 status; 366 367 if (p_dev->manufacturer == MID_GIGADEV || 368 p_dev->manufacturer == MID_WINBOND || 369 p_dev->manufacturer == MID_XTX || 370 p_dev->manufacturer == MID_MACRONIX || 371 p_dev->manufacturer == MID_PUYA || 372 p_dev->manufacturer == MID_XMC || 373 p_dev->manufacturer == MID_DOSILICON || 374 p_dev->manufacturer == MID_ZBIT) { 375 reg_index = p_dev->QE_bits >> 3; 376 bit_offset = p_dev->QE_bits & 0x7; 377 ret = snor_read_status(reg_index, &status); 378 if (ret != SFC_OK) 379 return ret; 380 381 if (!(status & (1 << bit_offset))) 382 return SFC_OK; 383 384 status &= ~(1 << bit_offset); 385 return p_dev->write_status(reg_index, status); 386 } 387 388 return ret; 389 } 390 391 int snor_read_data(struct SFNOR_DEV *p_dev, 392 u32 addr, 393 void *p_data, 394 u32 size) 395 { 396 int ret; 397 union SFCCMD_DATA sfcmd; 398 union SFCCTRL_DATA sfctrl; 399 400 sfcmd.d32 = 0; 401 sfcmd.b.cmd = p_dev->read_cmd; 402 sfcmd.b.datasize = size; 403 sfcmd.b.addrbits = SFC_ADDR_24BITS; 404 405 sfctrl.d32 = 0; 406 sfctrl.b.datalines = p_dev->read_lines; 407 if (!(size & 0x3) && size >= 4) 408 sfctrl.b.enbledma = 0; 409 410 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 411 p_dev->read_cmd == CMD_FAST_READ_X4 || 412 p_dev->read_cmd == CMD_FAST_READ_X2 || 413 p_dev->read_cmd == CMD_FAST_4READ_X4) { 414 sfcmd.b.dummybits = 8; 415 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 416 sfcmd.b.addrbits = SFC_ADDR_32BITS; 417 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 418 sfcmd.b.dummybits = 4; 419 sfctrl.b.addrlines = SFC_4BITS_LINE; 420 } 421 422 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 423 sfcmd.b.addrbits = SFC_ADDR_32BITS; 424 425 ret = sfc_request(sfcmd.d32, sfctrl.d32, addr, p_data); 426 427 return ret; 428 } 429 430 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 431 { 432 int ret = SFC_OK; 433 u32 addr, size, len; 434 u8 *p_buf = (u8 *)p_data; 435 436 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 437 438 if ((sec + n_sec) > p_dev->capacity) 439 return SFC_PARAM_ERR; 440 441 addr = sec << 9; 442 size = n_sec << 9; 443 while (size) { 444 len = size < SFC_MAX_IOSIZE ? size : SFC_MAX_IOSIZE; 445 ret = snor_read_data(p_dev, addr, p_buf, len); 446 if (ret != SFC_OK) { 447 rkflash_print_error("snor_read_data %x ret= %x\n", 448 addr >> 9, ret); 449 goto out; 450 } 451 452 size -= len; 453 addr += len; 454 p_buf += len; 455 } 456 out: 457 if (!ret) 458 ret = n_sec; 459 460 return ret; 461 } 462 463 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 464 { 465 int ret = SFC_OK; 466 u32 len, blk_size, offset; 467 u8 *p_buf = (u8 *)p_data; 468 u32 total_sec = n_sec; 469 470 rkflash_print_dio("%s %x %x %x\n", __func__, sec, n_sec, ((u32 *)p_data)[0]); 471 472 if ((sec + n_sec) > p_dev->capacity) 473 return SFC_PARAM_ERR; 474 475 while (n_sec) { 476 if (sec < 512 || sec >= p_dev->capacity - 512) 477 blk_size = 8; 478 else 479 blk_size = p_dev->blk_size; 480 481 offset = (sec & (blk_size - 1)); 482 if (!offset) { 483 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 484 ERASE_SECTOR : ERASE_BLOCK64K); 485 if (ret != SFC_OK) { 486 rkflash_print_error("snor_erase %x ret= %x\n", 487 sec, ret); 488 goto out; 489 } 490 } 491 len = (blk_size - offset) < n_sec ? 492 (blk_size - offset) : n_sec; 493 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 494 if (ret != SFC_OK) { 495 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 496 goto out; 497 } 498 n_sec -= len; 499 sec += len; 500 p_buf += len << 9; 501 } 502 out: 503 if (!ret) 504 ret = total_sec; 505 506 return ret; 507 } 508 509 int snor_read_id(u8 *data) 510 { 511 int ret; 512 union SFCCMD_DATA sfcmd; 513 514 sfcmd.d32 = 0; 515 sfcmd.b.cmd = CMD_READ_JEDECID; 516 sfcmd.b.datasize = 3; 517 518 ret = sfc_request(sfcmd.d32, 0, 0, data); 519 520 return ret; 521 } 522 523 static int snor_read_parameter(u32 addr, u8 *data) 524 { 525 int ret; 526 union SFCCMD_DATA sfcmd; 527 528 sfcmd.d32 = 0; 529 sfcmd.b.cmd = CMD_READ_PARAMETER; 530 sfcmd.b.datasize = 1; 531 sfcmd.b.addrbits = SFC_ADDR_24BITS; 532 sfcmd.b.dummybits = 8; 533 534 ret = sfc_request(sfcmd.d32, 0, addr, data); 535 536 return ret; 537 } 538 539 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 540 { 541 return p_dev->capacity; 542 } 543 544 static struct flash_info *snor_get_flash_info(u8 *flash_id) 545 { 546 u32 i; 547 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 548 549 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 550 if (spi_flash_tbl[i].id == id) 551 return &spi_flash_tbl[i]; 552 } 553 return NULL; 554 } 555 556 /* Adjust flash info in ram base on parameter */ 557 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 558 { 559 u32 addr; 560 u8 para_version; 561 562 if (spi_flash_info->id == 0xc84019) { 563 addr = 0x09; 564 snor_read_parameter(addr, ¶_version); 565 if (para_version == 0x06) { 566 spi_flash_info->QE_bits = 9; 567 spi_flash_info->prog_cmd_4 = 0x34; 568 } 569 } 570 return 0; 571 } 572 573 int snor_init(struct SFNOR_DEV *p_dev) 574 { 575 struct flash_info *g_spi_flash_info; 576 u32 i; 577 u8 id_byte[5]; 578 579 if (!p_dev) 580 return SFC_PARAM_ERR; 581 582 memset(p_dev, 0, sizeof(struct SFNOR_DEV)); 583 snor_read_id(id_byte); 584 rkflash_print_error("sfc nor id: %x %x %x\n", 585 id_byte[0], id_byte[1], id_byte[2]); 586 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 587 return SFC_ERROR; 588 589 p_dev->manufacturer = id_byte[0]; 590 p_dev->mem_type = id_byte[1]; 591 592 g_spi_flash_info = snor_get_flash_info(id_byte); 593 if (g_spi_flash_info) { 594 snor_flash_info_adjust(g_spi_flash_info); 595 p_dev->capacity = 1 << g_spi_flash_info->density; 596 p_dev->blk_size = g_spi_flash_info->block_size; 597 p_dev->page_size = NOR_SECS_PAGE; 598 p_dev->read_cmd = g_spi_flash_info->read_cmd; 599 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 600 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 601 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 602 p_dev->prog_lines = DATA_LINES_X1; 603 p_dev->read_lines = DATA_LINES_X1; 604 p_dev->QE_bits = g_spi_flash_info->QE_bits; 605 p_dev->addr_mode = ADDR_MODE_3BYTE; 606 607 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 608 if (i == 0) 609 p_dev->write_status = snor_write_status; 610 else if (i == 1) 611 p_dev->write_status = snor_write_status1; 612 else if (i == 2) 613 p_dev->write_status = snor_write_status2; 614 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 615 if (snor_enable_QE(p_dev) == SFC_OK) { 616 p_dev->read_lines = DATA_LINES_X4; 617 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 618 } 619 } 620 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 621 p_dev->read_lines == DATA_LINES_X4) { 622 p_dev->prog_lines = DATA_LINES_X4; 623 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 624 } 625 626 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 627 p_dev->addr_mode = ADDR_MODE_4BYTE; 628 629 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 630 snor_enter_4byte_mode(); 631 } else { 632 p_dev->capacity = 1 << id_byte[2] >> 3; 633 p_dev->QE_bits = 0; 634 p_dev->blk_size = NOR_SECS_BLK; 635 p_dev->page_size = NOR_SECS_PAGE; 636 p_dev->read_cmd = CMD_READ_DATA; 637 p_dev->prog_cmd = CMD_PAGE_PROG; 638 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 639 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 640 p_dev->prog_lines = DATA_LINES_X1; 641 p_dev->read_lines = DATA_LINES_X1; 642 p_dev->write_status = snor_write_status; 643 } 644 645 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 646 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 647 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 648 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 649 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 650 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 651 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 652 653 return SFC_OK; 654 } 655 656