1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 #include <linux/compat.h> 7 #include <linux/delay.h> 8 #include <linux/kernel.h> 9 #include <linux/string.h> 10 11 #include "rkflash_debug.h" 12 #include "sfc_nor.h" 13 14 static struct flash_info spi_flash_tbl[] = { 15 /* GD25Q32B */ 16 { 0xc84016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 17 /* GD25Q64B/E */ 18 { 0xc84017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 19 /* GD25Q127C and GD25Q128C/E */ 20 { 0xc84018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 21 /* GD25Q256B/C/D/E */ 22 { 0xc84019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 16, 6, 0 }, 23 /* GD25Q512MC */ 24 { 0xc84020, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1C, 17, 6, 0 }, 25 /* GD25LQ64C */ 26 { 0xc86017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 27 /* GD25LQ32E */ 28 { 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 29 /* GD25B512MEYIG */ 30 { 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 31 /* GD25LQ255E and GD25LQ256C */ 32 { 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 }, 33 /* GD25LB512MEYIG */ 34 { 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 }, 35 36 /* W25Q32JV */ 37 { 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 38 /* W25Q64JVSSIQ */ 39 { 0xef4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 40 /* W25Q128FV and W25Q128JV*/ 41 { 0xef4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 42 /* W25Q256F/J */ 43 { 0xef4019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 44 /* W25Q32JW */ 45 { 0xef6016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 46 /* W25Q64FWSSIG */ 47 { 0xef6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 48 /* W25Q128JWSQ */ 49 { 0xef6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 50 /* W25Q256JWEQ*/ 51 { 0xef6019, 128, 8, 0x13, 0x02, 0x6C, 0x32, 0x20, 0xD8, 0x3C, 16, 9, 0 }, 52 /* W25Q128JVSIM */ 53 { 0xef7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 54 /* W25Q256JVEM */ 55 { 0xef7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 9, 0 }, 56 57 /* MX25L3233FM2I-08G */ 58 { 0xc22016, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 59 /* MX25L6433F */ 60 { 0xc22017, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 61 /* MX25L12835E/F MX25L12833FMI-10G */ 62 { 0xc22018, 128, 8, 0x03, 0x02, 0x6B, 0x38, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 63 /* MX25L25635E/F MX25L25645G MX25L25645GMI-08G */ 64 { 0xc22019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 65 /* MX25L51245GMI */ 66 { 0xc2201a, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 67 /* MX25U51245G */ 68 { 0xc2253a, 128, 8, 0x0C, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 17, 6, 0 }, 69 /* MX25U3232F */ 70 { 0xc22536, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 13, 6, 0 }, 71 /* MX25U6432F */ 72 { 0xc22537, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 14, 6, 0 }, 73 /* MX25U12832F */ 74 { 0xc22538, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0E, 15, 6, 0 }, 75 /* MX25U25645GZ4I-00 */ 76 { 0xc22539, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1E, 16, 6, 0 }, 77 78 /* XM25QH32C */ 79 { 0x204016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 80 /* XM25QH64C */ 81 { 0x204017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 82 /* XM25QH128C */ 83 { 0x204018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 84 /* XM25QH256C */ 85 { 0x204019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 86 /* XM25QH64B */ 87 { 0x206017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 6, 0 }, 88 /* XM25QH128B */ 89 { 0x206018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 6, 0 }, 90 /* XM25QH(QU)256B */ 91 { 0x206019, 128, 8, 0x13, 0x12, 0x6C, 0x3E, 0x21, 0xDC, 0x1D, 16, 6, 0 }, 92 /* XM25QH64A */ 93 { 0x207017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 94 /* XM25QU128C */ 95 { 0x204118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 96 /* XM25QU64C */ 97 { 0x204117, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 98 99 /* XT25F128A XM25QH128A */ 100 { 0x207018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 101 /* XT25F64BSSIGU-5 XT25F64F */ 102 { 0x0b4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 103 /* XT25F128BSSIGU */ 104 { 0x0b4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 105 /* XT25F256BSFIGU */ 106 { 0x0b4019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 }, 107 /* XT25F32BS */ 108 { 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 }, 109 /* XT25F16BS */ 110 { 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 111 112 /* EN25QH64A */ 113 { 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 114 /* EN25QH128A */ 115 { 0x1c7018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 0, 0 }, 116 /* EN25QH32B */ 117 { 0x1c7016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 118 /* EN25S32A */ 119 { 0x1c3816, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 0, 0 }, 120 /* EN25S64A */ 121 { 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 }, 122 /* EN25QH256A */ 123 { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 }, 124 125 /* P25Q64H */ 126 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 127 /* P25Q128H */ 128 { 0x856018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 129 /* P25Q16H-SUH-IT */ 130 { 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 }, 131 /* FM25Q64A */ 132 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 133 /* FM25M64C */ 134 { 0xf84317, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 135 /* P25Q32SL */ 136 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 137 138 /* ZB25VQ64 */ 139 { 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 140 /* ZB25VQ128 */ 141 { 0x5e4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 142 /* ZB25LQ128 */ 143 { 0x5e5018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 144 145 /* BH25Q128AS */ 146 { 0x684018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 147 /* BH25Q64BS */ 148 { 0x684017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 149 150 /* P25Q64H */ 151 { 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 152 /* P25Q32SH-SSH-IT */ 153 { 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 }, 154 155 /* FM25Q128A */ 156 { 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 157 /* FM25Q64-SOB-T-G */ 158 { 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 }, 159 160 /* FM25Q64A */ 161 { 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 }, 162 /* FM25M4AA */ 163 { 0xf84218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 15, 9, 0 }, 164 /* DS25M4AB-1AIB4 */ 165 { 0xe54218, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 166 167 /* GM25Q128A */ 168 { 0x1c4018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 }, 169 }; 170 171 static int snor_write_en(void) 172 { 173 int ret; 174 struct rk_sfc_op op; 175 176 op.sfcmd.d32 = 0; 177 op.sfcmd.b.cmd = CMD_WRITE_EN; 178 179 op.sfctrl.d32 = 0; 180 181 ret = sfc_request(&op, 0, NULL, 0); 182 183 return ret; 184 } 185 186 int snor_reset_device(void) 187 { 188 struct rk_sfc_op op; 189 190 op.sfcmd.d32 = 0; 191 op.sfcmd.b.cmd = CMD_ENABLE_RESER; 192 193 op.sfctrl.d32 = 0; 194 sfc_request(&op, 0, NULL, 0); 195 196 op.sfcmd.d32 = 0; 197 op.sfcmd.b.cmd = CMD_RESET_DEVICE; 198 199 op.sfctrl.d32 = 0; 200 sfc_request(&op, 0, NULL, 0); 201 /* tRST=30us , delay 1ms here */ 202 sfc_delay(1000); 203 204 return SFC_OK; 205 } 206 207 static int snor_enter_4byte_mode(void) 208 { 209 int ret; 210 struct rk_sfc_op op; 211 212 op.sfcmd.d32 = 0; 213 op.sfcmd.b.cmd = CMD_ENTER_4BYTE_MODE; 214 215 op.sfctrl.d32 = 0; 216 217 ret = sfc_request(&op, 0, NULL, 0); 218 return ret; 219 } 220 221 static int snor_read_status(u32 reg_index, u8 *status) 222 { 223 int ret; 224 struct rk_sfc_op op; 225 u8 read_stat_cmd[] = {CMD_READ_STATUS, 226 CMD_READ_STATUS2, CMD_READ_STATUS3}; 227 op.sfcmd.d32 = 0; 228 op.sfcmd.b.cmd = read_stat_cmd[reg_index]; 229 230 op.sfctrl.d32 = 0; 231 ret = sfc_request(&op, 0, status, 1); 232 233 return ret; 234 } 235 236 static int snor_wait_busy(int timeout) 237 { 238 int ret; 239 struct rk_sfc_op op; 240 int i; 241 u32 status; 242 243 op.sfcmd.d32 = 0; 244 op.sfcmd.b.cmd = CMD_READ_STATUS; 245 246 op.sfctrl.d32 = 0; 247 248 for (i = 0; i < timeout; i++) { 249 ret = sfc_request(&op, 0, &status, 1); 250 if (ret != SFC_OK) 251 return ret; 252 253 if ((status & 0x01) == 0) 254 return SFC_OK; 255 256 sfc_delay(1); 257 } 258 rkflash_print_error("%s error %x\n", __func__, timeout); 259 260 return SFC_BUSY_TIMEOUT; 261 } 262 263 static int snor_write_status2(u32 reg_index, u8 status) 264 { 265 int ret; 266 struct rk_sfc_op op; 267 u8 status2[2]; 268 269 status2[reg_index] = status; 270 if (reg_index == 0) 271 ret = snor_read_status(2, &status2[1]); 272 else 273 ret = snor_read_status(0, &status2[0]); 274 if (ret != SFC_OK) 275 return ret; 276 277 snor_write_en(); 278 279 op.sfcmd.d32 = 0; 280 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 281 op.sfcmd.b.rw = SFC_WRITE; 282 283 op.sfctrl.d32 = 0; 284 285 ret = sfc_request(&op, 0, &status2[0], 2); 286 if (ret != SFC_OK) 287 return ret; 288 289 ret = snor_wait_busy(10000); /* 10ms */ 290 291 return ret; 292 } 293 294 static int snor_write_status1(u32 reg_index, u8 status) 295 { 296 int ret; 297 struct rk_sfc_op op; 298 u8 status2[2]; 299 u8 read_index; 300 301 status2[reg_index] = status; 302 read_index = (reg_index == 0) ? 1 : 0; 303 ret = snor_read_status(read_index, &status2[read_index]); 304 if (ret != SFC_OK) 305 return ret; 306 307 snor_write_en(); 308 309 op.sfcmd.d32 = 0; 310 op.sfcmd.b.cmd = CMD_WRITE_STATUS; 311 op.sfcmd.b.rw = SFC_WRITE; 312 313 op.sfctrl.d32 = 0; 314 315 ret = sfc_request(&op, 0, &status2[0], 2); 316 if (ret != SFC_OK) 317 return ret; 318 319 ret = snor_wait_busy(10000); /* 10ms */ 320 321 return ret; 322 } 323 324 static int snor_write_status(u32 reg_index, u8 status) 325 { 326 int ret; 327 struct rk_sfc_op op; 328 u8 write_stat_cmd[] = {CMD_WRITE_STATUS, 329 CMD_WRITE_STATUS2, CMD_WRITE_STATUS3}; 330 snor_write_en(); 331 op.sfcmd.d32 = 0; 332 op.sfcmd.b.cmd = write_stat_cmd[reg_index]; 333 op.sfcmd.b.rw = SFC_WRITE; 334 335 op.sfctrl.d32 = 0; 336 337 ret = sfc_request(&op, 0, &status, 1); 338 if (ret != SFC_OK) 339 return ret; 340 341 ret = snor_wait_busy(10000); /* 10ms */ 342 343 return ret; 344 } 345 346 int snor_erase(struct SFNOR_DEV *p_dev, 347 u32 addr, 348 enum NOR_ERASE_TYPE erase_type) 349 { 350 int ret; 351 struct rk_sfc_op op; 352 int timeout[] = {400, 2000, 40000}; /* ms */ 353 354 rkflash_print_dio("%s %x %x\n", __func__, addr, erase_type); 355 356 if (erase_type > ERASE_CHIP) 357 return SFC_PARAM_ERR; 358 359 op.sfcmd.d32 = 0; 360 if (erase_type == ERASE_BLOCK64K) 361 op.sfcmd.b.cmd = p_dev->blk_erase_cmd; 362 else if (erase_type == ERASE_SECTOR) 363 op.sfcmd.b.cmd = p_dev->sec_erase_cmd; 364 else 365 op.sfcmd.b.cmd = CMD_CHIP_ERASE; 366 367 op.sfcmd.b.addrbits = (erase_type != ERASE_CHIP) ? 368 SFC_ADDR_24BITS : SFC_ADDR_0BITS; 369 if (p_dev->addr_mode == ADDR_MODE_4BYTE && erase_type != ERASE_CHIP) 370 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 371 372 op.sfctrl.d32 = 0; 373 374 snor_write_en(); 375 376 ret = sfc_request(&op, addr, NULL, 0); 377 if (ret != SFC_OK) 378 return ret; 379 380 ret = snor_wait_busy(timeout[erase_type] * 1000); 381 return ret; 382 } 383 384 int snor_prog_page(struct SFNOR_DEV *p_dev, 385 u32 addr, 386 void *p_data, 387 u32 size) 388 { 389 int ret; 390 struct rk_sfc_op op; 391 392 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 393 394 op.sfcmd.d32 = 0; 395 op.sfcmd.b.cmd = p_dev->prog_cmd; 396 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 397 op.sfcmd.b.rw = SFC_WRITE; 398 399 op.sfctrl.d32 = 0; 400 op.sfctrl.b.datalines = p_dev->prog_lines; 401 op.sfctrl.b.enbledma = 1; 402 op.sfctrl.b.addrlines = p_dev->prog_addr_lines; 403 404 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 405 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 406 407 snor_write_en(); 408 409 ret = sfc_request(&op, addr, p_data, size); 410 if (ret != SFC_OK) 411 return ret; 412 413 ret = snor_wait_busy(10000); 414 415 return ret; 416 } 417 418 static int snor_prog(struct SFNOR_DEV *p_dev, u32 addr, void *p_data, u32 size) 419 { 420 int ret = SFC_OK; 421 u32 page_size, len; 422 u8 *p_buf = (u8 *)p_data; 423 424 page_size = NOR_PAGE_SIZE; 425 while (size) { 426 len = page_size < size ? page_size : size; 427 ret = snor_prog_page(p_dev, addr, p_buf, len); 428 if (ret != SFC_OK) 429 return ret; 430 431 size -= len; 432 addr += len; 433 p_buf += len; 434 } 435 436 return ret; 437 } 438 439 static int snor_enable_QE(struct SFNOR_DEV *p_dev) 440 { 441 int ret = SFC_OK; 442 int reg_index; 443 int bit_offset; 444 u8 status; 445 446 reg_index = p_dev->QE_bits >> 3; 447 bit_offset = p_dev->QE_bits & 0x7; 448 ret = snor_read_status(reg_index, &status); 449 if (ret != SFC_OK) 450 return ret; 451 452 if (status & (1 << bit_offset)) /* is QE bit set */ 453 return SFC_OK; 454 455 status |= (1 << bit_offset); 456 457 return p_dev->write_status(reg_index, status); 458 } 459 460 int snor_disable_QE(struct SFNOR_DEV *p_dev) 461 { 462 int ret = SFC_OK; 463 int reg_index; 464 int bit_offset; 465 u8 status; 466 467 reg_index = p_dev->QE_bits >> 3; 468 bit_offset = p_dev->QE_bits & 0x7; 469 ret = snor_read_status(reg_index, &status); 470 if (ret != SFC_OK) 471 return ret; 472 473 if (!(status & (1 << bit_offset))) 474 return SFC_OK; 475 476 status &= ~(1 << bit_offset); 477 478 return p_dev->write_status(reg_index, status); 479 } 480 481 int snor_read_data(struct SFNOR_DEV *p_dev, 482 u32 addr, 483 void *p_data, 484 u32 size) 485 { 486 int ret; 487 struct rk_sfc_op op; 488 489 op.sfcmd.d32 = 0; 490 op.sfcmd.b.cmd = p_dev->read_cmd; 491 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 492 493 op.sfctrl.d32 = 0; 494 op.sfctrl.b.datalines = p_dev->read_lines; 495 if (!(size & 0x3) && size >= 4) 496 op.sfctrl.b.enbledma = 1; 497 498 if (p_dev->read_cmd == CMD_FAST_READ_X1 || 499 p_dev->read_cmd == CMD_FAST_READ_X4 || 500 p_dev->read_cmd == CMD_FAST_READ_X2 || 501 p_dev->read_cmd == CMD_FAST_4READ_X4) { 502 op.sfcmd.b.dummybits = 8; 503 } else if (p_dev->read_cmd == CMD_FAST_READ_A4) { 504 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 505 addr = (addr << 8) | 0xFF; /* Set M[7:0] = 0xFF */ 506 op.sfcmd.b.dummybits = 4; 507 op.sfctrl.b.addrlines = SFC_4BITS_LINE; 508 } 509 510 if (p_dev->addr_mode == ADDR_MODE_4BYTE) 511 op.sfcmd.b.addrbits = SFC_ADDR_32BITS; 512 513 ret = sfc_request(&op, addr, p_data, size); 514 rkflash_print_dio("%s %x %x\n", __func__, addr, *(u32 *)(p_data)); 515 516 return ret; 517 } 518 519 int snor_read(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 520 { 521 int ret = SFC_OK; 522 u32 addr, size, len; 523 u8 *p_buf = (u8 *)p_data; 524 525 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 526 527 if ((sec + n_sec) > p_dev->capacity) 528 return SFC_PARAM_ERR; 529 530 addr = sec << 9; 531 size = n_sec << 9; 532 while (size) { 533 len = size < p_dev->max_iosize ? size : p_dev->max_iosize; 534 ret = snor_read_data(p_dev, addr, p_buf, len); 535 if (ret != SFC_OK) { 536 rkflash_print_error("snor_read_data %x ret= %x\n", 537 addr >> 9, ret); 538 goto out; 539 } 540 541 size -= len; 542 addr += len; 543 p_buf += len; 544 } 545 out: 546 if (!ret) 547 ret = n_sec; 548 549 return ret; 550 } 551 552 int snor_write(struct SFNOR_DEV *p_dev, u32 sec, u32 n_sec, void *p_data) 553 { 554 int ret = SFC_OK; 555 u32 len, blk_size, offset; 556 u8 *p_buf = (u8 *)p_data; 557 u32 total_sec = n_sec; 558 559 rkflash_print_dio("%s %x %x\n", __func__, sec, n_sec); 560 561 if ((sec + n_sec) > p_dev->capacity) 562 return SFC_PARAM_ERR; 563 564 while (n_sec) { 565 if (sec < 512 || sec >= p_dev->capacity - 512) 566 blk_size = 8; 567 else 568 blk_size = p_dev->blk_size; 569 570 offset = (sec & (blk_size - 1)); 571 if (!offset) { 572 ret = snor_erase(p_dev, sec << 9, (blk_size == 8) ? 573 ERASE_SECTOR : ERASE_BLOCK64K); 574 if (ret != SFC_OK) { 575 rkflash_print_error("snor_erase %x ret= %x\n", 576 sec, ret); 577 goto out; 578 } 579 } 580 len = (blk_size - offset) < n_sec ? 581 (blk_size - offset) : n_sec; 582 ret = snor_prog(p_dev, sec << 9, p_buf, len << 9); 583 if (ret != SFC_OK) { 584 rkflash_print_error("snor_prog %x ret= %x\n", sec, ret); 585 goto out; 586 } 587 n_sec -= len; 588 sec += len; 589 p_buf += len << 9; 590 } 591 out: 592 if (!ret) 593 ret = total_sec; 594 595 return ret; 596 } 597 598 int snor_read_id(u8 *data) 599 { 600 int ret; 601 struct rk_sfc_op op; 602 603 op.sfcmd.d32 = 0; 604 op.sfcmd.b.cmd = CMD_READ_JEDECID; 605 606 op.sfctrl.d32 = 0; 607 608 ret = sfc_request(&op, 0, data, 3); 609 610 return ret; 611 } 612 613 static int snor_read_parameter(u32 addr, u8 *data) 614 { 615 int ret; 616 struct rk_sfc_op op; 617 618 op.sfcmd.d32 = 0; 619 op.sfcmd.b.cmd = CMD_READ_PARAMETER; 620 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 621 op.sfcmd.b.dummybits = 8; 622 623 op.sfctrl.d32 = 0; 624 625 ret = sfc_request(&op, addr, data, 1); 626 627 return ret; 628 } 629 630 u32 snor_get_capacity(struct SFNOR_DEV *p_dev) 631 { 632 return p_dev->capacity; 633 } 634 635 static struct flash_info *snor_get_flash_info(u8 *flash_id) 636 { 637 u32 i; 638 u32 id = (flash_id[0] << 16) | (flash_id[1] << 8) | (flash_id[2] << 0); 639 640 for (i = 0; i < ARRAY_SIZE(spi_flash_tbl); i++) { 641 if (spi_flash_tbl[i].id == id) 642 return &spi_flash_tbl[i]; 643 } 644 return NULL; 645 } 646 647 /* Adjust flash info in ram base on parameter */ 648 static void *snor_flash_info_adjust(struct flash_info *spi_flash_info) 649 { 650 u32 addr; 651 u8 para_version; 652 653 if (spi_flash_info->id == 0xc84019) { 654 addr = 0x09; 655 snor_read_parameter(addr, ¶_version); 656 if (para_version == 0x06) { 657 spi_flash_info->QE_bits = 9; 658 spi_flash_info->prog_cmd_4 = 0x34; 659 } 660 } 661 return 0; 662 } 663 664 static int snor_parse_flash_table(struct SFNOR_DEV *p_dev, 665 struct flash_info *g_spi_flash_info) 666 { 667 int i, ret; 668 669 if (g_spi_flash_info) { 670 snor_flash_info_adjust(g_spi_flash_info); 671 p_dev->manufacturer = (g_spi_flash_info->id >> 16) & 0xFF; 672 p_dev->mem_type = (g_spi_flash_info->id >> 8) & 0xFF; 673 p_dev->capacity = 1 << g_spi_flash_info->density; 674 p_dev->blk_size = g_spi_flash_info->block_size; 675 p_dev->page_size = NOR_SECS_PAGE; 676 p_dev->read_cmd = g_spi_flash_info->read_cmd; 677 p_dev->prog_cmd = g_spi_flash_info->prog_cmd; 678 p_dev->sec_erase_cmd = g_spi_flash_info->sector_erase_cmd; 679 p_dev->blk_erase_cmd = g_spi_flash_info->block_erase_cmd; 680 p_dev->prog_lines = DATA_LINES_X1; 681 p_dev->read_lines = DATA_LINES_X1; 682 p_dev->QE_bits = g_spi_flash_info->QE_bits; 683 p_dev->addr_mode = ADDR_MODE_3BYTE; 684 685 i = g_spi_flash_info->feature & FEA_READ_STATUE_MASK; 686 if (i == 0) 687 p_dev->write_status = snor_write_status; 688 else if (i == 1) 689 p_dev->write_status = snor_write_status1; 690 else if (i == 2) 691 p_dev->write_status = snor_write_status2; 692 693 if (g_spi_flash_info->feature & FEA_4BIT_READ) { 694 ret = SFC_OK; 695 if (g_spi_flash_info->QE_bits) 696 ret = snor_enable_QE(p_dev); 697 if (ret == SFC_OK) { 698 p_dev->read_lines = DATA_LINES_X4; 699 p_dev->read_cmd = g_spi_flash_info->read_cmd_4; 700 } 701 } 702 if (g_spi_flash_info->feature & FEA_4BIT_PROG && 703 p_dev->read_lines == DATA_LINES_X4) { 704 p_dev->prog_lines = DATA_LINES_X4; 705 p_dev->prog_cmd = g_spi_flash_info->prog_cmd_4; 706 if ((p_dev->manufacturer == MID_MACRONIX) && 707 (p_dev->prog_cmd == CMD_PAGE_PROG_A4 || 708 p_dev->prog_cmd == CMD_PAGE_PROG_4PP)) 709 p_dev->prog_addr_lines = DATA_LINES_X4; 710 } 711 712 if (g_spi_flash_info->feature & FEA_4BYTE_ADDR) 713 p_dev->addr_mode = ADDR_MODE_4BYTE; 714 715 if ((g_spi_flash_info->feature & FEA_4BYTE_ADDR_MODE)) 716 snor_enter_4byte_mode(); 717 } 718 719 return SFC_OK; 720 } 721 722 int snor_init(struct SFNOR_DEV *p_dev) 723 { 724 struct flash_info *g_spi_flash_info; 725 u8 id_byte[5]; 726 727 if (!p_dev) 728 return SFC_PARAM_ERR; 729 730 memset((void *)p_dev, 0, sizeof(struct SFNOR_DEV)); 731 p_dev->max_iosize = sfc_get_max_iosize(); 732 733 snor_read_id(id_byte); 734 rkflash_print_error("sfc nor id: %x %x %x\n", 735 id_byte[0], id_byte[1], id_byte[2]); 736 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 737 return SFC_ERROR; 738 739 g_spi_flash_info = snor_get_flash_info(id_byte); 740 if (g_spi_flash_info) { 741 snor_parse_flash_table(p_dev, g_spi_flash_info); 742 } else { 743 p_dev->manufacturer = id_byte[0]; 744 p_dev->mem_type = id_byte[1]; 745 p_dev->capacity = 1 << (id_byte[2] - 9); 746 p_dev->QE_bits = 0; 747 p_dev->blk_size = NOR_SECS_BLK; 748 p_dev->page_size = NOR_SECS_PAGE; 749 p_dev->read_cmd = CMD_READ_DATA; 750 p_dev->prog_cmd = CMD_PAGE_PROG; 751 p_dev->sec_erase_cmd = CMD_SECTOR_ERASE; 752 p_dev->blk_erase_cmd = CMD_BLOCK_ERASE; 753 p_dev->prog_lines = DATA_LINES_X1; 754 p_dev->prog_addr_lines = DATA_LINES_X1; 755 p_dev->read_lines = DATA_LINES_X1; 756 p_dev->write_status = snor_write_status; 757 snor_reset_device(); 758 } 759 760 rkflash_print_info("addr_mode: %x\n", p_dev->addr_mode); 761 rkflash_print_info("read_lines: %x\n", p_dev->read_lines); 762 rkflash_print_info("prog_lines: %x\n", p_dev->prog_lines); 763 rkflash_print_info("read_cmd: %x\n", p_dev->read_cmd); 764 rkflash_print_info("prog_cmd: %x\n", p_dev->prog_cmd); 765 rkflash_print_info("blk_erase_cmd: %x\n", p_dev->blk_erase_cmd); 766 rkflash_print_info("sec_erase_cmd: %x\n", p_dev->sec_erase_cmd); 767 rkflash_print_info("capacity: %x\n", p_dev->capacity); 768 769 return SFC_OK; 770 } 771 772 int snor_reinit_from_table_packet(struct SFNOR_DEV *p_dev, 773 struct snor_info_packet *packet) 774 { 775 struct flash_info g_spi_flash_info; 776 u8 id_byte[5]; 777 int ret; 778 779 if (!p_dev || packet->id != SNOR_INFO_PACKET_ID) 780 return SFC_PARAM_ERR; 781 782 snor_read_id(id_byte); 783 if (0xFF == id_byte[0] || 0x00 == id_byte[0]) 784 return SFC_ERROR; 785 786 g_spi_flash_info.id = id_byte[0] << 16 | id_byte[1] << 8 | id_byte[2]; 787 g_spi_flash_info.block_size = NOR_SECS_BLK; 788 g_spi_flash_info.sector_size = NOR_SECS_PAGE; 789 g_spi_flash_info.read_cmd = packet->read_cmd; 790 g_spi_flash_info.prog_cmd = packet->prog_cmd; 791 g_spi_flash_info.read_cmd_4 = packet->read_cmd_4; 792 g_spi_flash_info.prog_cmd_4 = packet->prog_cmd_4; 793 if (id_byte[2] >= 0x19) 794 g_spi_flash_info.read_cmd_4 = CMD_FAST_4READ_X4; 795 g_spi_flash_info.sector_erase_cmd = packet->sector_erase_cmd; 796 g_spi_flash_info.block_erase_cmd = packet->block_erase_cmd; 797 g_spi_flash_info.feature = packet->feature; 798 g_spi_flash_info.density = id_byte[2] - 9; 799 g_spi_flash_info.QE_bits = packet->QE_bits; 800 801 ret = snor_parse_flash_table(p_dev, &g_spi_flash_info); 802 803 return ret; 804 } 805 806