1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __SFC_NAND_H 8 #define __SFC_NAND_H 9 10 #define SFC_NAND_STRESS_TEST_EN 0 11 12 #define SFC_NAND_PROG_ERASE_ERROR -2 13 #define SFC_NAND_HW_ERROR -1 14 #define SFC_NAND_ECC_ERROR NAND_ERROR 15 #define SFC_NAND_ECC_REFRESH NAND_STS_REFRESH 16 #define SFC_NAND_ECC_OK NAND_STS_OK 17 18 #define SFC_NAND_PAGE_MAX_SIZE 2112 19 20 #define FEA_READ_STATUE_MASK (0x3 << 0) 21 #define FEA_STATUE_MODE1 0 22 #define FEA_STATUE_MODE2 1 23 #define FEA_4BIT_READ BIT(2) 24 #define FEA_4BIT_PROG BIT(3) 25 #define FEA_4BYTE_ADDR BIT(4) 26 #define FEA_4BYTE_ADDR_MODE BIT(5) 27 28 #define MID_WINBOND 0xEF 29 #define MID_GIGADEV 0xC8 30 #define MID_MICRON 0x2C 31 #define MID_MACRONIX 0xC2 32 #define MID_SPANSION 0x01 33 #define MID_EON 0x1C 34 #define MID_ST 0x20 35 36 /* Command Set */ 37 #define CMD_READ_JEDECID (0x9F) 38 #define CMD_READ_DATA (0x03) 39 #define CMD_READ_STATUS (0x05) 40 #define CMD_WRITE_STATUS (0x01) 41 #define CMD_PAGE_PROG (0x02) 42 #define CMD_SECTOR_ERASE (0x20) 43 #define CMD_BLK64K_ERASE (0xD8) 44 #define CMD_BLK32K_ERASE (0x52) 45 #define CMD_CHIP_ERASE (0xC7) 46 #define CMD_WRITE_EN (0x06) 47 #define CMD_WRITE_DIS (0x04) 48 #define CMD_PAGE_READ (0x13) 49 #define CMD_GET_FEATURE (0x0F) 50 #define CMD_SET_FEATURE (0x1F) 51 #define CMD_PROG_LOAD (0x02) 52 #define CMD_PROG_EXEC (0x10) 53 #define CMD_BLOCK_ERASE (0xD8) 54 #define CMD_READ_DATA_X2 (0x3B) 55 #define CMD_READ_DATA_X4 (0x6B) 56 #define CMD_PROG_LOAD_X4 (0x32) 57 #define CMD_READ_STATUS2 (0x35) 58 #define CMD_READ_STATUS3 (0x15) 59 #define CMD_WRITE_STATUS2 (0x31) 60 #define CMD_WRITE_STATUS3 (0x11) 61 #define CMD_FAST_READ_X1 (0x0B) /* X1 cmd, X1 addr, X1 data */ 62 #define CMD_FAST_READ_X2 (0x3B) /* X1 cmd, X1 addr, X2 data */ 63 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 64 #define CMD_FAST_READ_X4 (0x6B) 65 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 66 #define CMD_FAST_4READ_X4 (0x6C) 67 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 68 #define CMD_FAST_READ_A4 (0xEB) 69 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 70 #define CMD_PAGE_PROG_X4 (0x32) 71 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 72 #define CMD_PAGE_PROG_A4 (0x38) 73 #define CMD_RESET_NAND (0xFF) 74 75 #define CMD_ENTER_4BYTE_MODE (0xB7) 76 #define CMD_EXIT_4BYTE_MODE (0xE9) 77 #define CMD_ENABLE_RESER (0x66) 78 #define CMD_RESET_DEVICE (0x99) 79 80 struct SFNAND_DEV { 81 u32 capacity; 82 u32 block_size; 83 u16 page_size; 84 u8 manufacturer; 85 u8 mem_type; 86 u8 read_lines; 87 u8 prog_lines; 88 u8 page_read_cmd; 89 u8 page_prog_cmd; 90 }; 91 92 struct nand_info { 93 u32 id; 94 95 u16 sec_per_page; 96 u16 page_per_blk; 97 u16 plane_per_die; 98 u16 blk_per_plane; 99 100 u8 page_read_cmd; 101 u8 page_prog_cmd; 102 u8 read_cache_cmd_1; 103 u8 prog_cache_cmd_1; 104 105 u8 read_cache_cmd_4; 106 u8 prog_cache_cmd_4; 107 u8 block_erase_cmd; 108 u8 feature; 109 110 u8 density; /* (1 << density) sectors*/ 111 u8 max_ecc_bits; 112 u8 QE_address; 113 u8 QE_bits; 114 115 u8 spare_offs_1; 116 u8 spare_offs_2; 117 u32 (*ecc_status)(void); 118 }; 119 120 u32 sfc_nand_init(void); 121 int sfc_nand_read_id(u8 *buf); 122 u32 sfc_nand_ecc_status_sp1(void); 123 u32 sfc_nand_ecc_status_sp3(void); 124 125 #endif 126