1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __SFC_NAND_H 8 #define __SFC_NAND_H 9 10 #include "flash_com.h" 11 12 #define SFC_NAND_WAIT_TIME_OUT 3 13 #define SFC_NAND_PROG_ERASE_ERROR 2 14 #define SFC_NAND_HW_ERROR 1 15 #define SFC_NAND_ECC_ERROR NAND_ERROR 16 #define SFC_NAND_ECC_REFRESH NAND_STS_REFRESH 17 #define SFC_NAND_ECC_OK NAND_STS_OK 18 19 #define SFC_NAND_PAGE_MAX_SIZE 4224 20 #define SFC_NAND_SECTOR_FULL_SIZE 528 21 #define SFC_NAND_SECTOR_SIZE 512 22 23 #define FEA_READ_STATUE_MASK (0x3 << 0) 24 #define FEA_STATUE_MODE1 0 25 #define FEA_STATUE_MODE2 1 26 #define FEA_4BIT_READ BIT(2) 27 #define FEA_4BIT_PROG BIT(3) 28 #define FEA_4BYTE_ADDR BIT(4) 29 #define FEA_4BYTE_ADDR_MODE BIT(5) 30 #define FEA_SOFT_QOP_BIT BIT(6) 31 32 /* Command Set */ 33 #define CMD_READ_JEDECID (0x9F) 34 #define CMD_READ_DATA (0x03) 35 #define CMD_READ_STATUS (0x05) 36 #define CMD_WRITE_STATUS (0x01) 37 #define CMD_PAGE_PROG (0x02) 38 #define CMD_SECTOR_ERASE (0x20) 39 #define CMD_BLK64K_ERASE (0xD8) 40 #define CMD_BLK32K_ERASE (0x52) 41 #define CMD_CHIP_ERASE (0xC7) 42 #define CMD_WRITE_EN (0x06) 43 #define CMD_WRITE_DIS (0x04) 44 #define CMD_PAGE_READ (0x13) 45 #define CMD_GET_FEATURE (0x0F) 46 #define CMD_SET_FEATURE (0x1F) 47 #define CMD_PROG_LOAD (0x02) 48 #define CMD_PROG_EXEC (0x10) 49 #define CMD_BLOCK_ERASE (0xD8) 50 #define CMD_READ_DATA_X2 (0x3B) 51 #define CMD_READ_DATA_X4 (0x6B) 52 #define CMD_PROG_LOAD_X4 (0x32) 53 #define CMD_READ_STATUS2 (0x35) 54 #define CMD_READ_STATUS3 (0x15) 55 #define CMD_WRITE_STATUS2 (0x31) 56 #define CMD_WRITE_STATUS3 (0x11) 57 #define CMD_FAST_READ_X1 (0x0B) /* X1 cmd, X1 addr, X1 data */ 58 #define CMD_FAST_READ_X2 (0x3B) /* X1 cmd, X1 addr, X2 data */ 59 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 60 #define CMD_FAST_READ_X4 (0x6B) 61 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 62 #define CMD_FAST_4READ_X4 (0x6C) 63 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 64 #define CMD_FAST_READ_A4 (0xEB) 65 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 66 #define CMD_PAGE_PROG_X4 (0x32) 67 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 68 #define CMD_PAGE_PROG_A4 (0x38) 69 #define CMD_RESET_NAND (0xFF) 70 71 #define CMD_ENTER_4BYTE_MODE (0xB7) 72 #define CMD_EXIT_4BYTE_MODE (0xE9) 73 #define CMD_ENABLE_RESER (0x66) 74 #define CMD_RESET_DEVICE (0x99) 75 76 struct SFNAND_DEV { 77 u32 capacity; 78 u32 block_size; 79 u16 page_size; 80 u8 manufacturer; 81 u8 mem_type; 82 u8 read_lines; 83 u8 prog_lines; 84 u8 page_read_cmd; 85 u8 page_prog_cmd; 86 }; 87 88 struct nand_mega_area { 89 u8 off0; 90 u8 off1; 91 u8 off2; 92 u8 off3; 93 }; 94 95 struct nand_info { 96 u32 id; 97 98 u16 sec_per_page; 99 u16 page_per_blk; 100 u16 plane_per_die; 101 u16 blk_per_plane; 102 103 u8 feature; 104 105 u8 density; /* (1 << density) sectors*/ 106 u8 max_ecc_bits; 107 u8 has_qe_bits; 108 109 struct nand_mega_area meta; 110 u32 (*ecc_status)(void); 111 }; 112 113 extern struct nand_phy_info g_nand_phy_info; 114 extern struct nand_ops g_nand_ops; 115 116 u32 sfc_nand_init(void); 117 void sfc_nand_deinit(void); 118 int sfc_nand_read_id(u8 *buf); 119 u32 sfc_nand_erase_block(u8 cs, u32 addr); 120 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 121 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 122 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf); 123 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf); 124 u32 sfc_nand_check_bad_block(u8 cs, u32 addr); 125 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr); 126 void sfc_nand_ftl_ops_init(void); 127 struct SFNAND_DEV *sfc_nand_get_private_dev(void); 128 129 #endif 130