1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __SFC_NAND_H 8 #define __SFC_NAND_H 9 10 #include "flash_com.h" 11 12 #define SFC_NAND_PROG_ERASE_ERROR 2 13 #define SFC_NAND_HW_ERROR 1 14 #define SFC_NAND_ECC_ERROR NAND_ERROR 15 #define SFC_NAND_ECC_REFRESH NAND_STS_REFRESH 16 #define SFC_NAND_ECC_OK NAND_STS_OK 17 18 #define SFC_NAND_PAGE_MAX_SIZE 4224 19 #define SFC_NAND_SECTOR_FULL_SIZE 528 20 #define SFC_NAND_SECTOR_SIZE 512 21 22 #define FEA_READ_STATUE_MASK (0x3 << 0) 23 #define FEA_STATUE_MODE1 0 24 #define FEA_STATUE_MODE2 1 25 #define FEA_4BIT_READ BIT(2) 26 #define FEA_4BIT_PROG BIT(3) 27 #define FEA_4BYTE_ADDR BIT(4) 28 #define FEA_4BYTE_ADDR_MODE BIT(5) 29 #define FEA_SOFT_QOP_BIT BIT(6) 30 31 /* Command Set */ 32 #define CMD_READ_JEDECID (0x9F) 33 #define CMD_READ_DATA (0x03) 34 #define CMD_READ_STATUS (0x05) 35 #define CMD_WRITE_STATUS (0x01) 36 #define CMD_PAGE_PROG (0x02) 37 #define CMD_SECTOR_ERASE (0x20) 38 #define CMD_BLK64K_ERASE (0xD8) 39 #define CMD_BLK32K_ERASE (0x52) 40 #define CMD_CHIP_ERASE (0xC7) 41 #define CMD_WRITE_EN (0x06) 42 #define CMD_WRITE_DIS (0x04) 43 #define CMD_PAGE_READ (0x13) 44 #define CMD_GET_FEATURE (0x0F) 45 #define CMD_SET_FEATURE (0x1F) 46 #define CMD_PROG_LOAD (0x02) 47 #define CMD_PROG_EXEC (0x10) 48 #define CMD_BLOCK_ERASE (0xD8) 49 #define CMD_READ_DATA_X2 (0x3B) 50 #define CMD_READ_DATA_X4 (0x6B) 51 #define CMD_PROG_LOAD_X4 (0x32) 52 #define CMD_READ_STATUS2 (0x35) 53 #define CMD_READ_STATUS3 (0x15) 54 #define CMD_WRITE_STATUS2 (0x31) 55 #define CMD_WRITE_STATUS3 (0x11) 56 #define CMD_FAST_READ_X1 (0x0B) /* X1 cmd, X1 addr, X1 data */ 57 #define CMD_FAST_READ_X2 (0x3B) /* X1 cmd, X1 addr, X2 data */ 58 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 59 #define CMD_FAST_READ_X4 (0x6B) 60 /* X1 cmd, X1 addr, X4 data SUPPORT GD MARCONIX WINBOND */ 61 #define CMD_FAST_4READ_X4 (0x6C) 62 /* X1 cmd, X4 addr, X4 data SUPPORT EON GD MARCONIX WINBOND */ 63 #define CMD_FAST_READ_A4 (0xEB) 64 /* X1 cmd, X1 addr, X4 data, SUPPORT GD WINBOND */ 65 #define CMD_PAGE_PROG_X4 (0x32) 66 /* X1 cmd, X4 addr, X4 data, SUPPORT MARCONIX */ 67 #define CMD_PAGE_PROG_A4 (0x38) 68 #define CMD_RESET_NAND (0xFF) 69 70 #define CMD_ENTER_4BYTE_MODE (0xB7) 71 #define CMD_EXIT_4BYTE_MODE (0xE9) 72 #define CMD_ENABLE_RESER (0x66) 73 #define CMD_RESET_DEVICE (0x99) 74 75 struct SFNAND_DEV { 76 u32 capacity; 77 u32 block_size; 78 u16 page_size; 79 u8 manufacturer; 80 u8 mem_type; 81 u8 read_lines; 82 u8 prog_lines; 83 u8 page_read_cmd; 84 u8 page_prog_cmd; 85 }; 86 87 struct nand_mega_area { 88 u8 off0; 89 u8 off1; 90 u8 off2; 91 u8 off3; 92 }; 93 94 struct nand_info { 95 u32 id; 96 97 u16 sec_per_page; 98 u16 page_per_blk; 99 u16 plane_per_die; 100 u16 blk_per_plane; 101 102 u8 page_read_cmd; 103 u8 page_prog_cmd; 104 u8 read_cache_cmd_1; 105 u8 prog_cache_cmd_1; 106 107 u8 read_cache_cmd_4; 108 u8 prog_cache_cmd_4; 109 u8 block_erase_cmd; 110 u8 feature; 111 112 u8 density; /* (1 << density) sectors*/ 113 u8 max_ecc_bits; 114 u8 QE_address; 115 u8 QE_bits; 116 117 struct nand_mega_area meta; 118 u32 (*ecc_status)(void); 119 }; 120 121 extern struct nand_phy_info g_nand_phy_info; 122 extern struct nand_ops g_nand_ops; 123 124 u32 sfc_nand_init(void); 125 void sfc_nand_deinit(void); 126 int sfc_nand_read_id(u8 *buf); 127 u32 sfc_nand_ecc_status_sp1(void); 128 u32 sfc_nand_ecc_status_sp2(void); 129 u32 sfc_nand_ecc_status_sp3(void); 130 u32 sfc_nand_ecc_status_sp4(void); 131 u32 sfc_nand_ecc_status_sp5(void); 132 u32 sfc_nand_erase_block(u8 cs, u32 addr); 133 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 134 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare); 135 u32 sfc_nand_check_bad_block(u8 cs, u32 addr); 136 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr); 137 void sfc_nand_ftl_ops_init(void); 138 struct SFNAND_DEV *sfc_nand_get_private_dev(void); 139 140 #endif 141