1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 static u32 sfc_nand_get_ecc_status7(void); 25 static u32 sfc_nand_get_ecc_status8(void); 26 27 static struct nand_info spi_nand_tbl[] = { 28 /* TC58CVG0S0HxAIx */ 29 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 30 /* TC58CVG1S0HxAIx */ 31 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 32 /* TC58CVG2S0HRAIJ */ 33 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 34 /* TC58CVG1S3HRAIJ */ 35 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 36 /* TC58CVG0S3HRAIJ */ 37 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 38 39 /* MX35LF1GE4AB */ 40 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 41 /* MX35LF2GE4AB */ 42 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 43 /* MX35LF2GE4AD */ 44 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 45 /* MX35LF4GE4AD */ 46 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 47 /* MX35UF1GE4AC */ 48 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 49 /* MX35UF2GE4AC */ 50 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 51 52 /* GD5F1GQ4UAYIG */ 53 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 54 /* GD5F1GQ4RB9IGR */ 55 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 56 /* GD5F2GQ40BY2GR */ 57 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 58 /* GD5F1GQ5UEYIG */ 59 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 60 /* GD5F2GQ5UEYIG */ 61 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 62 /* GD5F1GQ4R */ 63 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 64 /* GD5F4GQ6RExxG 1*4096 */ 65 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 66 /* GD5F4GQ6UExxG 1*4096 */ 67 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 68 /* GD5F1GQ4UExxH */ 69 { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 70 /* GD5F1GQ5REYIG */ 71 { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 72 /* GD5F2GQ5REYIG */ 73 { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 74 /* GD5F2GM7RxG */ 75 { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 76 /* GD5F2GM7UxG */ 77 { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 78 /* GD5F1GM7UxG */ 79 { 0xC8, 0x91, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 80 81 /* W25N01GV */ 82 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 83 /* W25N02KVZEIR */ 84 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 85 /* W25N04KVZEIR */ 86 { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 }, 87 /* W25N01GW */ 88 { 0xEF, 0xBA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 89 /* W25N02KW */ 90 { 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 91 /* W25N512GVEIG */ 92 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 93 94 /* HYF2GQ4UAACAE */ 95 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 96 /* HYF1GQ4UDACAE */ 97 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 98 /* HYF1GQ4UPACAE */ 99 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 100 /* HYF2GQ4UDACAE */ 101 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 102 /* HYF2GQ4UHCCAE */ 103 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 104 /* HYF4GQ4UAACBE */ 105 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 106 107 /* FS35ND01G-S1 */ 108 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 109 /* FS35ND02G-S2 */ 110 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 111 /* FS35ND01G-S1Y2 */ 112 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 113 /* FS35ND02G-S3Y2 */ 114 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 115 /* FS35ND04G-S2Y2 1*4096 */ 116 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 117 /* F35SQA001G */ 118 { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 119 /* F35SQA002G */ 120 { 0xCD, 0x72, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 121 122 /* DS35Q1GA-IB */ 123 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 124 /* DS35Q2GA-IB */ 125 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 126 /* DS35M1GA-1B */ 127 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 128 /* DS35M2GA-IB */ 129 { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 130 /* DS35Q2GB-IB */ 131 { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 132 /* DS35M1GB-IB */ 133 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 134 135 /* EM73C044VCC-H */ 136 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 137 /* EM73D044VCE-H */ 138 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 139 /* EM73E044SNA-G */ 140 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 141 /* EM73C044VCF-H */ 142 { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 143 144 /* XT26G02A */ 145 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 146 /* XT26G01A */ 147 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 148 /* XT26G04A */ 149 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 150 /* XT26G01B */ 151 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 152 /* XT26G02B */ 153 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 154 /* XT26G01C */ 155 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 156 /* XT26G02C */ 157 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 158 /* XT26G04C */ 159 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, 160 /* XT26G11C */ 161 { 0x0B, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 162 163 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ 164 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 165 /* MT29F1G01ABA, F50L1G41XA */ 166 { 0x2C, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 167 168 /* FM25S01 */ 169 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 170 /* FM25S01A */ 171 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 172 /* FM25S02A */ 173 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 174 /* FM25LS01 */ 175 { 0xA1, 0xA5, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 176 177 /* IS37SML01G1 */ 178 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 179 /* F50L1G41LB */ 180 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 181 /* ATO25D1GA */ 182 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 183 /* BWJX08K-2Gb */ 184 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 185 /* JS28U1GQSCAHG-83 */ 186 { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 187 /* SGM7000I-S24W1GH */ 188 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 189 /* TX25G01 */ 190 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 191 }; 192 193 static struct nand_info *p_nand_info; 194 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 195 static struct SFNAND_DEV sfc_nand_dev; 196 197 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 198 { 199 u32 i; 200 201 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 202 if (spi_nand_tbl[i].id0 == nand_id[0] && 203 spi_nand_tbl[i].id1 == nand_id[1]) { 204 if (spi_nand_tbl[i].id2 && 205 spi_nand_tbl[i].id2 != nand_id[2]) 206 continue; 207 208 return &spi_nand_tbl[i]; 209 } 210 } 211 212 return NULL; 213 } 214 215 static int sfc_nand_write_en(void) 216 { 217 int ret; 218 struct rk_sfc_op op; 219 220 op.sfcmd.d32 = 0; 221 op.sfcmd.b.cmd = CMD_WRITE_EN; 222 223 op.sfctrl.d32 = 0; 224 225 ret = sfc_request(&op, 0, NULL, 0); 226 return ret; 227 } 228 229 static int sfc_nand_rw_preset(void) 230 { 231 int ret; 232 struct rk_sfc_op op; 233 234 op.sfcmd.d32 = 0; 235 op.sfcmd.b.cmd = 0xff; 236 op.sfcmd.b.cs = 2; 237 238 op.sfctrl.d32 = 0; 239 op.sfctrl.b.datalines = 2; 240 op.sfctrl.b.cmdlines = 2; 241 op.sfctrl.b.addrlines = 2; 242 243 ret = sfc_request(&op, 0, NULL, 0); 244 return ret; 245 } 246 247 static int sfc_nand_read_feature(u8 addr, u8 *data) 248 { 249 int ret; 250 struct rk_sfc_op op; 251 252 op.sfcmd.d32 = 0; 253 op.sfcmd.b.cmd = 0x0F; 254 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 255 256 op.sfctrl.d32 = 0; 257 op.sfctrl.b.addrbits = 8; 258 259 *data = 0; 260 261 ret = sfc_request(&op, addr, data, 1); 262 263 if (ret != SFC_OK) 264 return ret; 265 266 return SFC_OK; 267 } 268 269 static int sfc_nand_write_feature(u32 addr, u8 status) 270 { 271 int ret; 272 struct rk_sfc_op op; 273 274 sfc_nand_write_en(); 275 276 op.sfcmd.d32 = 0; 277 op.sfcmd.b.cmd = 0x1F; 278 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 279 op.sfcmd.b.rw = SFC_WRITE; 280 281 op.sfctrl.d32 = 0; 282 op.sfctrl.b.addrbits = 8; 283 284 ret = sfc_request(&op, addr, &status, 1); 285 286 if (ret != SFC_OK) 287 return ret; 288 289 return ret; 290 } 291 292 static int sfc_nand_wait_busy(u8 *data, int timeout) 293 { 294 int ret; 295 int i; 296 u8 status; 297 298 *data = 0; 299 300 for (i = 0; i < timeout; i++) { 301 ret = sfc_nand_read_feature(0xC0, &status); 302 303 if (ret != SFC_OK) 304 return ret; 305 306 *data = status; 307 308 if (!(status & (1 << 0))) 309 return SFC_OK; 310 311 sfc_delay(1); 312 } 313 314 return SFC_NAND_WAIT_TIME_OUT; 315 } 316 317 /* 318 * ecc default: 319 * ecc bits: 0xC0[4,5] 320 * 0b00, No bit errors were detected 321 * 0b01, Bit errors were detected and corrected. 322 * 0b10, Multiple bit errors were detected and not corrected. 323 * 0b11, Bits errors were detected and corrected, bit error count 324 * reach the bit flip detection threshold 325 */ 326 static u32 sfc_nand_get_ecc_status0(void) 327 { 328 u32 ret; 329 u32 i; 330 u8 ecc; 331 u8 status; 332 u32 timeout = 1000 * 1000; 333 334 for (i = 0; i < timeout; i++) { 335 ret = sfc_nand_read_feature(0xC0, &status); 336 337 if (ret != SFC_OK) 338 return SFC_NAND_ECC_ERROR; 339 340 if (!(status & (1 << 0))) 341 break; 342 343 sfc_delay(1); 344 } 345 346 ecc = (status >> 4) & 0x03; 347 348 if (ecc <= 1) 349 ret = SFC_NAND_ECC_OK; 350 else if (ecc == 2) 351 ret = (u32)SFC_NAND_ECC_ERROR; 352 else 353 ret = SFC_NAND_ECC_REFRESH; 354 355 return ret; 356 } 357 358 /* 359 * ecc spectial type1: 360 * ecc bits: 0xC0[4,5] 361 * 0b00, No bit errors were detected; 362 * 0b01, Bits errors were detected and corrected, bit error count 363 * may reach the bit flip detection threshold; 364 * 0b10, Multiple bit errors were detected and not corrected; 365 * 0b11, Reserved. 366 */ 367 static u32 sfc_nand_get_ecc_status1(void) 368 { 369 u32 ret; 370 u32 i; 371 u8 ecc; 372 u8 status; 373 u32 timeout = 1000 * 1000; 374 375 for (i = 0; i < timeout; i++) { 376 ret = sfc_nand_read_feature(0xC0, &status); 377 378 if (ret != SFC_OK) 379 return SFC_NAND_ECC_ERROR; 380 381 if (!(status & (1 << 0))) 382 break; 383 384 sfc_delay(1); 385 } 386 387 ecc = (status >> 4) & 0x03; 388 389 if (ecc == 0) 390 ret = SFC_NAND_ECC_OK; 391 else if (ecc == 1) 392 ret = SFC_NAND_ECC_REFRESH; 393 else 394 ret = (u32)SFC_NAND_ECC_ERROR; 395 396 return ret; 397 } 398 399 /* 400 * ecc spectial type2: 401 * ecc bits: 0xC0[4,5] 0xF0[4,5] 402 * [0b0000, 0b0011], No bit errors were detected; 403 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 404 * reach Flipping Bits; 405 * [0b1000, 0b1011], Multiple bit errors were detected and 406 * not corrected. 407 * [0b1100, 0b1111], reserved. 408 */ 409 static u32 sfc_nand_get_ecc_status2(void) 410 { 411 u32 ret; 412 u32 i; 413 u8 ecc; 414 u8 status, status1; 415 u32 timeout = 1000 * 1000; 416 417 for (i = 0; i < timeout; i++) { 418 ret = sfc_nand_read_feature(0xC0, &status); 419 420 if (ret != SFC_OK) 421 return SFC_NAND_ECC_ERROR; 422 423 ret = sfc_nand_read_feature(0xF0, &status1); 424 425 if (ret != SFC_OK) 426 return SFC_NAND_ECC_ERROR; 427 428 if (!(status & (1 << 0))) 429 break; 430 431 sfc_delay(1); 432 } 433 434 ecc = (status >> 4) & 0x03; 435 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 436 437 if (ecc < 7) 438 ret = SFC_NAND_ECC_OK; 439 else if (ecc == 7) 440 ret = SFC_NAND_ECC_REFRESH; 441 else 442 ret = (u32)SFC_NAND_ECC_ERROR; 443 444 return ret; 445 } 446 447 /* 448 * ecc spectial type3: 449 * ecc bits: 0xC0[4,5] 0xF0[4,5] 450 * [0b0000, 0b0011], No bit errors were detected; 451 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 452 * reach Flipping Bits; 453 * [0b1000, 0b1011], Multiple bit errors were detected and 454 * not corrected. 455 * [0b1100, 0b1111], Bit error count equals the bit flip 456 * detectio nthreshold 457 */ 458 static u32 sfc_nand_get_ecc_status3(void) 459 { 460 u32 ret; 461 u32 i; 462 u8 ecc; 463 u8 status, status1; 464 u32 timeout = 1000 * 1000; 465 466 for (i = 0; i < timeout; i++) { 467 ret = sfc_nand_read_feature(0xC0, &status); 468 469 if (ret != SFC_OK) 470 return SFC_NAND_ECC_ERROR; 471 472 ret = sfc_nand_read_feature(0xF0, &status1); 473 474 if (ret != SFC_OK) 475 return SFC_NAND_ECC_ERROR; 476 477 if (!(status & (1 << 0))) 478 break; 479 480 sfc_delay(1); 481 } 482 483 ecc = (status >> 4) & 0x03; 484 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 485 486 if (ecc < 7) 487 ret = SFC_NAND_ECC_OK; 488 else if (ecc == 7 || ecc >= 12) 489 ret = SFC_NAND_ECC_REFRESH; 490 else 491 ret = (u32)SFC_NAND_ECC_ERROR; 492 493 return ret; 494 } 495 496 /* 497 * ecc spectial type4: 498 * ecc bits: 0xC0[2,5] 499 * [0b0000], No bit errors were detected; 500 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 501 * reach Flipping Bits; 502 * [0b1000], Multiple bit errors were detected and 503 * not corrected. 504 * [0b1100], Bit error count equals the bit flip 505 * detection threshold 506 * else, reserved 507 */ 508 static u32 sfc_nand_get_ecc_status4(void) 509 { 510 u32 ret; 511 u32 i; 512 u8 ecc; 513 u8 status; 514 u32 timeout = 1000 * 1000; 515 516 for (i = 0; i < timeout; i++) { 517 ret = sfc_nand_read_feature(0xC0, &status); 518 519 if (ret != SFC_OK) 520 return SFC_NAND_ECC_ERROR; 521 522 if (!(status & (1 << 0))) 523 break; 524 525 sfc_delay(1); 526 } 527 528 ecc = (status >> 2) & 0x0f; 529 530 if (ecc < 7) 531 ret = SFC_NAND_ECC_OK; 532 else if (ecc == 7 || ecc == 12) 533 ret = SFC_NAND_ECC_REFRESH; 534 else 535 ret = (u32)SFC_NAND_ECC_ERROR; 536 537 return ret; 538 } 539 540 /* 541 * ecc spectial type5: 542 * ecc bits: 0xC0[4,6] 543 * [0b000], No bit errors were detected; 544 * [0b001, 0b011], Bit errors were detected and corrected. Not 545 * reach Flipping Bits; 546 * [0b100], Bit error count equals the bit flip 547 * detection threshold 548 * [0b101, 0b110], Reserved; 549 * [0b111], Multiple bit errors were detected and 550 * not corrected. 551 */ 552 static u32 sfc_nand_get_ecc_status5(void) 553 { 554 u32 ret; 555 u32 i; 556 u8 ecc; 557 u8 status; 558 u32 timeout = 1000 * 1000; 559 560 for (i = 0; i < timeout; i++) { 561 ret = sfc_nand_read_feature(0xC0, &status); 562 563 if (ret != SFC_OK) 564 return SFC_NAND_ECC_ERROR; 565 566 if (!(status & (1 << 0))) 567 break; 568 569 sfc_delay(1); 570 } 571 572 ecc = (status >> 4) & 0x07; 573 574 if (ecc < 4) 575 ret = SFC_NAND_ECC_OK; 576 else if (ecc == 4) 577 ret = SFC_NAND_ECC_REFRESH; 578 else 579 ret = (u32)SFC_NAND_ECC_ERROR; 580 581 return ret; 582 } 583 584 /* 585 * ecc spectial type6: 586 * ecc bits: 0xC0[4,6] 587 * [0b000], No bit errors were detected; 588 * [0b001], 1-3 Bit errors were detected and corrected. Not 589 * reach Flipping Bits; 590 * [0b010], Multiple bit errors were detected and 591 * not corrected. 592 * [0b011], 4-6 Bit errors were detected and corrected. Not 593 * reach Flipping Bits; 594 * [0b101], Bit error count equals the bit flip 595 * detectionthreshold 596 * others, Reserved. 597 */ 598 static u32 sfc_nand_get_ecc_status6(void) 599 { 600 u32 ret; 601 u32 i; 602 u8 ecc; 603 u8 status; 604 u32 timeout = 1000 * 1000; 605 606 for (i = 0; i < timeout; i++) { 607 ret = sfc_nand_read_feature(0xC0, &status); 608 609 if (ret != SFC_OK) 610 return SFC_NAND_ECC_ERROR; 611 612 if (!(status & (1 << 0))) 613 break; 614 615 sfc_delay(1); 616 } 617 618 ecc = (status >> 4) & 0x07; 619 620 if (ecc == 0 || ecc == 1 || ecc == 3) 621 ret = SFC_NAND_ECC_OK; 622 else if (ecc == 5) 623 ret = SFC_NAND_ECC_REFRESH; 624 else 625 ret = (u32)SFC_NAND_ECC_ERROR; 626 627 return ret; 628 } 629 630 /* 631 * ecc spectial type7: 632 * ecc bits: 0xC0[4,7] 633 * [0b0000], No bit errors were detected; 634 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not 635 * reach Flipping Bits; 636 * [0b1000], 8 Bit errors were detected and corrected. Bit error count 637 * equals the bit flip detectionthreshold; 638 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; 639 * others, Reserved. 640 */ 641 static u32 sfc_nand_get_ecc_status7(void) 642 { 643 u32 ret; 644 u32 i; 645 u8 ecc; 646 u8 status; 647 u32 timeout = 1000 * 1000; 648 649 for (i = 0; i < timeout; i++) { 650 ret = sfc_nand_read_feature(0xC0, &status); 651 652 if (ret != SFC_OK) 653 return SFC_NAND_ECC_ERROR; 654 655 if (!(status & (1 << 0))) 656 break; 657 658 sfc_delay(1); 659 } 660 661 ecc = (status >> 4) & 0xf; 662 663 if (ecc < 7) 664 ret = SFC_NAND_ECC_OK; 665 else if (ecc == 7 || ecc == 8) 666 ret = SFC_NAND_ECC_REFRESH; 667 else 668 ret = (u32)SFC_NAND_ECC_ERROR; 669 670 return ret; 671 } 672 673 /* 674 * ecc spectial type8: 675 * ecc bits: 0xC0[4,6] 676 * [0b000], No bit errors were detected; 677 * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not 678 * reach Flipping Bits; 679 * [0b100], Bit error count equals the bit flip 680 * detection threshold 681 * others, Reserved. 682 */ 683 static u32 sfc_nand_get_ecc_status8(void) 684 { 685 u32 ret; 686 u32 i; 687 u8 ecc; 688 u8 status; 689 u32 timeout = 1000 * 1000; 690 691 for (i = 0; i < timeout; i++) { 692 ret = sfc_nand_read_feature(0xC0, &status); 693 694 if (ret != SFC_OK) 695 return SFC_NAND_ECC_ERROR; 696 697 if (!(status & (1 << 0))) 698 break; 699 700 sfc_delay(1); 701 } 702 703 ecc = (status >> 4) & 0x07; 704 705 if (ecc < 4) 706 ret = SFC_NAND_ECC_OK; 707 else if (ecc == 4) 708 ret = SFC_NAND_ECC_REFRESH; 709 else 710 ret = (u32)SFC_NAND_ECC_ERROR; 711 712 return ret; 713 } 714 715 u32 sfc_nand_erase_block(u8 cs, u32 addr) 716 { 717 int ret; 718 struct rk_sfc_op op; 719 u8 status; 720 721 rkflash_print_dio("%s %x\n", __func__, addr); 722 op.sfcmd.d32 = 0; 723 op.sfcmd.b.cmd = 0xd8; 724 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 725 op.sfcmd.b.rw = SFC_WRITE; 726 727 op.sfctrl.d32 = 0; 728 729 sfc_nand_write_en(); 730 ret = sfc_request(&op, addr, NULL, 0); 731 732 if (ret != SFC_OK) 733 return ret; 734 735 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 736 737 if (status & (1 << 2)) 738 return SFC_NAND_PROG_ERASE_ERROR; 739 740 return ret; 741 } 742 743 static u32 sfc_nand_read_cache(u32 row, u32 *p_page_buf, u32 column, u32 len) 744 { 745 int ret; 746 u32 plane; 747 struct rk_sfc_op op; 748 749 op.sfcmd.d32 = 0; 750 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 751 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 752 op.sfcmd.b.dummybits = 8; 753 754 op.sfctrl.d32 = 0; 755 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 756 op.sfctrl.b.addrbits = 16; 757 758 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 759 760 ret = sfc_request(&op, plane | column, p_page_buf, len); 761 if (ret != SFC_OK) 762 return SFC_NAND_HW_ERROR; 763 764 return ret; 765 } 766 767 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 768 { 769 int ret; 770 u32 plane; 771 struct rk_sfc_op op; 772 u8 status; 773 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 774 u32 data_area_size = SFC_NAND_SECTOR_SIZE * p_nand_info->sec_per_page; 775 776 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 777 sfc_nand_write_en(); 778 779 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 780 p_nand_info->feature & FEA_SOFT_QOP_BIT && 781 sfc_get_version() < SFC_VER_3) 782 sfc_nand_rw_preset(); 783 784 op.sfcmd.d32 = 0; 785 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 786 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 787 op.sfcmd.b.rw = SFC_WRITE; 788 789 op.sfctrl.d32 = 0; 790 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 791 op.sfctrl.b.addrbits = 16; 792 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 793 sfc_request(&op, plane, p_page_buf, page_size); 794 795 /* 796 * At the moment of power lost or dev running in harsh environment, flash 797 * maybe work in a unkonw state and result in bit flip, when this situation 798 * is detected by cache recheck, it's better to wait a second for a reliable 799 * hardware environment to avoid abnormal data written to flash array. 800 */ 801 if (p_nand_info->id0 == MID_GIGADEV) { 802 sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size); 803 if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) { 804 rkflash_print_error("%s %x cache bitflip\n", __func__, addr); 805 mdelay(1000); 806 sfc_request(&op, plane, p_page_buf, page_size); 807 } 808 } 809 810 op.sfcmd.d32 = 0; 811 op.sfcmd.b.cmd = 0x10; 812 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 813 op.sfcmd.b.rw = SFC_WRITE; 814 815 op.sfctrl.d32 = 0; 816 ret = sfc_request(&op, addr, p_page_buf, 0); 817 818 if (ret != SFC_OK) 819 return ret; 820 821 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 822 if (status & (1 << 3)) 823 return SFC_NAND_PROG_ERASE_ERROR; 824 825 return ret; 826 } 827 828 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 829 { 830 int ret; 831 u32 sec_per_page = p_nand_info->sec_per_page; 832 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 833 struct nand_mega_area *meta = &p_nand_info->meta; 834 835 memcpy(gp_page_buf, p_data, data_size); 836 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 837 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 838 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 839 840 if (sec_per_page == 8) { 841 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 842 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 843 } 844 845 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 846 847 return ret; 848 } 849 850 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 851 { 852 int ret; 853 u32 plane; 854 struct rk_sfc_op op; 855 u32 ecc_result; 856 u8 status; 857 858 op.sfcmd.d32 = 0; 859 op.sfcmd.b.cmd = 0x13; 860 op.sfcmd.b.rw = SFC_WRITE; 861 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 862 863 op.sfctrl.d32 = 0; 864 865 sfc_request(&op, row, p_page_buf, 0); 866 867 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 868 p_nand_info->feature & FEA_SOFT_QOP_BIT && 869 sfc_get_version() < SFC_VER_3) 870 sfc_nand_rw_preset(); 871 872 sfc_nand_wait_busy(&status, 1000 * 1000); 873 ecc_result = p_nand_info->ecc_status(); 874 875 op.sfcmd.d32 = 0; 876 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 877 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 878 op.sfcmd.b.dummybits = 8; 879 880 op.sfctrl.d32 = 0; 881 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 882 op.sfctrl.b.addrbits = 16; 883 884 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 885 ret = sfc_request(&op, plane | column, p_page_buf, len); 886 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 887 888 if (ret != SFC_OK) 889 return SFC_NAND_HW_ERROR; 890 891 return ecc_result; 892 } 893 894 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 895 { 896 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 897 898 return sfc_nand_read(addr, p_page_buf, 0, page_size); 899 } 900 901 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 902 { 903 u32 ret; 904 u32 sec_per_page = p_nand_info->sec_per_page; 905 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 906 struct nand_mega_area *meta = &p_nand_info->meta; 907 908 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 909 memcpy(p_data, gp_page_buf, data_size); 910 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 911 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 912 913 if (p_nand_info->sec_per_page == 8) { 914 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 915 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 916 } 917 918 if (ret == SFC_NAND_HW_ERROR) 919 ret = SFC_NAND_ECC_ERROR; 920 921 if (ret != SFC_NAND_ECC_OK) { 922 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 923 924 if (p_data) 925 rkflash_print_hex("data:", p_data, 4, 8); 926 927 if (p_spare) 928 rkflash_print_hex("spare:", p_spare, 4, 2); 929 } 930 931 return ret; 932 } 933 934 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 935 { 936 u32 ret; 937 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 938 u32 marker = 0; 939 940 ret = sfc_nand_read(addr, &marker, data_size, 2); 941 942 /* unify with mtd framework */ 943 if (ret == SFC_NAND_ECC_ERROR || (u16)marker != 0xffff) 944 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 945 __func__, addr, ret, marker); 946 947 /* Original bad block */ 948 if ((u16)marker != 0xffff) 949 return true; 950 951 return false; 952 } 953 954 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 955 { 956 u32 ret; 957 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 958 959 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 960 961 if (ret) 962 return SFC_NAND_HW_ERROR; 963 964 gp_page_buf[data_size / 4] = 0x0; 965 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 966 967 if (ret) 968 return SFC_NAND_HW_ERROR; 969 970 return ret; 971 } 972 973 int sfc_nand_read_id(u8 *data) 974 { 975 int ret; 976 struct rk_sfc_op op; 977 978 op.sfcmd.d32 = 0; 979 op.sfcmd.b.cmd = CMD_READ_JEDECID; 980 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 981 982 op.sfctrl.d32 = 0; 983 op.sfctrl.b.addrbits = 8; 984 985 ret = sfc_request(&op, 0, data, 3); 986 987 return ret; 988 } 989 990 /* 991 * Read the 1st page's 1st byte of a phy_blk 992 * If not FF, it's bad blk 993 */ 994 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 995 { 996 u32 bad_cnt, page; 997 u32 blk_per_die; 998 u16 blk; 999 1000 rkflash_print_info("%s\n", __func__); 1001 1002 bad_cnt = 0; 1003 blk_per_die = p_nand_info->plane_per_die * 1004 p_nand_info->blk_per_plane; 1005 1006 for (blk = 0; blk < blk_per_die; blk++) { 1007 page = (blk + blk_per_die * die) * 1008 p_nand_info->page_per_blk; 1009 1010 if (sfc_nand_check_bad_block(die, page)) { 1011 table[bad_cnt++] = blk; 1012 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 1013 } 1014 } 1015 1016 return (int)bad_cnt; 1017 } 1018 1019 void sfc_nand_ftl_ops_init(void) 1020 { 1021 /* para init */ 1022 g_nand_phy_info.nand_type = 1; 1023 g_nand_phy_info.die_num = 1; 1024 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 1025 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 1026 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 1027 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 1028 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 1029 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 1030 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 1031 p_nand_info->page_per_blk; 1032 g_nand_phy_info.reserved_blk = 8; 1033 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 1034 p_nand_info->blk_per_plane; 1035 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 1036 1037 /* driver register */ 1038 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 1039 g_nand_ops.erase_blk = sfc_nand_erase_block; 1040 g_nand_ops.prog_page = sfc_nand_prog_page; 1041 g_nand_ops.read_page = sfc_nand_read_page; 1042 g_nand_ops.bch_sel = NULL; 1043 } 1044 1045 static int sfc_nand_enable_QE(void) 1046 { 1047 int ret = SFC_OK; 1048 u8 status; 1049 1050 ret = sfc_nand_read_feature(0xB0, &status); 1051 1052 if (ret != SFC_OK) 1053 return ret; 1054 1055 if (status & 1) /* is QE bit set */ 1056 return SFC_OK; 1057 1058 status |= 1; 1059 1060 return sfc_nand_write_feature(0xB0, status); 1061 } 1062 1063 u32 sfc_nand_init(void) 1064 { 1065 u8 status, id_byte[8]; 1066 1067 sfc_nand_read_id(id_byte); 1068 rkflash_print_error("sfc_nand id: %x %x %x\n", 1069 id_byte[0], id_byte[1], id_byte[2]); 1070 1071 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 1072 return (u32)FTL_NO_FLASH; 1073 1074 p_nand_info = sfc_nand_get_info(id_byte); 1075 1076 if (!p_nand_info) { 1077 pr_err("The device not support yet!\n"); 1078 1079 return (u32)FTL_UNSUPPORTED_FLASH; 1080 } 1081 1082 sfc_nand_dev.manufacturer = id_byte[0]; 1083 sfc_nand_dev.mem_type = id_byte[1]; 1084 sfc_nand_dev.capacity = p_nand_info->density; 1085 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 1086 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 1087 1088 /* disable block lock */ 1089 sfc_nand_write_feature(0xA0, 0); 1090 sfc_nand_dev.read_lines = DATA_LINES_X1; 1091 sfc_nand_dev.prog_lines = DATA_LINES_X1; 1092 sfc_nand_dev.page_read_cmd = 0x03; 1093 sfc_nand_dev.page_prog_cmd = 0x02; 1094 sfc_nand_dev.recheck_buffer = ftl_malloc(SFC_NAND_PAGE_MAX_SIZE); 1095 if (!sfc_nand_dev.recheck_buffer) { 1096 rkflash_print_error("%s recheck_buffer alloc failed\n", __func__); 1097 return -1; 1098 } 1099 1100 if (p_nand_info->feature & FEA_4BIT_READ) { 1101 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 1102 !p_nand_info->has_qe_bits) { 1103 sfc_nand_dev.read_lines = DATA_LINES_X4; 1104 sfc_nand_dev.page_read_cmd = 0x6b; 1105 } 1106 } 1107 1108 if (p_nand_info->feature & FEA_4BIT_PROG && 1109 sfc_nand_dev.read_lines == DATA_LINES_X4) { 1110 sfc_nand_dev.prog_lines = DATA_LINES_X4; 1111 sfc_nand_dev.page_prog_cmd = 0x32; 1112 } 1113 1114 sfc_nand_read_feature(0xA0, &status); 1115 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 1116 sfc_nand_read_feature(0xB0, &status); 1117 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 1118 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 1119 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 1120 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 1121 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 1122 1123 return SFC_OK; 1124 } 1125 1126 void sfc_nand_deinit(void) 1127 { 1128 /* to-do */ 1129 kfree(sfc_nand_dev.recheck_buffer); 1130 } 1131 1132 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 1133 { 1134 return &sfc_nand_dev; 1135 } 1136 1137