1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static struct nand_info spi_nand_tbl[] = { 18 /* TC58CVG0S0HxAIx */ 19 {0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xB0, 0XFF, 4, 8, NULL}, 20 /* TC58CVG1S0HxAIx */ 21 {0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xB0, 0XFF, 4, 8, NULL}, 22 /* MX35LF1GE4AB */ 23 {0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 24 /* MX35LF2GE4AB */ 25 {0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 26 /* MX66L1G45G */ 27 {0x90AF, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 28 /* GD5F1GQ4UAYIG */ 29 {0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, NULL}, 30 /* MT29F1G01ZAC */ 31 {0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 32 /* GD5F2GQ40BY2GR */ 33 {0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 34 /* GD5F1GQ4U */ 35 {0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 36 /* IS37SML01G1 */ 37 {0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0XFF, 8, 12, &sfc_nand_ecc_status_sp1}, 38 /* W25N01GV */ 39 {0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0XFF, 4, 20, &sfc_nand_ecc_status_sp1}, 40 /* HYF2GQ4UAACAE */ 41 {0xC952, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 42 /* HYF2GQ4UAACAE */ 43 {0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 44 /* HYF2GQ4UDACAE */ 45 {0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, NULL}, 46 /* HYF2GQ4UHCCAE */ 47 {0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 48 /* HYF1GQ4UDACAE */ 49 {0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, NULL}, 50 /* F50L1G41LB */ 51 {0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 20, 36, NULL}, 52 /* XT26G02A */ 53 {0x0be2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 54 /* XT26G01A */ 55 {0x0be1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 56 /* FS35ND01G-S1 */ 57 {0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 16, 20, &sfc_nand_ecc_status_sp5}, 58 /* FS35ND02G-S2 */ 59 {0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, 16, 20, &sfc_nand_ecc_status_sp5}, 60 }; 61 62 static u8 id_byte[8]; 63 static struct nand_info *p_nand_info; 64 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 65 static struct SFNAND_DEV sfc_nand_dev; 66 67 static struct nand_info *spi_nand_get_info(u8 *nand_id) 68 { 69 u32 i; 70 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 71 72 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 73 if (spi_nand_tbl[i].id == id) 74 return &spi_nand_tbl[i]; 75 } 76 return NULL; 77 } 78 79 static int sfc_nand_write_en(void) 80 { 81 int ret; 82 union SFCCMD_DATA sfcmd; 83 84 sfcmd.d32 = 0; 85 sfcmd.b.cmd = CMD_WRITE_EN; 86 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 87 return ret; 88 } 89 90 static int sfc_nand_rw_preset(void) 91 { 92 int ret; 93 union SFCCTRL_DATA sfctrl; 94 union SFCCMD_DATA sfcmd; 95 u8 status = 0xFF; 96 97 sfcmd.d32 = 0; 98 sfcmd.b.cmd = 0; 99 sfcmd.b.datasize = 1; 100 sfcmd.b.rw = SFC_WRITE; 101 102 sfctrl.b.datalines = 2; 103 ret = sfc_request(sfcmd.d32, sfctrl.d32, 0, &status); 104 return ret; 105 } 106 107 static int sfc_nand_read_feature(u8 addr, u8 *data) 108 { 109 int ret; 110 union SFCCMD_DATA sfcmd; 111 112 sfcmd.d32 = 0; 113 sfcmd.b.cmd = 0x0F; 114 sfcmd.b.datasize = 1; 115 sfcmd.b.addrbits = SFC_ADDR_XBITS; 116 *data = 0; 117 118 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, data); 119 if (ret != SFC_OK) 120 return ret; 121 return SFC_OK; 122 } 123 124 static int sfc_nand_write_feature(u32 addr, u8 status) 125 { 126 int ret; 127 union SFCCMD_DATA sfcmd; 128 129 sfc_nand_write_en(); 130 131 sfcmd.d32 = 0; 132 sfcmd.b.cmd = 0x1F; 133 sfcmd.b.datasize = 1; 134 sfcmd.b.addrbits = SFC_ADDR_XBITS; 135 sfcmd.b.rw = SFC_WRITE; 136 137 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, &status); 138 if (ret != SFC_OK) 139 return ret; 140 return ret; 141 } 142 143 static int sfc_nand_wait_busy(u8 *data, int timeout) 144 { 145 int ret; 146 int i; 147 u8 status; 148 149 *data = 0; 150 for (i = 0; i < timeout; i++) { 151 ret = sfc_nand_read_feature(0xC0, &status); 152 if (ret != SFC_OK) 153 return ret; 154 *data = status; 155 if (!(status & (1 << 0))) 156 return SFC_OK; 157 sfc_delay(1); 158 } 159 return -1; 160 } 161 162 /* 163 * ecc default: 164 * 0, No bit errors were detected 165 * 1, Bit errors were detected and corrected. 166 * 2, Multiple bit errors were detected and not corrected. 167 * 3, Bits errors were detected and corrected, bit error count 168 * exceed the bit flip detection threshold 169 */ 170 static u32 sfc_nand_ecc_status(void) 171 { 172 int ret; 173 u32 i; 174 u8 ecc; 175 u8 status; 176 u32 timeout = 1000 * 1000; 177 178 for (i = 0; i < timeout; i++) { 179 ret = sfc_nand_read_feature(0xC0, &status); 180 if (ret != SFC_OK) 181 return SFC_NAND_ECC_ERROR; 182 if (!(status & (1 << 0))) 183 break; 184 sfc_delay(1); 185 } 186 187 ecc = (status >> 4) & 0x03; 188 189 if (ecc <= 1) 190 ret = SFC_NAND_ECC_OK; 191 else if (ecc == 2) 192 ret = SFC_NAND_ECC_ERROR; 193 else 194 ret = SFC_NAND_ECC_REFRESH; 195 196 return ret; 197 } 198 199 /* 200 * ecc spectial type1: 201 * 0x00, No bit errors were detected; 202 * 0x01, Bits errors were detected and corrected, bit error count 203 * may reach the bit flip detection threshold; 204 * 0x10, Multiple bit errors were detected and not corrected; 205 * 0x11, Reserved. 206 */ 207 u32 sfc_nand_ecc_status_sp1(void) 208 { 209 int ret; 210 u32 i; 211 u8 ecc; 212 u8 status; 213 u32 timeout = 1000 * 1000; 214 215 for (i = 0; i < timeout; i++) { 216 ret = sfc_nand_read_feature(0xC0, &status); 217 if (ret != SFC_OK) 218 return SFC_NAND_ECC_ERROR; 219 if (!(status & (1 << 0))) 220 break; 221 sfc_delay(1); 222 } 223 224 ecc = (status >> 4) & 0x03; 225 226 if (ecc == 0) 227 ret = SFC_NAND_ECC_OK; 228 else if (ecc == 1) 229 ret = SFC_NAND_ECC_REFRESH; 230 else 231 ret = SFC_NAND_ECC_ERROR; 232 233 return ret; 234 } 235 236 /* 237 * ecc spectial type3: 238 * [0x0000, 0x0011], No bit errors were detected; 239 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 240 * reach Flipping Bits; 241 * [0x1000, 0x1011], Multiple bit errors were detected and 242 * not corrected. 243 * [0x1100, 0x1111], Bit error count equals the bit flip 244 * detectionthreshold 245 */ 246 u32 sfc_nand_ecc_status_sp3(void) 247 { 248 int ret; 249 u32 i; 250 u8 ecc; 251 u8 status, status1; 252 u32 timeout = 1000 * 1000; 253 254 for (i = 0; i < timeout; i++) { 255 ret = sfc_nand_read_feature(0xC0, &status); 256 if (ret != SFC_OK) 257 return SFC_NAND_ECC_ERROR; 258 ret = sfc_nand_read_feature(0xF0, &status1); 259 if (ret != SFC_OK) 260 return SFC_NAND_ECC_ERROR; 261 if (!(status & (1 << 0))) 262 break; 263 sfc_delay(1); 264 } 265 266 ecc = (status >> 4) & 0x03; 267 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 268 if (ecc < 7) 269 ret = SFC_NAND_ECC_OK; 270 else if (ecc == 7 || ecc >= 12) 271 ret = SFC_NAND_ECC_REFRESH; 272 else 273 ret = SFC_NAND_ECC_ERROR; 274 275 return ret; 276 } 277 278 /* 279 * ecc spectial type4: 280 * [0x0000], No bit errors were detected; 281 * [0x0001, 0x0111], Bit errors were detected and corrected. Not 282 * reach Flipping Bits; 283 * [0x1000], Multiple bit errors were detected and 284 * not corrected. 285 * [0x1100], Bit error count equals the bit flip 286 * detectionthreshold 287 * else, reserved 288 */ 289 u32 sfc_nand_ecc_status_sp4(void) 290 { 291 int ret; 292 u32 i; 293 u8 ecc; 294 u8 status; 295 u32 timeout = 1000 * 1000; 296 297 for (i = 0; i < timeout; i++) { 298 ret = sfc_nand_read_feature(0xC0, &status); 299 if (ret != SFC_OK) 300 return SFC_NAND_ECC_ERROR; 301 if (!(status & (1 << 0))) 302 break; 303 sfc_delay(1); 304 } 305 306 ecc = (status >> 2) & 0x0f; 307 if (ecc < 7) 308 ret = SFC_NAND_ECC_OK; 309 else if (ecc == 7 || ecc == 12) 310 ret = SFC_NAND_ECC_REFRESH; 311 else 312 ret = SFC_NAND_ECC_ERROR; 313 314 return ret; 315 } 316 317 /* 318 * ecc spectial type5: 319 * [0x0], No bit errors were detected; 320 * [0x001, 0x011], Bit errors were detected and corrected. Not 321 * reach Flipping Bits; 322 * [0x100], Bit error count equals the bit flip 323 * detectionthreshold 324 * [0x101, 0x110], Reserved; 325 * [0x111], Multiple bit errors were detected and 326 * not corrected. 327 */ 328 u32 sfc_nand_ecc_status_sp5(void) 329 { 330 int ret; 331 u32 i; 332 u8 ecc; 333 u8 status; 334 u32 timeout = 1000 * 1000; 335 336 for (i = 0; i < timeout; i++) { 337 ret = sfc_nand_read_feature(0xC0, &status); 338 if (ret != SFC_OK) 339 return SFC_NAND_ECC_ERROR; 340 if (!(status & (1 << 0))) 341 break; 342 sfc_delay(1); 343 } 344 345 ecc = (status >> 4) & 0x07; 346 if (ecc < 4) 347 ret = SFC_NAND_ECC_OK; 348 else if (ecc == 4) 349 ret = SFC_NAND_ECC_REFRESH; 350 else 351 ret = SFC_NAND_ECC_ERROR; 352 353 return ret; 354 } 355 356 static u32 sfc_nand_erase_block(u8 cs, u32 addr) 357 { 358 int ret; 359 union SFCCMD_DATA sfcmd; 360 u8 status; 361 362 sfcmd.d32 = 0; 363 sfcmd.b.cmd = p_nand_info->block_erase_cmd; 364 sfcmd.b.addrbits = SFC_ADDR_24BITS; 365 sfc_nand_write_en(); 366 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 367 if (ret != SFC_OK) 368 return ret; 369 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 370 if (status & (1 << 2)) 371 return SFC_NAND_PROG_ERASE_ERROR; 372 return ret; 373 } 374 375 static u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 376 { 377 int ret; 378 union SFCCMD_DATA sfcmd; 379 union SFCCTRL_DATA sfctrl; 380 u8 status; 381 u32 data_sz = 2048; 382 u32 spare_offs_1 = p_nand_info->spare_offs_1; 383 u32 spare_offs_2 = p_nand_info->spare_offs_2; 384 385 memcpy(gp_page_buf, p_data, data_sz); 386 gp_page_buf[(data_sz + spare_offs_1) / 4] = p_spare[0]; 387 gp_page_buf[(data_sz + spare_offs_2) / 4] = p_spare[1]; 388 389 sfc_nand_write_en(); 390 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 391 p_nand_info->feature & FEA_SOFT_QOP_BIT && 392 sfc_get_version() < SFC_VER_3) 393 sfc_nand_rw_preset(); 394 395 sfcmd.d32 = 0; 396 sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 397 sfcmd.b.addrbits = SFC_ADDR_XBITS; 398 sfcmd.b.datasize = SFC_NAND_PAGE_MAX_SIZE; 399 sfcmd.b.rw = SFC_WRITE; 400 401 sfctrl.d32 = 0; 402 sfctrl.b.datalines = sfc_nand_dev.prog_lines; 403 sfctrl.b.addrbits = 16; 404 sfc_request(sfcmd.d32, sfctrl.d32, 0, gp_page_buf); 405 406 sfcmd.d32 = 0; 407 sfcmd.b.cmd = p_nand_info->page_prog_cmd; 408 sfcmd.b.addrbits = SFC_ADDR_24BITS; 409 sfcmd.b.datasize = 0; 410 sfcmd.b.rw = SFC_WRITE; 411 ret = sfc_request(sfcmd.d32, 0, addr, p_data); 412 if (ret != SFC_OK) 413 return ret; 414 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 415 if (status & (1 << 3)) 416 return SFC_NAND_PROG_ERASE_ERROR; 417 return ret; 418 } 419 420 static u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 421 { 422 int ret; 423 union SFCCMD_DATA sfcmd; 424 union SFCCTRL_DATA sfctrl; 425 u32 ecc_result; 426 u32 data_sz = 2048; 427 u32 spare_offs_1 = p_nand_info->spare_offs_1; 428 u32 spare_offs_2 = p_nand_info->spare_offs_2; 429 430 sfcmd.d32 = 0; 431 sfcmd.b.cmd = p_nand_info->page_read_cmd; 432 sfcmd.b.datasize = 0; 433 sfcmd.b.addrbits = SFC_ADDR_24BITS; 434 sfc_request(sfcmd.d32, 0, addr, p_data); 435 436 if (p_nand_info->ecc_status) 437 ecc_result = p_nand_info->ecc_status(); 438 else 439 ecc_result = sfc_nand_ecc_status(); 440 441 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 442 p_nand_info->feature & FEA_SOFT_QOP_BIT && 443 sfc_get_version() < SFC_VER_3) 444 sfc_nand_rw_preset(); 445 446 sfcmd.d32 = 0; 447 sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 448 sfcmd.b.datasize = SFC_NAND_PAGE_MAX_SIZE; 449 sfcmd.b.addrbits = SFC_ADDR_24BITS; 450 sfctrl.d32 = 0; 451 sfctrl.b.datalines = sfc_nand_dev.read_lines; 452 453 memset(gp_page_buf, 0, SFC_NAND_PAGE_MAX_SIZE); 454 ret = sfc_request(sfcmd.d32, sfctrl.d32, 0, gp_page_buf); 455 456 memcpy(p_data, gp_page_buf, data_sz); 457 p_spare[0] = gp_page_buf[(data_sz + spare_offs_1) / 4]; 458 p_spare[1] = gp_page_buf[(data_sz + spare_offs_2) / 4]; 459 if (ret != SFC_OK) 460 return SFC_NAND_ECC_ERROR; 461 462 if (ecc_result != SFC_NAND_ECC_OK) { 463 PRINT_SFC_E("%s[0x%x], ret=0x%x\n", __func__, addr, ecc_result); 464 if (p_data) 465 PRINT_SFC_HEX("data:", p_data, 4, 8); 466 if (p_spare) 467 PRINT_SFC_HEX("spare:", p_spare, 4, 2); 468 } 469 return ecc_result; 470 } 471 472 static int sfc_nand_read_id_raw(u8 *data) 473 { 474 int ret; 475 union SFCCMD_DATA sfcmd; 476 477 sfcmd.d32 = 0; 478 sfcmd.b.cmd = CMD_READ_JEDECID; 479 sfcmd.b.datasize = 3; 480 sfcmd.b.addrbits = SFC_ADDR_XBITS; 481 482 ret = sfc_request(sfcmd.d32, 0x8 << 16, 0, data); 483 484 return ret; 485 } 486 487 /* 488 * Read the 1st page's 1st byte of a phy_blk 489 * If not FF, it's bad blk 490 */ 491 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 492 { 493 u16 blk; 494 u32 bad_cnt, page; 495 u32 blk_per_die; 496 u32 *pread; 497 u32 *pspare_read; 498 499 PRINT_SFC_E("%s\n", __func__); 500 pread = ftl_malloc(2048); 501 pspare_read = ftl_malloc(8); 502 bad_cnt = 0; 503 blk_per_die = p_nand_info->plane_per_die * 504 p_nand_info->blk_per_plane; 505 for (blk = 0; blk < blk_per_die; blk++) { 506 page = (blk + blk_per_die * die) * 507 p_nand_info->page_per_blk; 508 sfc_nand_read_page(0, page, pread, pspare_read); 509 510 if (pread[0] != 0xFFFFFFFF || 511 pspare_read[0] != 0xFFFFFFFF) { 512 table[bad_cnt++] = blk; 513 PRINT_SFC_E("die[%d], bad_blk[%d]\n", die, blk); 514 } 515 } 516 ftl_free(pread); 517 ftl_free(pspare_read); 518 return (int)bad_cnt; 519 } 520 521 #if SFC_NAND_STRESS_TEST_EN 522 523 #define SFC_NAND_PAGE_SIZE 2048 524 #define SFC_NAND_SPARE_SIZE 8 525 526 static u16 bad_blk_list[1024]; 527 static u32 pwrite[SFC_NAND_PAGE_SIZE / 4]; 528 static u32 pread[SFC_NAND_PAGE_SIZE / 4]; 529 static u32 pspare_write[SFC_NAND_SPARE_SIZE / 4]; 530 static u32 pspare_read[SFC_NAND_SPARE_SIZE / 4]; 531 static u32 bad_blk_num; 532 static u32 bad_page_num; 533 534 static void sfc_nand_test(void) 535 { 536 u32 i, blk, page, bad_cnt, page_addr; 537 int ret; 538 u32 pages_num = 64; 539 u32 blk_addr = 64; 540 u32 is_bad_blk = 0; 541 542 PRINT_SFC_E("%s\n", __func__); 543 544 bad_blk_num = 0; 545 bad_page_num = 0; 546 bad_cnt = sfc_nand_get_bad_block_list(bad_blk_list, 0); 547 548 for (blk = 0; blk < 1024; blk++) { 549 for (i = 0; i < bad_cnt; i++) { 550 if (bad_blk_list[i] == blk) 551 break; 552 } 553 if (i < bad_cnt) 554 continue; 555 is_bad_blk = 0; 556 PRINT_SFC_E("Flash prog block: %x\n", blk); 557 sfc_nand_erase_block(0, blk * blk_addr); 558 for (page = 0; page < pages_num; page++) { 559 page_addr = blk * blk_addr + page; 560 for (i = 0; i < 512; i++) 561 pwrite[i] = (page_addr << 16) + i; 562 pspare_write[0] = pwrite[0] + 0x5AF0; 563 pspare_write[1] = pspare_write[0] + 1; 564 sfc_nand_prog_page(0, page_addr, pwrite, pspare_write); 565 memset(pread, 0, 2048); 566 memset(pspare_read, 0, 8); 567 ret = sfc_nand_read_page(0, page_addr, pread, 568 pspare_read); 569 if (ret != SFC_NAND_ECC_OK) 570 is_bad_blk = 1; 571 for (i = 0; i < 512; i++) { 572 if (pwrite[i] != pread[i]) { 573 is_bad_blk = 1; 574 break; 575 } 576 } 577 for (i = 0; i < 2; i++) { 578 if (pspare_write[i] != pspare_read[i]) { 579 is_bad_blk = 1; 580 break; 581 } 582 } 583 if (is_bad_blk) { 584 bad_page_num++; 585 PRINT_SFC_E("ERR:page%x, ret=%x\n", 586 page_addr, ret); 587 PRINT_SFC_HEX("data:", pread, 4, 8); 588 PRINT_SFC_HEX("spare:", pspare_read, 4, 2); 589 } 590 } 591 sfc_nand_erase_block(0, blk * blk_addr); 592 if (is_bad_blk) 593 bad_blk_num++; 594 } 595 PRINT_SFC_E("bad_blk_num = %d, bad_page_num = %d\n", 596 bad_blk_num, bad_page_num); 597 598 PRINT_SFC_E("Flash Test Finish!!!\n"); 599 while (1) 600 ; 601 } 602 #endif 603 604 static void ftl_flash_init(void) 605 { 606 /* para init */ 607 g_nand_phy_info.nand_type = 1; 608 g_nand_phy_info.die_num = 1; 609 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 610 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 611 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 612 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 613 g_nand_phy_info.byte_per_sec = 512; 614 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 615 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 616 p_nand_info->page_per_blk; 617 g_nand_phy_info.reserved_blk = 8; 618 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 619 p_nand_info->blk_per_plane; 620 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 621 622 /* driver register */ 623 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 624 g_nand_ops.erase_blk = sfc_nand_erase_block; 625 g_nand_ops.prog_page = sfc_nand_prog_page; 626 g_nand_ops.read_page = sfc_nand_read_page; 627 g_nand_ops.bch_sel = NULL; 628 } 629 630 static int spi_nand_enable_QE(void) 631 { 632 int ret = SFC_OK; 633 u8 status; 634 int bit_offset = p_nand_info->QE_bits; 635 636 if (bit_offset == 0xFF) 637 return SFC_OK; 638 639 ret = sfc_nand_read_feature(p_nand_info->QE_address, &status); 640 if (ret != SFC_OK) 641 return ret; 642 643 if (status & (1 << bit_offset)) /* is QE bit set */ 644 return SFC_OK; 645 646 status |= (1 << bit_offset); 647 return sfc_nand_write_feature(p_nand_info->QE_address, status); 648 649 return ret; 650 } 651 652 u32 sfc_nand_init(void) 653 { 654 PRINT_SFC_I("...%s enter...\n", __func__); 655 656 sfc_nand_read_id_raw(id_byte); 657 PRINT_SFC_E("sfc_nand id: %x %x %x\n", 658 id_byte[0], id_byte[1], id_byte[2]); 659 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 660 return FTL_NO_FLASH; 661 662 p_nand_info = spi_nand_get_info(id_byte); 663 if (!p_nand_info) 664 return FTL_UNSUPPORTED_FLASH; 665 666 sfc_nand_dev.manufacturer = id_byte[0]; 667 sfc_nand_dev.mem_type = id_byte[1]; 668 669 /* disable block lock */ 670 sfc_nand_write_feature(0xA0, 0); 671 sfc_nand_dev.read_lines = DATA_LINES_X1; 672 sfc_nand_dev.prog_lines = DATA_LINES_X1; 673 sfc_nand_dev.page_read_cmd = p_nand_info->read_cache_cmd_1; 674 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_1; 675 if (p_nand_info->feature & FEA_4BIT_READ) { 676 if (spi_nand_enable_QE() == SFC_OK) { 677 sfc_nand_dev.read_lines = DATA_LINES_X4; 678 sfc_nand_dev.page_read_cmd = 679 p_nand_info->read_cache_cmd_4; 680 } 681 } 682 683 if (p_nand_info->feature & FEA_4BIT_PROG && 684 sfc_nand_dev.read_lines == DATA_LINES_X4) { 685 sfc_nand_dev.prog_lines = DATA_LINES_X4; 686 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_4; 687 } 688 689 if (1) { 690 u8 status; 691 692 sfc_nand_read_feature(0xA0, &status); 693 PRINT_SFC_I("sfc_nand A0 = 0x%x\n", status); 694 sfc_nand_read_feature(0xB0, &status); 695 PRINT_SFC_I("sfc_nand B0 = 0x%x\n", status); 696 sfc_nand_read_feature(0xC0, &status); 697 PRINT_SFC_I("sfc_nand C0 = 0x%x\n", status); 698 PRINT_SFC_I("read_lines = %x\n", sfc_nand_dev.read_lines); 699 PRINT_SFC_I("prog_lines = %x\n", sfc_nand_dev.prog_lines); 700 PRINT_SFC_I("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 701 PRINT_SFC_I("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 702 } 703 ftl_flash_init(); 704 705 #if SFC_NAND_STRESS_TEST_EN 706 sfc_nand_test(); 707 #endif 708 709 return SFC_OK; 710 } 711 712 int sfc_nand_read_id(u8 *data) 713 { 714 memcpy(data, id_byte, 3); 715 return 0; 716 } 717