1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 25 static struct nand_info spi_nand_tbl[] = { 26 /* TC58CVG0S0HxAIx */ 27 { 0x98C2, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 28 /* TC58CVG1S0HxAIx */ 29 { 0x98CB, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 30 /* TC58CVG2S0HRAIJ */ 31 { 0x98ED, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 32 /* TC58CVG1S3HRAIJ */ 33 { 0x98EB, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 34 /* TC58CVG0S3HRAIJ */ 35 { 0x98E2, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 36 37 /* MX35LF1GE4AB */ 38 { 0xC212, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 39 /* MX35LF2GE4AB */ 40 { 0xC222, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 41 /* MX35LF2GE4AD */ 42 { 0xC226, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 43 /* MX35LF4GE4AD */ 44 { 0xC237, 8, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 45 /* MT29F1G01ZAC */ 46 { 0x2C12, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 47 48 /* GD5F1GQ4UAYIG */ 49 { 0xC8F1, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 50 /* GD5F1GQ4RB9IGR */ 51 { 0xC8D1, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 52 /* GD5F2GQ40BY2GR */ 53 { 0xC8D2, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 54 /* GD5F1GQ5UEYIG */ 55 { 0xC851, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 56 /* GD5F2GQ5UEYIG */ 57 { 0xC852, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 58 /* GD5F1GQ4R */ 59 { 0xC8C1, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 60 61 /* W25N01GV */ 62 { 0xEFAA, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 63 /* W25N01GW */ 64 { 0xEFBA, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 65 66 /* HYF2GQ4UAACAE */ 67 { 0xC952, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 68 /* HYF1GQ4UDACAE */ 69 { 0xC921, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 70 /* HYF1GQ4UPACAE */ 71 { 0xC9A1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 72 /* HYF2GQ4UDACAE */ 73 { 0xC922, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 74 /* HYF2GQ4UHCCAE */ 75 { 0xC95A, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 76 /* HYF4GQ4UAACBE */ 77 { 0xC9D4, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 78 79 /* FS35ND01G-S1 */ 80 { 0xCDB1, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 81 /* FS35ND02G-S2 */ 82 { 0xCDA2, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 83 /* FS35ND01G-S1Y2 */ 84 { 0xCDEA, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 85 /* FS35ND02G-S3Y2 */ 86 { 0xCDEB, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 87 /* FS35ND04G-S2Y2 1*4096 */ 88 { 0xCDEC, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 89 90 /* DS35Q1GA-IB */ 91 { 0xE571, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 92 /* DS35Q2GA-IB */ 93 { 0xE572, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 94 /* DS35M1GA-1B */ 95 { 0xE521, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 96 97 /* EM73C044VCC-H */ 98 { 0xD522, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 99 /* EM73D044VCE-H */ 100 { 0xD520, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 101 /* EM73E044SNA-G */ 102 { 0xD503, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 103 104 /* XT26G02A */ 105 { 0x0BE2, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 106 /* XT26G01A */ 107 { 0x0BE1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 108 /* XT26G04A */ 109 { 0x0BE3, 4, 0x80, 1, 2048, 0x4C, 20, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 110 /* XT26G01B */ 111 { 0x0BF1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 112 /* XT26G02B */ 113 { 0x0BF2, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 114 /* XT26G02E */ 115 { 0x2C24, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 116 117 /* IS37SML01G1 */ 118 { 0xC821, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 119 /* F50L1G41LB */ 120 { 0xC801, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 121 /* ATO25D1GA */ 122 { 0x9B12, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 123 /* FM25S01 */ 124 { 0xA1A1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 125 }; 126 127 static struct nand_info *p_nand_info; 128 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 129 static struct SFNAND_DEV sfc_nand_dev; 130 131 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 132 { 133 u32 i; 134 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 135 136 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 137 if (spi_nand_tbl[i].id == id) 138 return &spi_nand_tbl[i]; 139 } 140 141 return NULL; 142 } 143 144 static int sfc_nand_write_en(void) 145 { 146 int ret; 147 struct rk_sfc_op op; 148 149 op.sfcmd.d32 = 0; 150 op.sfcmd.b.cmd = CMD_WRITE_EN; 151 152 op.sfctrl.d32 = 0; 153 154 ret = sfc_request(&op, 0, NULL, 0); 155 return ret; 156 } 157 158 static int sfc_nand_rw_preset(void) 159 { 160 int ret; 161 struct rk_sfc_op op; 162 163 op.sfcmd.d32 = 0; 164 op.sfcmd.b.cmd = 0xff; 165 op.sfcmd.b.cs = 2; 166 167 op.sfctrl.d32 = 0; 168 op.sfctrl.b.datalines = 2; 169 op.sfctrl.b.cmdlines = 2; 170 op.sfctrl.b.addrlines = 2; 171 172 ret = sfc_request(&op, 0, NULL, 0); 173 return ret; 174 } 175 176 static int sfc_nand_read_feature(u8 addr, u8 *data) 177 { 178 int ret; 179 struct rk_sfc_op op; 180 181 op.sfcmd.d32 = 0; 182 op.sfcmd.b.cmd = 0x0F; 183 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 184 185 op.sfctrl.d32 = 0; 186 op.sfctrl.b.addrbits = 8; 187 188 *data = 0; 189 190 ret = sfc_request(&op, addr, data, 1); 191 192 if (ret != SFC_OK) 193 return ret; 194 195 return SFC_OK; 196 } 197 198 static int sfc_nand_write_feature(u32 addr, u8 status) 199 { 200 int ret; 201 struct rk_sfc_op op; 202 203 sfc_nand_write_en(); 204 205 op.sfcmd.d32 = 0; 206 op.sfcmd.b.cmd = 0x1F; 207 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 208 op.sfcmd.b.rw = SFC_WRITE; 209 210 op.sfctrl.d32 = 0; 211 op.sfctrl.b.addrbits = 8; 212 213 ret = sfc_request(&op, addr, &status, 1); 214 215 if (ret != SFC_OK) 216 return ret; 217 218 return ret; 219 } 220 221 static int sfc_nand_wait_busy(u8 *data, int timeout) 222 { 223 int ret; 224 int i; 225 u8 status; 226 227 *data = 0; 228 229 for (i = 0; i < timeout; i++) { 230 ret = sfc_nand_read_feature(0xC0, &status); 231 232 if (ret != SFC_OK) 233 return ret; 234 235 *data = status; 236 237 if (!(status & (1 << 0))) 238 return SFC_OK; 239 240 sfc_delay(1); 241 } 242 243 return SFC_NAND_WAIT_TIME_OUT; 244 } 245 246 /* 247 * ecc default: 248 * ecc bits: 0xC0[4,5] 249 * 0b00, No bit errors were detected 250 * 0b01, Bit errors were detected and corrected. 251 * 0b10, Multiple bit errors were detected and not corrected. 252 * 0b11, Bits errors were detected and corrected, bit error count 253 * exceed the bit flip detection threshold 254 */ 255 static u32 sfc_nand_get_ecc_status0(void) 256 { 257 u32 ret; 258 u32 i; 259 u8 ecc; 260 u8 status; 261 u32 timeout = 1000 * 1000; 262 263 for (i = 0; i < timeout; i++) { 264 ret = sfc_nand_read_feature(0xC0, &status); 265 266 if (ret != SFC_OK) 267 return SFC_NAND_ECC_ERROR; 268 269 if (!(status & (1 << 0))) 270 break; 271 272 sfc_delay(1); 273 } 274 275 ecc = (status >> 4) & 0x03; 276 277 if (ecc <= 1) 278 ret = SFC_NAND_ECC_OK; 279 else if (ecc == 2) 280 ret = (u32)SFC_NAND_ECC_ERROR; 281 else 282 ret = SFC_NAND_ECC_REFRESH; 283 284 return ret; 285 } 286 287 /* 288 * ecc spectial type1: 289 * ecc bits: 0xC0[4,5] 290 * 0b00, No bit errors were detected; 291 * 0b01, Bits errors were detected and corrected, bit error count 292 * may reach the bit flip detection threshold; 293 * 0b10, Multiple bit errors were detected and not corrected; 294 * 0b11, Reserved. 295 */ 296 static u32 sfc_nand_get_ecc_status1(void) 297 { 298 u32 ret; 299 u32 i; 300 u8 ecc; 301 u8 status; 302 u32 timeout = 1000 * 1000; 303 304 for (i = 0; i < timeout; i++) { 305 ret = sfc_nand_read_feature(0xC0, &status); 306 307 if (ret != SFC_OK) 308 return SFC_NAND_ECC_ERROR; 309 310 if (!(status & (1 << 0))) 311 break; 312 313 sfc_delay(1); 314 } 315 316 ecc = (status >> 4) & 0x03; 317 318 if (ecc == 0) 319 ret = SFC_NAND_ECC_OK; 320 else if (ecc == 1) 321 ret = SFC_NAND_ECC_REFRESH; 322 else 323 ret = (u32)SFC_NAND_ECC_ERROR; 324 325 return ret; 326 } 327 328 /* 329 * ecc spectial type2: 330 * ecc bits: 0xC0[4,5] 0xF0[4,5] 331 * [0b0000, 0b0011], No bit errors were detected; 332 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 333 * reach Flipping Bits; 334 * [0b1000, 0b1011], Multiple bit errors were detected and 335 * not corrected. 336 * [0b1100, 0b1111], reserved. 337 */ 338 static u32 sfc_nand_get_ecc_status2(void) 339 { 340 u32 ret; 341 u32 i; 342 u8 ecc; 343 u8 status, status1; 344 u32 timeout = 1000 * 1000; 345 346 for (i = 0; i < timeout; i++) { 347 ret = sfc_nand_read_feature(0xC0, &status); 348 349 if (ret != SFC_OK) 350 return SFC_NAND_ECC_ERROR; 351 352 ret = sfc_nand_read_feature(0xF0, &status1); 353 354 if (ret != SFC_OK) 355 return SFC_NAND_ECC_ERROR; 356 357 if (!(status & (1 << 0))) 358 break; 359 360 sfc_delay(1); 361 } 362 363 ecc = (status >> 4) & 0x03; 364 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 365 366 if (ecc < 7) 367 ret = SFC_NAND_ECC_OK; 368 else if (ecc == 7) 369 ret = SFC_NAND_ECC_REFRESH; 370 else 371 ret = (u32)SFC_NAND_ECC_ERROR; 372 373 return ret; 374 } 375 376 /* 377 * ecc spectial type3: 378 * ecc bits: 0xC0[4,5] 0xF0[4,5] 379 * [0b0000, 0b0011], No bit errors were detected; 380 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 381 * reach Flipping Bits; 382 * [0b1000, 0b1011], Multiple bit errors were detected and 383 * not corrected. 384 * [0b1100, 0b1111], Bit error count equals the bit flip 385 * detectio nthreshold 386 */ 387 static u32 sfc_nand_get_ecc_status3(void) 388 { 389 u32 ret; 390 u32 i; 391 u8 ecc; 392 u8 status, status1; 393 u32 timeout = 1000 * 1000; 394 395 for (i = 0; i < timeout; i++) { 396 ret = sfc_nand_read_feature(0xC0, &status); 397 398 if (ret != SFC_OK) 399 return SFC_NAND_ECC_ERROR; 400 401 ret = sfc_nand_read_feature(0xF0, &status1); 402 403 if (ret != SFC_OK) 404 return SFC_NAND_ECC_ERROR; 405 406 if (!(status & (1 << 0))) 407 break; 408 409 sfc_delay(1); 410 } 411 412 ecc = (status >> 4) & 0x03; 413 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 414 415 if (ecc < 7) 416 ret = SFC_NAND_ECC_OK; 417 else if (ecc == 7 || ecc >= 12) 418 ret = SFC_NAND_ECC_REFRESH; 419 else 420 ret = (u32)SFC_NAND_ECC_ERROR; 421 422 return ret; 423 } 424 425 /* 426 * ecc spectial type4: 427 * ecc bits: 0xC0[2,5] 428 * [0b0000], No bit errors were detected; 429 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 430 * reach Flipping Bits; 431 * [0b1000], Multiple bit errors were detected and 432 * not corrected. 433 * [0b1100], Bit error count equals the bit flip 434 * detectionthreshold 435 * else, reserved 436 */ 437 static u32 sfc_nand_get_ecc_status4(void) 438 { 439 u32 ret; 440 u32 i; 441 u8 ecc; 442 u8 status; 443 u32 timeout = 1000 * 1000; 444 445 for (i = 0; i < timeout; i++) { 446 ret = sfc_nand_read_feature(0xC0, &status); 447 448 if (ret != SFC_OK) 449 return SFC_NAND_ECC_ERROR; 450 451 if (!(status & (1 << 0))) 452 break; 453 454 sfc_delay(1); 455 } 456 457 ecc = (status >> 2) & 0x0f; 458 459 if (ecc < 7) 460 ret = SFC_NAND_ECC_OK; 461 else if (ecc == 7 || ecc == 12) 462 ret = SFC_NAND_ECC_REFRESH; 463 else 464 ret = (u32)SFC_NAND_ECC_ERROR; 465 466 return ret; 467 } 468 469 /* 470 * ecc spectial type5: 471 * ecc bits: 0xC0[4,6] 472 * [0b000], No bit errors were detected; 473 * [0b001, 0b011], Bit errors were detected and corrected. Not 474 * reach Flipping Bits; 475 * [0b100], Bit error count equals the bit flip 476 * detectionthreshold 477 * [0b101, 0b110], Reserved; 478 * [0b111], Multiple bit errors were detected and 479 * not corrected. 480 */ 481 static u32 sfc_nand_get_ecc_status5(void) 482 { 483 u32 ret; 484 u32 i; 485 u8 ecc; 486 u8 status; 487 u32 timeout = 1000 * 1000; 488 489 for (i = 0; i < timeout; i++) { 490 ret = sfc_nand_read_feature(0xC0, &status); 491 492 if (ret != SFC_OK) 493 return SFC_NAND_ECC_ERROR; 494 495 if (!(status & (1 << 0))) 496 break; 497 498 sfc_delay(1); 499 } 500 501 ecc = (status >> 4) & 0x07; 502 503 if (ecc < 4) 504 ret = SFC_NAND_ECC_OK; 505 else if (ecc == 4) 506 ret = SFC_NAND_ECC_REFRESH; 507 else 508 ret = (u32)SFC_NAND_ECC_ERROR; 509 510 return ret; 511 } 512 513 /* 514 * ecc spectial type6: 515 * ecc bits: 0xC0[4,6] 516 * [0b000], No bit errors were detected; 517 * [0b001], 1-3 Bit errors were detected and corrected. Not 518 * reach Flipping Bits; 519 * [0b010], Multiple bit errors were detected and 520 * not corrected. 521 * [0b011], 4-6 Bit errors were detected and corrected. Not 522 * reach Flipping Bits; 523 * [0b101], Bit error count equals the bit flip 524 * detectionthreshold 525 * others, Reserved. 526 */ 527 static u32 sfc_nand_get_ecc_status6(void) 528 { 529 u32 ret; 530 u32 i; 531 u8 ecc; 532 u8 status; 533 u32 timeout = 1000 * 1000; 534 535 for (i = 0; i < timeout; i++) { 536 ret = sfc_nand_read_feature(0xC0, &status); 537 538 if (ret != SFC_OK) 539 return SFC_NAND_ECC_ERROR; 540 541 if (!(status & (1 << 0))) 542 break; 543 544 sfc_delay(1); 545 } 546 547 ecc = (status >> 4) & 0x07; 548 549 if (ecc == 0 || ecc == 1 || ecc == 3) 550 ret = SFC_NAND_ECC_OK; 551 else if (ecc == 5) 552 ret = SFC_NAND_ECC_REFRESH; 553 else 554 ret = (u32)SFC_NAND_ECC_ERROR; 555 556 return ret; 557 } 558 559 u32 sfc_nand_erase_block(u8 cs, u32 addr) 560 { 561 int ret; 562 struct rk_sfc_op op; 563 u8 status; 564 565 rkflash_print_dio("%s %x\n", __func__, addr); 566 op.sfcmd.d32 = 0; 567 op.sfcmd.b.cmd = 0xd8; 568 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 569 op.sfcmd.b.rw = SFC_WRITE; 570 571 op.sfctrl.d32 = 0; 572 573 sfc_nand_write_en(); 574 ret = sfc_request(&op, addr, NULL, 0); 575 576 if (ret != SFC_OK) 577 return ret; 578 579 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 580 581 if (status & (1 << 2)) 582 return SFC_NAND_PROG_ERASE_ERROR; 583 584 return ret; 585 } 586 587 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 588 { 589 int ret; 590 u32 plane; 591 struct rk_sfc_op op; 592 u8 status; 593 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 594 595 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 596 sfc_nand_write_en(); 597 598 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 599 p_nand_info->feature & FEA_SOFT_QOP_BIT && 600 sfc_get_version() < SFC_VER_3) 601 sfc_nand_rw_preset(); 602 603 op.sfcmd.d32 = 0; 604 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 605 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 606 op.sfcmd.b.rw = SFC_WRITE; 607 608 op.sfctrl.d32 = 0; 609 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 610 op.sfctrl.b.addrbits = 16; 611 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 612 sfc_request(&op, plane, p_page_buf, page_size); 613 614 op.sfcmd.d32 = 0; 615 op.sfcmd.b.cmd = 0x10; 616 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 617 op.sfcmd.b.rw = SFC_WRITE; 618 619 op.sfctrl.d32 = 0; 620 ret = sfc_request(&op, addr, p_page_buf, 0); 621 622 if (ret != SFC_OK) 623 return ret; 624 625 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 626 627 if (status & (1 << 3)) 628 return SFC_NAND_PROG_ERASE_ERROR; 629 630 return ret; 631 } 632 633 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 634 { 635 int ret; 636 u32 sec_per_page = p_nand_info->sec_per_page; 637 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 638 struct nand_mega_area *meta = &p_nand_info->meta; 639 640 memcpy(gp_page_buf, p_data, data_size); 641 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 642 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 643 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 644 645 if (sec_per_page == 8) { 646 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 647 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 648 } 649 650 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 651 652 return ret; 653 } 654 655 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 656 { 657 int ret; 658 u32 plane; 659 struct rk_sfc_op op; 660 u32 ecc_result; 661 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 662 u8 status; 663 664 op.sfcmd.d32 = 0; 665 op.sfcmd.b.cmd = 0x13; 666 op.sfcmd.b.rw = SFC_WRITE; 667 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 668 669 op.sfctrl.d32 = 0; 670 671 sfc_request(&op, addr, p_page_buf, 0); 672 673 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 674 p_nand_info->feature & FEA_SOFT_QOP_BIT && 675 sfc_get_version() < SFC_VER_3) 676 sfc_nand_rw_preset(); 677 678 sfc_nand_wait_busy(&status, 1000 * 1000); 679 ecc_result = p_nand_info->ecc_status(); 680 681 op.sfcmd.d32 = 0; 682 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 683 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 684 685 op.sfctrl.d32 = 0; 686 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 687 688 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 689 ret = sfc_request(&op, plane << 8, p_page_buf, page_size); 690 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 691 692 if (ret != SFC_OK) 693 return SFC_NAND_HW_ERROR; 694 695 return ecc_result; 696 } 697 698 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 699 { 700 u32 ret; 701 u32 sec_per_page = p_nand_info->sec_per_page; 702 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 703 struct nand_mega_area *meta = &p_nand_info->meta; 704 705 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 706 memcpy(p_data, gp_page_buf, data_size); 707 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 708 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 709 710 if (p_nand_info->sec_per_page == 8) { 711 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 712 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 713 } 714 715 if (ret == SFC_NAND_HW_ERROR) 716 ret = SFC_NAND_ECC_ERROR; 717 718 if (ret != SFC_NAND_ECC_OK) { 719 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 720 721 if (p_data) 722 rkflash_print_hex("data:", p_data, 4, 8); 723 724 if (p_spare) 725 rkflash_print_hex("spare:", p_spare, 4, 2); 726 } 727 728 return ret; 729 } 730 731 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 732 { 733 u32 ret; 734 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 735 736 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 737 738 /* unify with mtd framework */ 739 if (ret == SFC_NAND_ECC_ERROR) 740 rkflash_print_error("%s page= %x ret= %x data0= %x, spare0= %x\n", 741 __func__, addr, ret, gp_page_buf[0], 742 (gp_page_buf[data_size / 4] & 0xFF)); 743 744 /* Original bad block */ 745 if ((gp_page_buf[data_size / 4] & 0xFFFF) != 0xFFFF) 746 return true; 747 748 return false; 749 } 750 751 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 752 { 753 u32 ret; 754 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 755 756 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 757 758 if (ret) 759 return SFC_NAND_HW_ERROR; 760 761 gp_page_buf[data_size / 4] = 0x0; 762 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 763 764 if (ret) 765 return SFC_NAND_HW_ERROR; 766 767 return ret; 768 } 769 770 int sfc_nand_read_id(u8 *data) 771 { 772 int ret; 773 struct rk_sfc_op op; 774 775 op.sfcmd.d32 = 0; 776 op.sfcmd.b.cmd = CMD_READ_JEDECID; 777 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 778 779 op.sfctrl.d32 = 0; 780 op.sfctrl.b.addrbits = 8; 781 782 ret = sfc_request(&op, 0, data, 3); 783 784 return ret; 785 } 786 787 /* 788 * Read the 1st page's 1st byte of a phy_blk 789 * If not FF, it's bad blk 790 */ 791 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 792 { 793 u32 bad_cnt, page; 794 u32 blk_per_die; 795 u16 blk; 796 797 rkflash_print_info("%s\n", __func__); 798 799 bad_cnt = 0; 800 blk_per_die = p_nand_info->plane_per_die * 801 p_nand_info->blk_per_plane; 802 803 for (blk = 0; blk < blk_per_die; blk++) { 804 page = (blk + blk_per_die * die) * 805 p_nand_info->page_per_blk; 806 807 if (sfc_nand_check_bad_block(die, page)) { 808 table[bad_cnt++] = blk; 809 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 810 } 811 } 812 813 return (int)bad_cnt; 814 } 815 816 void sfc_nand_ftl_ops_init(void) 817 { 818 /* para init */ 819 g_nand_phy_info.nand_type = 1; 820 g_nand_phy_info.die_num = 1; 821 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 822 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 823 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 824 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 825 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 826 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 827 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 828 p_nand_info->page_per_blk; 829 g_nand_phy_info.reserved_blk = 8; 830 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 831 p_nand_info->blk_per_plane; 832 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 833 834 /* driver register */ 835 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 836 g_nand_ops.erase_blk = sfc_nand_erase_block; 837 g_nand_ops.prog_page = sfc_nand_prog_page; 838 g_nand_ops.read_page = sfc_nand_read_page; 839 g_nand_ops.bch_sel = NULL; 840 } 841 842 static int sfc_nand_enable_QE(void) 843 { 844 int ret = SFC_OK; 845 u8 status; 846 847 ret = sfc_nand_read_feature(0xB0, &status); 848 849 if (ret != SFC_OK) 850 return ret; 851 852 if (status & 1) /* is QE bit set */ 853 return SFC_OK; 854 855 status |= 1; 856 857 return sfc_nand_write_feature(0xB0, status); 858 } 859 860 u32 sfc_nand_init(void) 861 { 862 u8 status, id_byte[8]; 863 864 sfc_nand_read_id(id_byte); 865 rkflash_print_error("sfc_nand id: %x %x %x\n", 866 id_byte[0], id_byte[1], id_byte[2]); 867 868 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 869 return (u32)FTL_NO_FLASH; 870 871 p_nand_info = sfc_nand_get_info(id_byte); 872 873 if (!p_nand_info) 874 return (u32)FTL_UNSUPPORTED_FLASH; 875 876 sfc_nand_dev.manufacturer = id_byte[0]; 877 sfc_nand_dev.mem_type = id_byte[1]; 878 sfc_nand_dev.capacity = p_nand_info->density; 879 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 880 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 881 882 /* disable block lock */ 883 sfc_nand_write_feature(0xA0, 0); 884 sfc_nand_dev.read_lines = DATA_LINES_X1; 885 sfc_nand_dev.prog_lines = DATA_LINES_X1; 886 sfc_nand_dev.page_read_cmd = 0x03; 887 sfc_nand_dev.page_prog_cmd = 0x02; 888 889 if (p_nand_info->feature & FEA_4BIT_READ) { 890 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 891 !p_nand_info->has_qe_bits) { 892 sfc_nand_dev.read_lines = DATA_LINES_X4; 893 sfc_nand_dev.page_read_cmd = 0x6b; 894 } 895 } 896 897 if (p_nand_info->feature & FEA_4BIT_PROG && 898 sfc_nand_dev.read_lines == DATA_LINES_X4) { 899 sfc_nand_dev.prog_lines = DATA_LINES_X4; 900 sfc_nand_dev.page_prog_cmd = 0x32; 901 } 902 903 sfc_nand_read_feature(0xA0, &status); 904 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 905 sfc_nand_read_feature(0xB0, &status); 906 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 907 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 908 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 909 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 910 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 911 912 return SFC_OK; 913 } 914 915 void sfc_nand_deinit(void) 916 { 917 /* to-do */ 918 } 919 920 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 921 { 922 return &sfc_nand_dev; 923 } 924 925