1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 static u32 sfc_nand_get_ecc_status7(void); 25 26 static struct nand_info spi_nand_tbl[] = { 27 /* TC58CVG0S0HxAIx */ 28 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 29 /* TC58CVG1S0HxAIx */ 30 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 31 /* TC58CVG2S0HRAIJ */ 32 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 33 /* TC58CVG1S3HRAIJ */ 34 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 35 /* TC58CVG0S3HRAIJ */ 36 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 37 38 /* MX35LF1GE4AB */ 39 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 40 /* MX35LF2GE4AB */ 41 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 42 /* MX35LF2GE4AD */ 43 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 44 /* MX35LF4GE4AD */ 45 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 46 /* MX35UF1GE4AC */ 47 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 48 /* MX35UF2GE4AC */ 49 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 50 51 /* GD5F1GQ4UAYIG */ 52 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 53 /* GD5F1GQ4RB9IGR */ 54 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 55 /* GD5F2GQ40BY2GR */ 56 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 57 /* GD5F1GQ5UEYIG */ 58 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 59 /* GD5F2GQ5UEYIG */ 60 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 61 /* GD5F1GQ4R */ 62 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 63 /* GD5F4GQ6RExxG 1*4096 */ 64 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 65 /* GD5F4GQ6UExxG 1*4096 */ 66 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 67 68 /* W25N01GV */ 69 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 70 /* W25N02KVZEIR */ 71 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 72 /* W25N01GW */ 73 { 0xEF, 0xBA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 74 75 /* HYF2GQ4UAACAE */ 76 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 77 /* HYF1GQ4UDACAE */ 78 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 79 /* HYF1GQ4UPACAE */ 80 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 81 /* HYF2GQ4UDACAE */ 82 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 83 /* HYF2GQ4UHCCAE */ 84 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 85 /* HYF4GQ4UAACBE */ 86 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 87 88 /* FS35ND01G-S1 */ 89 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 90 /* FS35ND02G-S2 */ 91 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 92 /* FS35ND01G-S1Y2 */ 93 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 94 /* FS35ND02G-S3Y2 */ 95 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 96 /* FS35ND04G-S2Y2 1*4096 */ 97 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 98 99 /* DS35Q1GA-IB */ 100 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 101 /* DS35Q2GA-IB */ 102 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 103 /* DS35M1GA-1B */ 104 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 105 106 /* EM73C044VCC-H */ 107 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 108 /* EM73D044VCE-H */ 109 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 110 /* EM73E044SNA-G */ 111 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 112 113 /* XT26G02A */ 114 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 115 /* XT26G01A */ 116 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 117 /* XT26G04A */ 118 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 119 /* XT26G01B */ 120 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 121 /* XT26G02B */ 122 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 123 /* XT26G01C */ 124 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 125 /* XT26G02C */ 126 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 127 /* XT26G04C */ 128 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, 129 130 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ 131 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 132 133 /* FM25S01 */ 134 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 135 /* FM25S01A */ 136 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 137 /* FM25S02A */ 138 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 139 140 /* IS37SML01G1 */ 141 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 142 /* F50L1G41LB */ 143 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 144 /* ATO25D1GA */ 145 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 146 /* BWJX08K-2Gb */ 147 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 148 }; 149 150 static struct nand_info *p_nand_info; 151 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 152 static struct SFNAND_DEV sfc_nand_dev; 153 154 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 155 { 156 u32 i; 157 158 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 159 if (spi_nand_tbl[i].id0 == nand_id[0] && 160 spi_nand_tbl[i].id1 == nand_id[1]) { 161 if (spi_nand_tbl[i].id2 && 162 spi_nand_tbl[i].id2 != nand_id[2]) 163 continue; 164 165 return &spi_nand_tbl[i]; 166 } 167 } 168 169 return NULL; 170 } 171 172 static int sfc_nand_write_en(void) 173 { 174 int ret; 175 struct rk_sfc_op op; 176 177 op.sfcmd.d32 = 0; 178 op.sfcmd.b.cmd = CMD_WRITE_EN; 179 180 op.sfctrl.d32 = 0; 181 182 ret = sfc_request(&op, 0, NULL, 0); 183 return ret; 184 } 185 186 static int sfc_nand_rw_preset(void) 187 { 188 int ret; 189 struct rk_sfc_op op; 190 191 op.sfcmd.d32 = 0; 192 op.sfcmd.b.cmd = 0xff; 193 op.sfcmd.b.cs = 2; 194 195 op.sfctrl.d32 = 0; 196 op.sfctrl.b.datalines = 2; 197 op.sfctrl.b.cmdlines = 2; 198 op.sfctrl.b.addrlines = 2; 199 200 ret = sfc_request(&op, 0, NULL, 0); 201 return ret; 202 } 203 204 static int sfc_nand_read_feature(u8 addr, u8 *data) 205 { 206 int ret; 207 struct rk_sfc_op op; 208 209 op.sfcmd.d32 = 0; 210 op.sfcmd.b.cmd = 0x0F; 211 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 212 213 op.sfctrl.d32 = 0; 214 op.sfctrl.b.addrbits = 8; 215 216 *data = 0; 217 218 ret = sfc_request(&op, addr, data, 1); 219 220 if (ret != SFC_OK) 221 return ret; 222 223 return SFC_OK; 224 } 225 226 static int sfc_nand_write_feature(u32 addr, u8 status) 227 { 228 int ret; 229 struct rk_sfc_op op; 230 231 sfc_nand_write_en(); 232 233 op.sfcmd.d32 = 0; 234 op.sfcmd.b.cmd = 0x1F; 235 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 236 op.sfcmd.b.rw = SFC_WRITE; 237 238 op.sfctrl.d32 = 0; 239 op.sfctrl.b.addrbits = 8; 240 241 ret = sfc_request(&op, addr, &status, 1); 242 243 if (ret != SFC_OK) 244 return ret; 245 246 return ret; 247 } 248 249 static int sfc_nand_wait_busy(u8 *data, int timeout) 250 { 251 int ret; 252 int i; 253 u8 status; 254 255 *data = 0; 256 257 for (i = 0; i < timeout; i++) { 258 ret = sfc_nand_read_feature(0xC0, &status); 259 260 if (ret != SFC_OK) 261 return ret; 262 263 *data = status; 264 265 if (!(status & (1 << 0))) 266 return SFC_OK; 267 268 sfc_delay(1); 269 } 270 271 return SFC_NAND_WAIT_TIME_OUT; 272 } 273 274 /* 275 * ecc default: 276 * ecc bits: 0xC0[4,5] 277 * 0b00, No bit errors were detected 278 * 0b01, Bit errors were detected and corrected. 279 * 0b10, Multiple bit errors were detected and not corrected. 280 * 0b11, Bits errors were detected and corrected, bit error count 281 * reach the bit flip detection threshold 282 */ 283 static u32 sfc_nand_get_ecc_status0(void) 284 { 285 u32 ret; 286 u32 i; 287 u8 ecc; 288 u8 status; 289 u32 timeout = 1000 * 1000; 290 291 for (i = 0; i < timeout; i++) { 292 ret = sfc_nand_read_feature(0xC0, &status); 293 294 if (ret != SFC_OK) 295 return SFC_NAND_ECC_ERROR; 296 297 if (!(status & (1 << 0))) 298 break; 299 300 sfc_delay(1); 301 } 302 303 ecc = (status >> 4) & 0x03; 304 305 if (ecc <= 1) 306 ret = SFC_NAND_ECC_OK; 307 else if (ecc == 2) 308 ret = (u32)SFC_NAND_ECC_ERROR; 309 else 310 ret = SFC_NAND_ECC_REFRESH; 311 312 return ret; 313 } 314 315 /* 316 * ecc spectial type1: 317 * ecc bits: 0xC0[4,5] 318 * 0b00, No bit errors were detected; 319 * 0b01, Bits errors were detected and corrected, bit error count 320 * may reach the bit flip detection threshold; 321 * 0b10, Multiple bit errors were detected and not corrected; 322 * 0b11, Reserved. 323 */ 324 static u32 sfc_nand_get_ecc_status1(void) 325 { 326 u32 ret; 327 u32 i; 328 u8 ecc; 329 u8 status; 330 u32 timeout = 1000 * 1000; 331 332 for (i = 0; i < timeout; i++) { 333 ret = sfc_nand_read_feature(0xC0, &status); 334 335 if (ret != SFC_OK) 336 return SFC_NAND_ECC_ERROR; 337 338 if (!(status & (1 << 0))) 339 break; 340 341 sfc_delay(1); 342 } 343 344 ecc = (status >> 4) & 0x03; 345 346 if (ecc == 0) 347 ret = SFC_NAND_ECC_OK; 348 else if (ecc == 1) 349 ret = SFC_NAND_ECC_REFRESH; 350 else 351 ret = (u32)SFC_NAND_ECC_ERROR; 352 353 return ret; 354 } 355 356 /* 357 * ecc spectial type2: 358 * ecc bits: 0xC0[4,5] 0xF0[4,5] 359 * [0b0000, 0b0011], No bit errors were detected; 360 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 361 * reach Flipping Bits; 362 * [0b1000, 0b1011], Multiple bit errors were detected and 363 * not corrected. 364 * [0b1100, 0b1111], reserved. 365 */ 366 static u32 sfc_nand_get_ecc_status2(void) 367 { 368 u32 ret; 369 u32 i; 370 u8 ecc; 371 u8 status, status1; 372 u32 timeout = 1000 * 1000; 373 374 for (i = 0; i < timeout; i++) { 375 ret = sfc_nand_read_feature(0xC0, &status); 376 377 if (ret != SFC_OK) 378 return SFC_NAND_ECC_ERROR; 379 380 ret = sfc_nand_read_feature(0xF0, &status1); 381 382 if (ret != SFC_OK) 383 return SFC_NAND_ECC_ERROR; 384 385 if (!(status & (1 << 0))) 386 break; 387 388 sfc_delay(1); 389 } 390 391 ecc = (status >> 4) & 0x03; 392 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 393 394 if (ecc < 7) 395 ret = SFC_NAND_ECC_OK; 396 else if (ecc == 7) 397 ret = SFC_NAND_ECC_REFRESH; 398 else 399 ret = (u32)SFC_NAND_ECC_ERROR; 400 401 return ret; 402 } 403 404 /* 405 * ecc spectial type3: 406 * ecc bits: 0xC0[4,5] 0xF0[4,5] 407 * [0b0000, 0b0011], No bit errors were detected; 408 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 409 * reach Flipping Bits; 410 * [0b1000, 0b1011], Multiple bit errors were detected and 411 * not corrected. 412 * [0b1100, 0b1111], Bit error count equals the bit flip 413 * detectio nthreshold 414 */ 415 static u32 sfc_nand_get_ecc_status3(void) 416 { 417 u32 ret; 418 u32 i; 419 u8 ecc; 420 u8 status, status1; 421 u32 timeout = 1000 * 1000; 422 423 for (i = 0; i < timeout; i++) { 424 ret = sfc_nand_read_feature(0xC0, &status); 425 426 if (ret != SFC_OK) 427 return SFC_NAND_ECC_ERROR; 428 429 ret = sfc_nand_read_feature(0xF0, &status1); 430 431 if (ret != SFC_OK) 432 return SFC_NAND_ECC_ERROR; 433 434 if (!(status & (1 << 0))) 435 break; 436 437 sfc_delay(1); 438 } 439 440 ecc = (status >> 4) & 0x03; 441 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 442 443 if (ecc < 7) 444 ret = SFC_NAND_ECC_OK; 445 else if (ecc == 7 || ecc >= 12) 446 ret = SFC_NAND_ECC_REFRESH; 447 else 448 ret = (u32)SFC_NAND_ECC_ERROR; 449 450 return ret; 451 } 452 453 /* 454 * ecc spectial type4: 455 * ecc bits: 0xC0[2,5] 456 * [0b0000], No bit errors were detected; 457 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 458 * reach Flipping Bits; 459 * [0b1000], Multiple bit errors were detected and 460 * not corrected. 461 * [0b1100], Bit error count equals the bit flip 462 * detectionthreshold 463 * else, reserved 464 */ 465 static u32 sfc_nand_get_ecc_status4(void) 466 { 467 u32 ret; 468 u32 i; 469 u8 ecc; 470 u8 status; 471 u32 timeout = 1000 * 1000; 472 473 for (i = 0; i < timeout; i++) { 474 ret = sfc_nand_read_feature(0xC0, &status); 475 476 if (ret != SFC_OK) 477 return SFC_NAND_ECC_ERROR; 478 479 if (!(status & (1 << 0))) 480 break; 481 482 sfc_delay(1); 483 } 484 485 ecc = (status >> 2) & 0x0f; 486 487 if (ecc < 7) 488 ret = SFC_NAND_ECC_OK; 489 else if (ecc == 7 || ecc == 12) 490 ret = SFC_NAND_ECC_REFRESH; 491 else 492 ret = (u32)SFC_NAND_ECC_ERROR; 493 494 return ret; 495 } 496 497 /* 498 * ecc spectial type5: 499 * ecc bits: 0xC0[4,6] 500 * [0b000], No bit errors were detected; 501 * [0b001, 0b011], Bit errors were detected and corrected. Not 502 * reach Flipping Bits; 503 * [0b100], Bit error count equals the bit flip 504 * detectionthreshold 505 * [0b101, 0b110], Reserved; 506 * [0b111], Multiple bit errors were detected and 507 * not corrected. 508 */ 509 static u32 sfc_nand_get_ecc_status5(void) 510 { 511 u32 ret; 512 u32 i; 513 u8 ecc; 514 u8 status; 515 u32 timeout = 1000 * 1000; 516 517 for (i = 0; i < timeout; i++) { 518 ret = sfc_nand_read_feature(0xC0, &status); 519 520 if (ret != SFC_OK) 521 return SFC_NAND_ECC_ERROR; 522 523 if (!(status & (1 << 0))) 524 break; 525 526 sfc_delay(1); 527 } 528 529 ecc = (status >> 4) & 0x07; 530 531 if (ecc < 4) 532 ret = SFC_NAND_ECC_OK; 533 else if (ecc == 4) 534 ret = SFC_NAND_ECC_REFRESH; 535 else 536 ret = (u32)SFC_NAND_ECC_ERROR; 537 538 return ret; 539 } 540 541 /* 542 * ecc spectial type6: 543 * ecc bits: 0xC0[4,6] 544 * [0b000], No bit errors were detected; 545 * [0b001], 1-3 Bit errors were detected and corrected. Not 546 * reach Flipping Bits; 547 * [0b010], Multiple bit errors were detected and 548 * not corrected. 549 * [0b011], 4-6 Bit errors were detected and corrected. Not 550 * reach Flipping Bits; 551 * [0b101], Bit error count equals the bit flip 552 * detectionthreshold 553 * others, Reserved. 554 */ 555 static u32 sfc_nand_get_ecc_status6(void) 556 { 557 u32 ret; 558 u32 i; 559 u8 ecc; 560 u8 status; 561 u32 timeout = 1000 * 1000; 562 563 for (i = 0; i < timeout; i++) { 564 ret = sfc_nand_read_feature(0xC0, &status); 565 566 if (ret != SFC_OK) 567 return SFC_NAND_ECC_ERROR; 568 569 if (!(status & (1 << 0))) 570 break; 571 572 sfc_delay(1); 573 } 574 575 ecc = (status >> 4) & 0x07; 576 577 if (ecc == 0 || ecc == 1 || ecc == 3) 578 ret = SFC_NAND_ECC_OK; 579 else if (ecc == 5) 580 ret = SFC_NAND_ECC_REFRESH; 581 else 582 ret = (u32)SFC_NAND_ECC_ERROR; 583 584 return ret; 585 } 586 587 /* 588 * ecc spectial type7: 589 * ecc bits: 0xC0[4,7] 590 * [0b0000], No bit errors were detected; 591 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not 592 * reach Flipping Bits; 593 * [0b1000], 8 Bit errors were detected and corrected. Bit error count 594 * equals the bit flip detectionthreshold; 595 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; 596 * others, Reserved. 597 */ 598 static u32 sfc_nand_get_ecc_status7(void) 599 { 600 u32 ret; 601 u32 i; 602 u8 ecc; 603 u8 status; 604 u32 timeout = 1000 * 1000; 605 606 for (i = 0; i < timeout; i++) { 607 ret = sfc_nand_read_feature(0xC0, &status); 608 609 if (ret != SFC_OK) 610 return SFC_NAND_ECC_ERROR; 611 612 if (!(status & (1 << 0))) 613 break; 614 615 sfc_delay(1); 616 } 617 618 ecc = (status >> 4) & 0xf; 619 620 if (ecc < 7) 621 ret = SFC_NAND_ECC_OK; 622 else if (ecc == 7 || ecc == 8) 623 ret = SFC_NAND_ECC_REFRESH; 624 else 625 ret = (u32)SFC_NAND_ECC_ERROR; 626 627 return ret; 628 } 629 630 u32 sfc_nand_erase_block(u8 cs, u32 addr) 631 { 632 int ret; 633 struct rk_sfc_op op; 634 u8 status; 635 636 rkflash_print_dio("%s %x\n", __func__, addr); 637 op.sfcmd.d32 = 0; 638 op.sfcmd.b.cmd = 0xd8; 639 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 640 op.sfcmd.b.rw = SFC_WRITE; 641 642 op.sfctrl.d32 = 0; 643 644 sfc_nand_write_en(); 645 ret = sfc_request(&op, addr, NULL, 0); 646 647 if (ret != SFC_OK) 648 return ret; 649 650 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 651 652 if (status & (1 << 2)) 653 return SFC_NAND_PROG_ERASE_ERROR; 654 655 return ret; 656 } 657 658 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 659 { 660 int ret; 661 u32 plane; 662 struct rk_sfc_op op; 663 u8 status; 664 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 665 666 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 667 sfc_nand_write_en(); 668 669 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 670 p_nand_info->feature & FEA_SOFT_QOP_BIT && 671 sfc_get_version() < SFC_VER_3) 672 sfc_nand_rw_preset(); 673 674 op.sfcmd.d32 = 0; 675 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 676 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 677 op.sfcmd.b.rw = SFC_WRITE; 678 679 op.sfctrl.d32 = 0; 680 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 681 op.sfctrl.b.addrbits = 16; 682 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 683 sfc_request(&op, plane, p_page_buf, page_size); 684 685 op.sfcmd.d32 = 0; 686 op.sfcmd.b.cmd = 0x10; 687 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 688 op.sfcmd.b.rw = SFC_WRITE; 689 690 op.sfctrl.d32 = 0; 691 ret = sfc_request(&op, addr, p_page_buf, 0); 692 693 if (ret != SFC_OK) 694 return ret; 695 696 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 697 698 if (status & (1 << 3)) 699 return SFC_NAND_PROG_ERASE_ERROR; 700 701 return ret; 702 } 703 704 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 705 { 706 int ret; 707 u32 sec_per_page = p_nand_info->sec_per_page; 708 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 709 struct nand_mega_area *meta = &p_nand_info->meta; 710 711 memcpy(gp_page_buf, p_data, data_size); 712 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 713 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 714 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 715 716 if (sec_per_page == 8) { 717 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 718 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 719 } 720 721 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 722 723 return ret; 724 } 725 726 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 727 { 728 int ret; 729 u32 plane; 730 struct rk_sfc_op op; 731 u32 ecc_result; 732 u8 status; 733 734 op.sfcmd.d32 = 0; 735 op.sfcmd.b.cmd = 0x13; 736 op.sfcmd.b.rw = SFC_WRITE; 737 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 738 739 op.sfctrl.d32 = 0; 740 741 sfc_request(&op, row, p_page_buf, 0); 742 743 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 744 p_nand_info->feature & FEA_SOFT_QOP_BIT && 745 sfc_get_version() < SFC_VER_3) 746 sfc_nand_rw_preset(); 747 748 sfc_nand_wait_busy(&status, 1000 * 1000); 749 ecc_result = p_nand_info->ecc_status(); 750 751 op.sfcmd.d32 = 0; 752 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 753 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 754 op.sfcmd.b.dummybits = 8; 755 756 op.sfctrl.d32 = 0; 757 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 758 op.sfctrl.b.addrbits = 16; 759 760 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 761 ret = sfc_request(&op, plane | column, p_page_buf, len); 762 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 763 764 if (ret != SFC_OK) 765 return SFC_NAND_HW_ERROR; 766 767 return ecc_result; 768 } 769 770 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 771 { 772 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 773 774 return sfc_nand_read(addr, p_page_buf, 0, page_size); 775 } 776 777 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 778 { 779 u32 ret; 780 u32 sec_per_page = p_nand_info->sec_per_page; 781 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 782 struct nand_mega_area *meta = &p_nand_info->meta; 783 784 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 785 memcpy(p_data, gp_page_buf, data_size); 786 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 787 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 788 789 if (p_nand_info->sec_per_page == 8) { 790 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 791 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 792 } 793 794 if (ret == SFC_NAND_HW_ERROR) 795 ret = SFC_NAND_ECC_ERROR; 796 797 if (ret != SFC_NAND_ECC_OK) { 798 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 799 800 if (p_data) 801 rkflash_print_hex("data:", p_data, 4, 8); 802 803 if (p_spare) 804 rkflash_print_hex("spare:", p_spare, 4, 2); 805 } 806 807 return ret; 808 } 809 810 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 811 { 812 u32 ret; 813 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 814 u32 marker = 0; 815 816 ret = sfc_nand_read(addr, &marker, data_size, 2); 817 818 /* unify with mtd framework */ 819 if (ret == SFC_NAND_ECC_ERROR) 820 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 821 __func__, addr, ret, marker); 822 823 /* Original bad block */ 824 if ((u16)marker != 0xffff) 825 return true; 826 827 return false; 828 } 829 830 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 831 { 832 u32 ret; 833 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 834 835 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 836 837 if (ret) 838 return SFC_NAND_HW_ERROR; 839 840 gp_page_buf[data_size / 4] = 0x0; 841 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 842 843 if (ret) 844 return SFC_NAND_HW_ERROR; 845 846 return ret; 847 } 848 849 int sfc_nand_read_id(u8 *data) 850 { 851 int ret; 852 struct rk_sfc_op op; 853 854 op.sfcmd.d32 = 0; 855 op.sfcmd.b.cmd = CMD_READ_JEDECID; 856 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 857 858 op.sfctrl.d32 = 0; 859 op.sfctrl.b.addrbits = 8; 860 861 ret = sfc_request(&op, 0, data, 3); 862 863 return ret; 864 } 865 866 /* 867 * Read the 1st page's 1st byte of a phy_blk 868 * If not FF, it's bad blk 869 */ 870 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 871 { 872 u32 bad_cnt, page; 873 u32 blk_per_die; 874 u16 blk; 875 876 rkflash_print_info("%s\n", __func__); 877 878 bad_cnt = 0; 879 blk_per_die = p_nand_info->plane_per_die * 880 p_nand_info->blk_per_plane; 881 882 for (blk = 0; blk < blk_per_die; blk++) { 883 page = (blk + blk_per_die * die) * 884 p_nand_info->page_per_blk; 885 886 if (sfc_nand_check_bad_block(die, page)) { 887 table[bad_cnt++] = blk; 888 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 889 } 890 } 891 892 return (int)bad_cnt; 893 } 894 895 void sfc_nand_ftl_ops_init(void) 896 { 897 /* para init */ 898 g_nand_phy_info.nand_type = 1; 899 g_nand_phy_info.die_num = 1; 900 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 901 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 902 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 903 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 904 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 905 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 906 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 907 p_nand_info->page_per_blk; 908 g_nand_phy_info.reserved_blk = 8; 909 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 910 p_nand_info->blk_per_plane; 911 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 912 913 /* driver register */ 914 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 915 g_nand_ops.erase_blk = sfc_nand_erase_block; 916 g_nand_ops.prog_page = sfc_nand_prog_page; 917 g_nand_ops.read_page = sfc_nand_read_page; 918 g_nand_ops.bch_sel = NULL; 919 } 920 921 static int sfc_nand_enable_QE(void) 922 { 923 int ret = SFC_OK; 924 u8 status; 925 926 ret = sfc_nand_read_feature(0xB0, &status); 927 928 if (ret != SFC_OK) 929 return ret; 930 931 if (status & 1) /* is QE bit set */ 932 return SFC_OK; 933 934 status |= 1; 935 936 return sfc_nand_write_feature(0xB0, status); 937 } 938 939 u32 sfc_nand_init(void) 940 { 941 u8 status, id_byte[8]; 942 943 sfc_nand_read_id(id_byte); 944 rkflash_print_error("sfc_nand id: %x %x %x\n", 945 id_byte[0], id_byte[1], id_byte[2]); 946 947 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 948 return (u32)FTL_NO_FLASH; 949 950 p_nand_info = sfc_nand_get_info(id_byte); 951 952 if (!p_nand_info) 953 return (u32)FTL_UNSUPPORTED_FLASH; 954 955 sfc_nand_dev.manufacturer = id_byte[0]; 956 sfc_nand_dev.mem_type = id_byte[1]; 957 sfc_nand_dev.capacity = p_nand_info->density; 958 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 959 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 960 961 /* disable block lock */ 962 sfc_nand_write_feature(0xA0, 0); 963 sfc_nand_dev.read_lines = DATA_LINES_X1; 964 sfc_nand_dev.prog_lines = DATA_LINES_X1; 965 sfc_nand_dev.page_read_cmd = 0x03; 966 sfc_nand_dev.page_prog_cmd = 0x02; 967 968 if (p_nand_info->feature & FEA_4BIT_READ) { 969 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 970 !p_nand_info->has_qe_bits) { 971 sfc_nand_dev.read_lines = DATA_LINES_X4; 972 sfc_nand_dev.page_read_cmd = 0x6b; 973 } 974 } 975 976 if (p_nand_info->feature & FEA_4BIT_PROG && 977 sfc_nand_dev.read_lines == DATA_LINES_X4) { 978 sfc_nand_dev.prog_lines = DATA_LINES_X4; 979 sfc_nand_dev.page_prog_cmd = 0x32; 980 } 981 982 sfc_nand_read_feature(0xA0, &status); 983 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 984 sfc_nand_read_feature(0xB0, &status); 985 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 986 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 987 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 988 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 989 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 990 991 return SFC_OK; 992 } 993 994 void sfc_nand_deinit(void) 995 { 996 /* to-do */ 997 } 998 999 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 1000 { 1001 return &sfc_nand_dev; 1002 } 1003 1004