1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static struct nand_info spi_nand_tbl[] = { 18 /* TC58CVG0S0HxAIx */ 19 {0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xFF, 0xFF, 4, 8, NULL}, 20 /* TC58CVG1S0HxAIx */ 21 {0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xFF, 0xFF, 4, 8, NULL}, 22 /* MX35LF1GE4AB */ 23 {0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 24 /* MX35LF2GE4AB */ 25 {0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 26 /* GD5F1GQ4UAYIG */ 27 {0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, NULL}, 28 /* MT29F1G01ZAC */ 29 {0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 30 /* GD5F2GQ40BY2GR */ 31 {0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 32 /* GD5F1GQ4U */ 33 {0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 34 /* IS37SML01G1 */ 35 {0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xFF, 0xFF, 8, 12, &sfc_nand_ecc_status_sp1}, 36 /* W25N01GV */ 37 {0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 4, 20, &sfc_nand_ecc_status_sp1}, 38 /* HYF2GQ4UAACAE */ 39 {0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 40 /* HYF2GQ4UDACAE */ 41 {0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, NULL}, 42 /* HYF2GQ4UHCCAE */ 43 {0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 44 /* HYF1GQ4UDACAE */ 45 {0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, NULL}, 46 /* F50L1G41LB */ 47 {0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 20, 36, &sfc_nand_ecc_status_sp1}, 48 /* XT26G02A */ 49 {0x0BE2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 50 /* XT26G01A */ 51 {0x0BE1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 52 /* FS35ND01G-S1 */ 53 {0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 16, 20, &sfc_nand_ecc_status_sp5}, 54 /* FS35ND02G-S2 */ 55 {0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, 16, 20, &sfc_nand_ecc_status_sp5}, 56 /* DS35Q1GA-1B */ 57 {0xE571, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 58 /* DS35Q2GA-1B */ 59 {0xE572, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 60 /* EM73C044SNC-G */ 61 {0xD522, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0x0, 4, 20, NULL}, 62 /* EM73D044SNB-G */ 63 {0xD520, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0x0, 4, 20, NULL} 64 }; 65 66 static u8 id_byte[8]; 67 static struct nand_info *p_nand_info; 68 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 69 static struct SFNAND_DEV sfc_nand_dev; 70 71 static struct nand_info *spi_nand_get_info(u8 *nand_id) 72 { 73 u32 i; 74 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 75 76 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 77 if (spi_nand_tbl[i].id == id) 78 return &spi_nand_tbl[i]; 79 } 80 return NULL; 81 } 82 83 static int sfc_nand_write_en(void) 84 { 85 int ret; 86 union SFCCMD_DATA sfcmd; 87 88 sfcmd.d32 = 0; 89 sfcmd.b.cmd = CMD_WRITE_EN; 90 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 91 return ret; 92 } 93 94 static int sfc_nand_rw_preset(void) 95 { 96 int ret; 97 union SFCCTRL_DATA sfctrl; 98 union SFCCMD_DATA sfcmd; 99 u8 status = 0xFF; 100 101 sfcmd.d32 = 0; 102 sfcmd.b.cmd = 0; 103 sfcmd.b.datasize = 1; 104 sfcmd.b.rw = SFC_WRITE; 105 106 sfctrl.b.datalines = 2; 107 ret = sfc_request(sfcmd.d32, sfctrl.d32, 0, &status); 108 return ret; 109 } 110 111 static int sfc_nand_read_feature(u8 addr, u8 *data) 112 { 113 int ret; 114 union SFCCMD_DATA sfcmd; 115 116 sfcmd.d32 = 0; 117 sfcmd.b.cmd = 0x0F; 118 sfcmd.b.datasize = 1; 119 sfcmd.b.addrbits = SFC_ADDR_XBITS; 120 *data = 0; 121 122 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, data); 123 if (ret != SFC_OK) 124 return ret; 125 return SFC_OK; 126 } 127 128 static int sfc_nand_write_feature(u32 addr, u8 status) 129 { 130 int ret; 131 union SFCCMD_DATA sfcmd; 132 133 sfc_nand_write_en(); 134 135 sfcmd.d32 = 0; 136 sfcmd.b.cmd = 0x1F; 137 sfcmd.b.datasize = 1; 138 sfcmd.b.addrbits = SFC_ADDR_XBITS; 139 sfcmd.b.rw = SFC_WRITE; 140 141 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, &status); 142 if (ret != SFC_OK) 143 return ret; 144 return ret; 145 } 146 147 static int sfc_nand_wait_busy(u8 *data, int timeout) 148 { 149 int ret; 150 int i; 151 u8 status; 152 153 *data = 0; 154 for (i = 0; i < timeout; i++) { 155 ret = sfc_nand_read_feature(0xC0, &status); 156 if (ret != SFC_OK) 157 return ret; 158 *data = status; 159 if (!(status & (1 << 0))) 160 return SFC_OK; 161 sfc_delay(1); 162 } 163 return -1; 164 } 165 166 /* 167 * ecc default: 168 * 0, No bit errors were detected 169 * 1, Bit errors were detected and corrected. 170 * 2, Multiple bit errors were detected and not corrected. 171 * 3, Bits errors were detected and corrected, bit error count 172 * exceed the bit flip detection threshold 173 */ 174 static u32 sfc_nand_ecc_status(void) 175 { 176 int ret; 177 u32 i; 178 u8 ecc; 179 u8 status; 180 u32 timeout = 1000 * 1000; 181 182 for (i = 0; i < timeout; i++) { 183 ret = sfc_nand_read_feature(0xC0, &status); 184 if (ret != SFC_OK) 185 return SFC_NAND_ECC_ERROR; 186 if (!(status & (1 << 0))) 187 break; 188 sfc_delay(1); 189 } 190 191 ecc = (status >> 4) & 0x03; 192 193 if (ecc <= 1) 194 ret = SFC_NAND_ECC_OK; 195 else if (ecc == 2) 196 ret = SFC_NAND_ECC_ERROR; 197 else 198 ret = SFC_NAND_ECC_REFRESH; 199 200 return ret; 201 } 202 203 /* 204 * ecc spectial type1: 205 * 0x00, No bit errors were detected; 206 * 0x01, Bits errors were detected and corrected, bit error count 207 * may reach the bit flip detection threshold; 208 * 0x10, Multiple bit errors were detected and not corrected; 209 * 0x11, Reserved. 210 */ 211 u32 sfc_nand_ecc_status_sp1(void) 212 { 213 int ret; 214 u32 i; 215 u8 ecc; 216 u8 status; 217 u32 timeout = 1000 * 1000; 218 219 for (i = 0; i < timeout; i++) { 220 ret = sfc_nand_read_feature(0xC0, &status); 221 if (ret != SFC_OK) 222 return SFC_NAND_ECC_ERROR; 223 if (!(status & (1 << 0))) 224 break; 225 sfc_delay(1); 226 } 227 228 ecc = (status >> 4) & 0x03; 229 230 if (ecc == 0) 231 ret = SFC_NAND_ECC_OK; 232 else if (ecc == 1) 233 ret = SFC_NAND_ECC_REFRESH; 234 else 235 ret = SFC_NAND_ECC_ERROR; 236 237 return ret; 238 } 239 240 /* 241 * ecc spectial type3: 242 * [0x0000, 0x0011], No bit errors were detected; 243 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 244 * reach Flipping Bits; 245 * [0x1000, 0x1011], Multiple bit errors were detected and 246 * not corrected. 247 * [0x1100, 0x1111], Bit error count equals the bit flip 248 * detectionthreshold 249 */ 250 u32 sfc_nand_ecc_status_sp3(void) 251 { 252 int ret; 253 u32 i; 254 u8 ecc; 255 u8 status, status1; 256 u32 timeout = 1000 * 1000; 257 258 for (i = 0; i < timeout; i++) { 259 ret = sfc_nand_read_feature(0xC0, &status); 260 if (ret != SFC_OK) 261 return SFC_NAND_ECC_ERROR; 262 ret = sfc_nand_read_feature(0xF0, &status1); 263 if (ret != SFC_OK) 264 return SFC_NAND_ECC_ERROR; 265 if (!(status & (1 << 0))) 266 break; 267 sfc_delay(1); 268 } 269 270 ecc = (status >> 4) & 0x03; 271 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 272 if (ecc < 7) 273 ret = SFC_NAND_ECC_OK; 274 else if (ecc == 7 || ecc >= 12) 275 ret = SFC_NAND_ECC_REFRESH; 276 else 277 ret = SFC_NAND_ECC_ERROR; 278 279 return ret; 280 } 281 282 /* 283 * ecc spectial type4: 284 * [0x0000], No bit errors were detected; 285 * [0x0001, 0x0111], Bit errors were detected and corrected. Not 286 * reach Flipping Bits; 287 * [0x1000], Multiple bit errors were detected and 288 * not corrected. 289 * [0x1100], Bit error count equals the bit flip 290 * detectionthreshold 291 * else, reserved 292 */ 293 u32 sfc_nand_ecc_status_sp4(void) 294 { 295 int ret; 296 u32 i; 297 u8 ecc; 298 u8 status; 299 u32 timeout = 1000 * 1000; 300 301 for (i = 0; i < timeout; i++) { 302 ret = sfc_nand_read_feature(0xC0, &status); 303 if (ret != SFC_OK) 304 return SFC_NAND_ECC_ERROR; 305 if (!(status & (1 << 0))) 306 break; 307 sfc_delay(1); 308 } 309 310 ecc = (status >> 2) & 0x0f; 311 if (ecc < 7) 312 ret = SFC_NAND_ECC_OK; 313 else if (ecc == 7 || ecc == 12) 314 ret = SFC_NAND_ECC_REFRESH; 315 else 316 ret = SFC_NAND_ECC_ERROR; 317 318 return ret; 319 } 320 321 /* 322 * ecc spectial type5: 323 * [0x0], No bit errors were detected; 324 * [0x001, 0x011], Bit errors were detected and corrected. Not 325 * reach Flipping Bits; 326 * [0x100], Bit error count equals the bit flip 327 * detectionthreshold 328 * [0x101, 0x110], Reserved; 329 * [0x111], Multiple bit errors were detected and 330 * not corrected. 331 */ 332 u32 sfc_nand_ecc_status_sp5(void) 333 { 334 int ret; 335 u32 i; 336 u8 ecc; 337 u8 status; 338 u32 timeout = 1000 * 1000; 339 340 for (i = 0; i < timeout; i++) { 341 ret = sfc_nand_read_feature(0xC0, &status); 342 if (ret != SFC_OK) 343 return SFC_NAND_ECC_ERROR; 344 if (!(status & (1 << 0))) 345 break; 346 sfc_delay(1); 347 } 348 349 ecc = (status >> 4) & 0x07; 350 if (ecc < 4) 351 ret = SFC_NAND_ECC_OK; 352 else if (ecc == 4) 353 ret = SFC_NAND_ECC_REFRESH; 354 else 355 ret = SFC_NAND_ECC_ERROR; 356 357 return ret; 358 } 359 360 static u32 sfc_nand_erase_block(u8 cs, u32 addr) 361 { 362 int ret; 363 union SFCCMD_DATA sfcmd; 364 u8 status; 365 366 sfcmd.d32 = 0; 367 sfcmd.b.cmd = p_nand_info->block_erase_cmd; 368 sfcmd.b.addrbits = SFC_ADDR_24BITS; 369 sfc_nand_write_en(); 370 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 371 if (ret != SFC_OK) 372 return ret; 373 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 374 if (status & (1 << 2)) 375 return SFC_NAND_PROG_ERASE_ERROR; 376 return ret; 377 } 378 379 static u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 380 { 381 int ret; 382 u32 plane; 383 union SFCCMD_DATA sfcmd; 384 union SFCCTRL_DATA sfctrl; 385 u8 status; 386 u32 data_sz = 2048; 387 u32 spare_offs_1 = p_nand_info->spare_offs_1; 388 u32 spare_offs_2 = p_nand_info->spare_offs_2; 389 390 memcpy(gp_page_buf, p_data, data_sz); 391 ftl_memset(&gp_page_buf[data_sz / 4], 0xff, 64); 392 gp_page_buf[(data_sz + spare_offs_1) / 4] = p_spare[0]; 393 gp_page_buf[(data_sz + spare_offs_2) / 4] = p_spare[1]; 394 395 sfc_nand_write_en(); 396 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 397 p_nand_info->feature & FEA_SOFT_QOP_BIT && 398 sfc_get_version() < SFC_VER_3) 399 sfc_nand_rw_preset(); 400 401 sfcmd.d32 = 0; 402 sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 403 sfcmd.b.addrbits = SFC_ADDR_XBITS; 404 sfcmd.b.datasize = SFC_NAND_PAGE_MAX_SIZE; 405 sfcmd.b.rw = SFC_WRITE; 406 407 sfctrl.d32 = 0; 408 sfctrl.b.datalines = sfc_nand_dev.prog_lines; 409 sfctrl.b.addrbits = 16; 410 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 411 sfc_request(sfcmd.d32, sfctrl.d32, plane, gp_page_buf); 412 413 sfcmd.d32 = 0; 414 sfcmd.b.cmd = p_nand_info->page_prog_cmd; 415 sfcmd.b.addrbits = SFC_ADDR_24BITS; 416 sfcmd.b.datasize = 0; 417 sfcmd.b.rw = SFC_WRITE; 418 ret = sfc_request(sfcmd.d32, 0, addr, p_data); 419 if (ret != SFC_OK) 420 return ret; 421 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 422 if (status & (1 << 3)) 423 return SFC_NAND_PROG_ERASE_ERROR; 424 return ret; 425 } 426 427 static u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 428 { 429 int ret; 430 u32 plane; 431 union SFCCMD_DATA sfcmd; 432 union SFCCTRL_DATA sfctrl; 433 u32 ecc_result; 434 u32 data_sz = 2048; 435 u32 spare_offs_1 = p_nand_info->spare_offs_1; 436 u32 spare_offs_2 = p_nand_info->spare_offs_2; 437 438 sfcmd.d32 = 0; 439 sfcmd.b.cmd = p_nand_info->page_read_cmd; 440 sfcmd.b.datasize = 0; 441 sfcmd.b.addrbits = SFC_ADDR_24BITS; 442 sfc_request(sfcmd.d32, 0, addr, p_data); 443 444 if (p_nand_info->ecc_status) 445 ecc_result = p_nand_info->ecc_status(); 446 else 447 ecc_result = sfc_nand_ecc_status(); 448 449 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 450 p_nand_info->feature & FEA_SOFT_QOP_BIT && 451 sfc_get_version() < SFC_VER_3) 452 sfc_nand_rw_preset(); 453 454 sfcmd.d32 = 0; 455 sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 456 sfcmd.b.datasize = SFC_NAND_PAGE_MAX_SIZE; 457 sfcmd.b.addrbits = SFC_ADDR_24BITS; 458 sfctrl.d32 = 0; 459 sfctrl.b.datalines = sfc_nand_dev.read_lines; 460 461 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 462 memset(gp_page_buf, 0, SFC_NAND_PAGE_MAX_SIZE); 463 ret = sfc_request(sfcmd.d32, sfctrl.d32, plane << 8, gp_page_buf); 464 465 memcpy(p_data, gp_page_buf, data_sz); 466 p_spare[0] = gp_page_buf[(data_sz + spare_offs_1) / 4]; 467 p_spare[1] = gp_page_buf[(data_sz + spare_offs_2) / 4]; 468 if (ret != SFC_OK) 469 return SFC_NAND_ECC_ERROR; 470 471 if (ecc_result != SFC_NAND_ECC_OK) { 472 PRINT_SFC_E("%s[0x%x], ret=0x%x\n", __func__, addr, ecc_result); 473 if (p_data) 474 PRINT_SFC_HEX("data:", p_data, 4, 8); 475 if (p_spare) 476 PRINT_SFC_HEX("spare:", p_spare, 4, 2); 477 } 478 return ecc_result; 479 } 480 481 static int sfc_nand_read_id_raw(u8 *data) 482 { 483 int ret; 484 union SFCCMD_DATA sfcmd; 485 486 sfcmd.d32 = 0; 487 sfcmd.b.cmd = CMD_READ_JEDECID; 488 sfcmd.b.datasize = 3; 489 sfcmd.b.addrbits = SFC_ADDR_XBITS; 490 491 ret = sfc_request(sfcmd.d32, 0x8 << 16, 0, data); 492 493 return ret; 494 } 495 496 /* 497 * Read the 1st page's 1st byte of a phy_blk 498 * If not FF, it's bad blk 499 */ 500 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 501 { 502 u16 blk; 503 u32 bad_cnt, page; 504 u32 blk_per_die; 505 u32 *pread; 506 u32 *pspare_read; 507 508 PRINT_SFC_E("%s\n", __func__); 509 pread = ftl_malloc(2048); 510 pspare_read = ftl_malloc(8); 511 bad_cnt = 0; 512 blk_per_die = p_nand_info->plane_per_die * 513 p_nand_info->blk_per_plane; 514 for (blk = 0; blk < blk_per_die; blk++) { 515 page = (blk + blk_per_die * die) * 516 p_nand_info->page_per_blk; 517 sfc_nand_read_page(0, page, pread, pspare_read); 518 519 if (pread[0] != 0xFFFFFFFF || 520 pspare_read[0] != 0xFFFFFFFF) { 521 table[bad_cnt++] = blk; 522 PRINT_SFC_E("die[%d], bad_blk[%d]\n", die, blk); 523 } 524 } 525 ftl_free(pread); 526 ftl_free(pspare_read); 527 return (int)bad_cnt; 528 } 529 530 #if SFC_NAND_STRESS_TEST_EN 531 532 #define SFC_NAND_PAGE_SIZE 2048 533 #define SFC_NAND_SPARE_SIZE 8 534 535 static u16 bad_blk_list[1024]; 536 static u32 pwrite[SFC_NAND_PAGE_SIZE / 4]; 537 static u32 pread[SFC_NAND_PAGE_SIZE / 4]; 538 static u32 pspare_write[SFC_NAND_SPARE_SIZE / 4]; 539 static u32 pspare_read[SFC_NAND_SPARE_SIZE / 4]; 540 static u32 bad_blk_num; 541 static u32 bad_page_num; 542 543 static void sfc_nand_test(void) 544 { 545 u32 i, blk, page, bad_cnt, page_addr; 546 int ret; 547 u32 pages_num = 64; 548 u32 blk_addr = 64; 549 u32 is_bad_blk = 0; 550 551 PRINT_SFC_E("%s\n", __func__); 552 553 bad_blk_num = 0; 554 bad_page_num = 0; 555 bad_cnt = sfc_nand_get_bad_block_list(bad_blk_list, 0); 556 557 for (blk = 0; blk < 1024; blk++) { 558 for (i = 0; i < bad_cnt; i++) { 559 if (bad_blk_list[i] == blk) 560 break; 561 } 562 if (i < bad_cnt) 563 continue; 564 is_bad_blk = 0; 565 PRINT_SFC_E("Flash prog block: %x\n", blk); 566 sfc_nand_erase_block(0, blk * blk_addr); 567 for (page = 0; page < pages_num; page++) { 568 page_addr = blk * blk_addr + page; 569 for (i = 0; i < 512; i++) 570 pwrite[i] = (page_addr << 16) + i; 571 pspare_write[0] = pwrite[0] + 0x5AF0; 572 pspare_write[1] = pspare_write[0] + 1; 573 sfc_nand_prog_page(0, page_addr, pwrite, pspare_write); 574 memset(pread, 0, 2048); 575 memset(pspare_read, 0, 8); 576 ret = sfc_nand_read_page(0, page_addr, pread, 577 pspare_read); 578 if (ret != SFC_NAND_ECC_OK) 579 is_bad_blk = 1; 580 for (i = 0; i < 512; i++) { 581 if (pwrite[i] != pread[i]) { 582 is_bad_blk = 1; 583 break; 584 } 585 } 586 for (i = 0; i < 2; i++) { 587 if (pspare_write[i] != pspare_read[i]) { 588 is_bad_blk = 1; 589 break; 590 } 591 } 592 if (is_bad_blk) { 593 bad_page_num++; 594 PRINT_SFC_E("ERR:page%x, ret=%x\n", 595 page_addr, ret); 596 PRINT_SFC_HEX("data:", pread, 4, 8); 597 PRINT_SFC_HEX("spare:", pspare_read, 4, 2); 598 } 599 } 600 sfc_nand_erase_block(0, blk * blk_addr); 601 if (is_bad_blk) 602 bad_blk_num++; 603 } 604 PRINT_SFC_E("bad_blk_num = %d, bad_page_num = %d\n", 605 bad_blk_num, bad_page_num); 606 607 PRINT_SFC_E("Flash Test Finish!!!\n"); 608 while (1) 609 ; 610 } 611 #endif 612 613 static void ftl_flash_init(void) 614 { 615 /* para init */ 616 g_nand_phy_info.nand_type = 1; 617 g_nand_phy_info.die_num = 1; 618 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 619 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 620 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 621 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 622 g_nand_phy_info.byte_per_sec = 512; 623 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 624 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 625 p_nand_info->page_per_blk; 626 g_nand_phy_info.reserved_blk = 8; 627 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 628 p_nand_info->blk_per_plane; 629 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 630 631 /* driver register */ 632 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 633 g_nand_ops.erase_blk = sfc_nand_erase_block; 634 g_nand_ops.prog_page = sfc_nand_prog_page; 635 g_nand_ops.read_page = sfc_nand_read_page; 636 g_nand_ops.bch_sel = NULL; 637 } 638 639 static int spi_nand_enable_QE(void) 640 { 641 int ret = SFC_OK; 642 u8 status; 643 int bit_offset = p_nand_info->QE_bits; 644 645 if (bit_offset == 0xFF) 646 return SFC_OK; 647 648 ret = sfc_nand_read_feature(p_nand_info->QE_address, &status); 649 if (ret != SFC_OK) 650 return ret; 651 652 if (status & (1 << bit_offset)) /* is QE bit set */ 653 return SFC_OK; 654 655 status |= (1 << bit_offset); 656 return sfc_nand_write_feature(p_nand_info->QE_address, status); 657 658 return ret; 659 } 660 661 u32 sfc_nand_init(void) 662 { 663 PRINT_SFC_I("...%s enter...\n", __func__); 664 665 sfc_nand_read_id_raw(id_byte); 666 PRINT_SFC_E("sfc_nand id: %x %x %x\n", 667 id_byte[0], id_byte[1], id_byte[2]); 668 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 669 return FTL_NO_FLASH; 670 671 p_nand_info = spi_nand_get_info(id_byte); 672 if (!p_nand_info) 673 return FTL_UNSUPPORTED_FLASH; 674 675 sfc_nand_dev.manufacturer = id_byte[0]; 676 sfc_nand_dev.mem_type = id_byte[1]; 677 678 /* disable block lock */ 679 sfc_nand_write_feature(0xA0, 0); 680 sfc_nand_dev.read_lines = DATA_LINES_X1; 681 sfc_nand_dev.prog_lines = DATA_LINES_X1; 682 sfc_nand_dev.page_read_cmd = p_nand_info->read_cache_cmd_1; 683 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_1; 684 if (p_nand_info->feature & FEA_4BIT_READ) { 685 if (spi_nand_enable_QE() == SFC_OK) { 686 sfc_nand_dev.read_lines = DATA_LINES_X4; 687 sfc_nand_dev.page_read_cmd = 688 p_nand_info->read_cache_cmd_4; 689 } 690 } 691 692 if (p_nand_info->feature & FEA_4BIT_PROG && 693 sfc_nand_dev.read_lines == DATA_LINES_X4) { 694 sfc_nand_dev.prog_lines = DATA_LINES_X4; 695 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_4; 696 } 697 698 if (1) { 699 u8 status; 700 701 sfc_nand_read_feature(0xA0, &status); 702 PRINT_SFC_I("sfc_nand A0 = 0x%x\n", status); 703 sfc_nand_read_feature(0xB0, &status); 704 PRINT_SFC_I("sfc_nand B0 = 0x%x\n", status); 705 sfc_nand_read_feature(0xC0, &status); 706 PRINT_SFC_I("sfc_nand C0 = 0x%x\n", status); 707 PRINT_SFC_I("read_lines = %x\n", sfc_nand_dev.read_lines); 708 PRINT_SFC_I("prog_lines = %x\n", sfc_nand_dev.prog_lines); 709 PRINT_SFC_I("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 710 PRINT_SFC_I("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 711 } 712 ftl_flash_init(); 713 714 #if SFC_NAND_STRESS_TEST_EN 715 sfc_nand_test(); 716 #endif 717 718 return SFC_OK; 719 } 720 721 int sfc_nand_read_id(u8 *data) 722 { 723 memcpy(data, id_byte, 3); 724 return 0; 725 } 726