1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 static u32 sfc_nand_get_ecc_status7(void); 25 static u32 sfc_nand_get_ecc_status8(void); 26 static u32 sfc_nand_get_ecc_status9(void); 27 28 static struct nand_info spi_nand_tbl[] = { 29 /* TC58CVG0S0HxAIx */ 30 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 31 /* TC58CVG1S0HxAIx */ 32 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 33 /* TC58CVG2S0HRAIJ */ 34 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 35 /* TC58CVG1S3HRAIJ */ 36 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 37 /* TC58CVG0S3HRAIJ */ 38 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 39 40 /* MX35LF1GE4AB */ 41 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 42 /* MX35LF2GE4AB */ 43 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 44 /* MX35LF2GE4AD */ 45 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 46 /* MX35LF4GE4AD */ 47 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 48 /* MX35UF1GE4AC */ 49 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 50 /* MX35UF2GE4AC */ 51 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 52 /* MX35UF1GE4AD */ 53 { 0xC2, 0x96, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 54 /* MX35UF2GE4AD */ 55 { 0xC2, 0xA6, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 56 /* MX35UF4GE4AD */ 57 { 0xC2, 0xB7, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 58 59 /* GD5F1GQ4UAYIG */ 60 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 61 /* GD5F1GQ4RB9IGR */ 62 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 63 /* GD5F2GQ40BY2GR */ 64 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 65 /* GD5F1GQ5UEYIG */ 66 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 67 /* GD5F2GQ5UEYIG */ 68 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 69 /* GD5F1GQ4R */ 70 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 71 /* GD5F4GQ6RExxG 1*4096 */ 72 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, 73 /* GD5F4GQ6UExxG 1*4096 */ 74 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, 75 /* GD5F1GQ4UExxH */ 76 { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 77 /* GD5F1GQ5REYIG */ 78 { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 79 /* GD5F2GQ5REYIG */ 80 { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 81 /* GD5F2GM7RxG */ 82 { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 83 /* GD5F2GM7UxG */ 84 { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 85 /* GD5F1GM7UxG */ 86 { 0xC8, 0x91, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 87 /* GD5F4GQ4UAYIG 1*4096 */ 88 { 0xC8, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 89 90 /* W25N01GV */ 91 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 92 /* W25N02KVZEIR */ 93 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 94 /* W25N04KVZEIR */ 95 { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 }, 96 /* W25N01GW */ 97 { 0xEF, 0xBA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 98 /* W25N02KW */ 99 { 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 100 /* W25N512GVEIG */ 101 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 102 /* W25N01KV */ 103 { 0xEF, 0xAE, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 104 105 /* HYF2GQ4UAACAE */ 106 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 107 /* HYF1GQ4UDACAE */ 108 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 109 /* HYF1GQ4UPACAE */ 110 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 111 /* HYF2GQ4UDACAE */ 112 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 113 /* HYF2GQ4UHCCAE */ 114 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 115 /* HYF4GQ4UAACBE */ 116 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 117 /* HYF2GQ4IAACAE */ 118 { 0xC9, 0x82, 0x00, 4, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 119 /* HYF1GQ4IDACAE */ 120 { 0xC9, 0x81, 0x00, 4, 0x40, 1, 1024, 0x4C, 20, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 121 122 /* FS35ND01G-S1 */ 123 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 124 /* FS35ND02G-S2 */ 125 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 126 /* FS35ND01G-S1Y2 */ 127 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 128 /* FS35ND02G-S3Y2 */ 129 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 130 /* FS35ND04G-S2Y2 1*4096 */ 131 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 132 /* F35SQA001G */ 133 { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 134 /* F35SQA002G */ 135 { 0xCD, 0x72, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 136 /* F35SQA512M */ 137 { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 138 /* F35UQA512M */ 139 { 0xCD, 0x60, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 140 141 /* DS35Q1GA-IB */ 142 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 143 /* DS35Q2GA-IB */ 144 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 145 /* DS35M1GA-1B */ 146 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 147 /* DS35M2GA-IB */ 148 { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 149 /* DS35Q1GB-IB */ 150 { 0xE5, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 151 /* DS35Q2GB-IB */ 152 { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 153 /* DS35Q4GM */ 154 { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 155 /* DS35M1GB-IB */ 156 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 157 /* DS35Q12B-IB */ 158 { 0xE5, 0xF5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 159 /* DS35M12B-IB */ 160 { 0xE5, 0xA5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 161 162 /* EM73C044VCC-H */ 163 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 164 /* EM73D044VCE-H */ 165 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 166 /* EM73E044SNA-G */ 167 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 168 /* EM73C044VCF-H */ 169 { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 170 171 /* XT26G02A */ 172 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 173 /* XT26G01A */ 174 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 175 /* XT26G04A */ 176 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 177 /* XT26G01B */ 178 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 179 /* XT26G02B */ 180 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 181 /* XT26G01C */ 182 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 183 /* XT26G02C */ 184 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 185 /* XT26G04C */ 186 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, 187 /* XT26G11C */ 188 { 0x0B, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 189 190 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ 191 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 192 /* MT29F1G01ABA, F50L1G41XA */ 193 { 0x2C, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 194 195 /* FM25S01 */ 196 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 197 /* FM25S01A */ 198 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 199 /* FM25S02A */ 200 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 201 /* FM25LS01 */ 202 { 0xA1, 0xA5, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 203 204 /* IS37SML01G1 */ 205 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 206 /* F50L1G41LB */ 207 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 208 /* ATO25D1GA */ 209 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 210 /* BWJX08K-2Gb */ 211 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 212 /* JS28U1GQSCAHG-83 */ 213 { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 214 /* SGM7000I-S24W1GH */ 215 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 216 /* TX25G01 */ 217 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 218 /* ANV1GCP0CLG, HYF1GQ4UTXCAE */ 219 { 0x01, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status9 }, 220 /* S35ML02G3, ANV1GCP0CLG */ 221 { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, 222 /* S35ML04G3 */ 223 { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, 224 /* GSS01GSAK1 */ 225 { 0x52, 0xBA, 0x13, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 226 /* GSS02GSAK1 */ 227 { 0x52, 0xBA, 0x23, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 228 }; 229 230 static struct nand_info *p_nand_info; 231 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 232 static struct SFNAND_DEV sfc_nand_dev; 233 234 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 235 { 236 u32 i; 237 238 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 239 if (spi_nand_tbl[i].id0 == nand_id[0] && 240 spi_nand_tbl[i].id1 == nand_id[1]) { 241 if (spi_nand_tbl[i].id2 && 242 spi_nand_tbl[i].id2 != nand_id[2]) 243 continue; 244 245 return &spi_nand_tbl[i]; 246 } 247 } 248 249 return NULL; 250 } 251 252 static int sfc_nand_write_en(void) 253 { 254 int ret; 255 struct rk_sfc_op op; 256 257 op.sfcmd.d32 = 0; 258 op.sfcmd.b.cmd = CMD_WRITE_EN; 259 260 op.sfctrl.d32 = 0; 261 262 ret = sfc_request(&op, 0, NULL, 0); 263 return ret; 264 } 265 266 static int sfc_nand_rw_preset(void) 267 { 268 int ret; 269 struct rk_sfc_op op; 270 271 op.sfcmd.d32 = 0; 272 op.sfcmd.b.cmd = 0xff; 273 op.sfcmd.b.cs = 2; 274 275 op.sfctrl.d32 = 0; 276 op.sfctrl.b.datalines = 2; 277 op.sfctrl.b.cmdlines = 2; 278 op.sfctrl.b.addrlines = 2; 279 280 ret = sfc_request(&op, 0, NULL, 0); 281 return ret; 282 } 283 284 static int sfc_nand_read_feature(u8 addr, u8 *data) 285 { 286 int ret; 287 struct rk_sfc_op op; 288 289 op.sfcmd.d32 = 0; 290 op.sfcmd.b.cmd = 0x0F; 291 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 292 293 op.sfctrl.d32 = 0; 294 op.sfctrl.b.addrbits = 8; 295 296 *data = 0; 297 298 ret = sfc_request(&op, addr, data, 1); 299 300 if (ret != SFC_OK) 301 return ret; 302 303 return SFC_OK; 304 } 305 306 static int sfc_nand_write_feature(u32 addr, u8 status) 307 { 308 int ret; 309 struct rk_sfc_op op; 310 311 sfc_nand_write_en(); 312 313 op.sfcmd.d32 = 0; 314 op.sfcmd.b.cmd = 0x1F; 315 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 316 op.sfcmd.b.rw = SFC_WRITE; 317 318 op.sfctrl.d32 = 0; 319 op.sfctrl.b.addrbits = 8; 320 321 ret = sfc_request(&op, addr, &status, 1); 322 323 if (ret != SFC_OK) 324 return ret; 325 326 return ret; 327 } 328 329 static int sfc_nand_wait_busy(u8 *data, int timeout) 330 { 331 int ret; 332 int i; 333 u8 status; 334 335 *data = 0; 336 337 for (i = 0; i < timeout; i++) { 338 ret = sfc_nand_read_feature(0xC0, &status); 339 340 if (ret != SFC_OK) 341 return ret; 342 343 *data = status; 344 345 if (!(status & (1 << 0))) 346 return SFC_OK; 347 348 sfc_delay(1); 349 } 350 351 return SFC_NAND_WAIT_TIME_OUT; 352 } 353 354 /* 355 * ecc default: 356 * ecc bits: 0xC0[4,5] 357 * 0b00, No bit errors were detected 358 * 0b01, Bit errors were detected and corrected. 359 * 0b10, Multiple bit errors were detected and not corrected. 360 * 0b11, Bits errors were detected and corrected, bit error count 361 * reach the bit flip detection threshold 362 */ 363 static u32 sfc_nand_get_ecc_status0(void) 364 { 365 u32 ret; 366 u32 i; 367 u8 ecc; 368 u8 status; 369 u32 timeout = 1000 * 1000; 370 371 for (i = 0; i < timeout; i++) { 372 ret = sfc_nand_read_feature(0xC0, &status); 373 374 if (ret != SFC_OK) 375 return SFC_NAND_ECC_ERROR; 376 377 if (!(status & (1 << 0))) 378 break; 379 380 sfc_delay(1); 381 } 382 383 ecc = (status >> 4) & 0x03; 384 385 if (ecc <= 1) 386 ret = SFC_NAND_ECC_OK; 387 else if (ecc == 2) 388 ret = (u32)SFC_NAND_ECC_ERROR; 389 else 390 ret = SFC_NAND_ECC_REFRESH; 391 392 return ret; 393 } 394 395 /* 396 * ecc spectial type1: 397 * ecc bits: 0xC0[4,5] 398 * 0b00, No bit errors were detected; 399 * 0b01, Bits errors were detected and corrected, bit error count 400 * may reach the bit flip detection threshold; 401 * 0b10, Multiple bit errors were detected and not corrected; 402 * 0b11, Reserved. 403 */ 404 static u32 sfc_nand_get_ecc_status1(void) 405 { 406 u32 ret; 407 u32 i; 408 u8 ecc; 409 u8 status; 410 u32 timeout = 1000 * 1000; 411 412 for (i = 0; i < timeout; i++) { 413 ret = sfc_nand_read_feature(0xC0, &status); 414 415 if (ret != SFC_OK) 416 return SFC_NAND_ECC_ERROR; 417 418 if (!(status & (1 << 0))) 419 break; 420 421 sfc_delay(1); 422 } 423 424 ecc = (status >> 4) & 0x03; 425 426 if (ecc == 0) 427 ret = SFC_NAND_ECC_OK; 428 else if (ecc == 1) 429 ret = SFC_NAND_ECC_REFRESH; 430 else 431 ret = (u32)SFC_NAND_ECC_ERROR; 432 433 return ret; 434 } 435 436 /* 437 * ecc spectial type2: 438 * ecc bits: 0xC0[4,5] 0xF0[4,5] 439 * [0b0000, 0b0011], No bit errors were detected; 440 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 441 * reach Flipping Bits; 442 * [0b1000, 0b1011], Multiple bit errors were detected and 443 * not corrected. 444 * [0b1100, 0b1111], reserved. 445 */ 446 static u32 sfc_nand_get_ecc_status2(void) 447 { 448 u32 ret; 449 u32 i; 450 u8 ecc; 451 u8 status, status1; 452 u32 timeout = 1000 * 1000; 453 454 for (i = 0; i < timeout; i++) { 455 ret = sfc_nand_read_feature(0xC0, &status); 456 457 if (ret != SFC_OK) 458 return SFC_NAND_ECC_ERROR; 459 460 ret = sfc_nand_read_feature(0xF0, &status1); 461 462 if (ret != SFC_OK) 463 return SFC_NAND_ECC_ERROR; 464 465 if (!(status & (1 << 0))) 466 break; 467 468 sfc_delay(1); 469 } 470 471 ecc = (status >> 4) & 0x03; 472 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 473 474 if (ecc < 7) 475 ret = SFC_NAND_ECC_OK; 476 else if (ecc == 7) 477 ret = SFC_NAND_ECC_REFRESH; 478 else 479 ret = (u32)SFC_NAND_ECC_ERROR; 480 481 return ret; 482 } 483 484 /* 485 * ecc spectial type3: 486 * ecc bits: 0xC0[4,5] 0xF0[4,5] 487 * [0b0000, 0b0011], No bit errors were detected; 488 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 489 * reach Flipping Bits; 490 * [0b1000, 0b1011], Multiple bit errors were detected and 491 * not corrected. 492 * [0b1100, 0b1111], Bit error count equals the bit flip 493 * detectio nthreshold 494 */ 495 static u32 sfc_nand_get_ecc_status3(void) 496 { 497 u32 ret; 498 u32 i; 499 u8 ecc; 500 u8 status, status1; 501 u32 timeout = 1000 * 1000; 502 503 for (i = 0; i < timeout; i++) { 504 ret = sfc_nand_read_feature(0xC0, &status); 505 506 if (ret != SFC_OK) 507 return SFC_NAND_ECC_ERROR; 508 509 ret = sfc_nand_read_feature(0xF0, &status1); 510 511 if (ret != SFC_OK) 512 return SFC_NAND_ECC_ERROR; 513 514 if (!(status & (1 << 0))) 515 break; 516 517 sfc_delay(1); 518 } 519 520 ecc = (status >> 4) & 0x03; 521 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 522 523 if (ecc < 7) 524 ret = SFC_NAND_ECC_OK; 525 else if (ecc == 7 || ecc >= 12) 526 ret = SFC_NAND_ECC_REFRESH; 527 else 528 ret = (u32)SFC_NAND_ECC_ERROR; 529 530 return ret; 531 } 532 533 /* 534 * ecc spectial type4: 535 * ecc bits: 0xC0[2,5] 536 * [0b0000], No bit errors were detected; 537 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 538 * reach Flipping Bits; 539 * [0b1000], Multiple bit errors were detected and 540 * not corrected. 541 * [0b1100], Bit error count equals the bit flip 542 * detection threshold 543 * else, reserved 544 */ 545 static u32 sfc_nand_get_ecc_status4(void) 546 { 547 u32 ret; 548 u32 i; 549 u8 ecc; 550 u8 status; 551 u32 timeout = 1000 * 1000; 552 553 for (i = 0; i < timeout; i++) { 554 ret = sfc_nand_read_feature(0xC0, &status); 555 556 if (ret != SFC_OK) 557 return SFC_NAND_ECC_ERROR; 558 559 if (!(status & (1 << 0))) 560 break; 561 562 sfc_delay(1); 563 } 564 565 ecc = (status >> 2) & 0x0f; 566 567 if (ecc < 7) 568 ret = SFC_NAND_ECC_OK; 569 else if (ecc == 7 || ecc == 12) 570 ret = SFC_NAND_ECC_REFRESH; 571 else 572 ret = (u32)SFC_NAND_ECC_ERROR; 573 574 return ret; 575 } 576 577 /* 578 * ecc spectial type5: 579 * ecc bits: 0xC0[4,6] 580 * [0b000], No bit errors were detected; 581 * [0b001, 0b011], Bit errors were detected and corrected. Not 582 * reach Flipping Bits; 583 * [0b100], Bit error count equals the bit flip 584 * detection threshold 585 * [0b101, 0b110], Reserved; 586 * [0b111], Multiple bit errors were detected and 587 * not corrected. 588 */ 589 static u32 sfc_nand_get_ecc_status5(void) 590 { 591 u32 ret; 592 u32 i; 593 u8 ecc; 594 u8 status; 595 u32 timeout = 1000 * 1000; 596 597 for (i = 0; i < timeout; i++) { 598 ret = sfc_nand_read_feature(0xC0, &status); 599 600 if (ret != SFC_OK) 601 return SFC_NAND_ECC_ERROR; 602 603 if (!(status & (1 << 0))) 604 break; 605 606 sfc_delay(1); 607 } 608 609 ecc = (status >> 4) & 0x07; 610 611 if (ecc < 4) 612 ret = SFC_NAND_ECC_OK; 613 else if (ecc == 4) 614 ret = SFC_NAND_ECC_REFRESH; 615 else 616 ret = (u32)SFC_NAND_ECC_ERROR; 617 618 return ret; 619 } 620 621 /* 622 * ecc spectial type6: 623 * ecc bits: 0xC0[4,6] 624 * [0b000], No bit errors were detected; 625 * [0b001], 1-3 Bit errors were detected and corrected. Not 626 * reach Flipping Bits; 627 * [0b010], Multiple bit errors were detected and 628 * not corrected. 629 * [0b011], 4-6 Bit errors were detected and corrected. Not 630 * reach Flipping Bits; 631 * [0b101], Bit error count equals the bit flip 632 * detectionthreshold 633 * others, Reserved. 634 */ 635 static u32 sfc_nand_get_ecc_status6(void) 636 { 637 u32 ret; 638 u32 i; 639 u8 ecc; 640 u8 status; 641 u32 timeout = 1000 * 1000; 642 643 for (i = 0; i < timeout; i++) { 644 ret = sfc_nand_read_feature(0xC0, &status); 645 646 if (ret != SFC_OK) 647 return SFC_NAND_ECC_ERROR; 648 649 if (!(status & (1 << 0))) 650 break; 651 652 sfc_delay(1); 653 } 654 655 ecc = (status >> 4) & 0x07; 656 657 if (ecc == 0 || ecc == 1 || ecc == 3) 658 ret = SFC_NAND_ECC_OK; 659 else if (ecc == 5) 660 ret = SFC_NAND_ECC_REFRESH; 661 else 662 ret = (u32)SFC_NAND_ECC_ERROR; 663 664 return ret; 665 } 666 667 /* 668 * ecc spectial type7: 669 * ecc bits: 0xC0[4,7] 670 * [0b0000], No bit errors were detected; 671 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not 672 * reach Flipping Bits; 673 * [0b1000], 8 Bit errors were detected and corrected. Bit error count 674 * equals the bit flip detectionthreshold; 675 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; 676 * others, Reserved. 677 */ 678 static u32 sfc_nand_get_ecc_status7(void) 679 { 680 u32 ret; 681 u32 i; 682 u8 ecc; 683 u8 status; 684 u32 timeout = 1000 * 1000; 685 686 for (i = 0; i < timeout; i++) { 687 ret = sfc_nand_read_feature(0xC0, &status); 688 689 if (ret != SFC_OK) 690 return SFC_NAND_ECC_ERROR; 691 692 if (!(status & (1 << 0))) 693 break; 694 695 sfc_delay(1); 696 } 697 698 ecc = (status >> 4) & 0xf; 699 700 if (ecc < 7) 701 ret = SFC_NAND_ECC_OK; 702 else if (ecc == 7 || ecc == 8) 703 ret = SFC_NAND_ECC_REFRESH; 704 else 705 ret = (u32)SFC_NAND_ECC_ERROR; 706 707 return ret; 708 } 709 710 /* 711 * ecc spectial type8: 712 * ecc bits: 0xC0[4,6] 713 * [0b000], No bit errors were detected; 714 * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not 715 * reach Flipping Bits; 716 * [0b100], Bit error count equals the bit flip 717 * detection threshold 718 * others, Reserved. 719 */ 720 static u32 sfc_nand_get_ecc_status8(void) 721 { 722 u32 ret; 723 u32 i; 724 u8 ecc; 725 u8 status; 726 u32 timeout = 1000 * 1000; 727 728 for (i = 0; i < timeout; i++) { 729 ret = sfc_nand_read_feature(0xC0, &status); 730 731 if (ret != SFC_OK) 732 return SFC_NAND_ECC_ERROR; 733 734 if (!(status & (1 << 0))) 735 break; 736 737 sfc_delay(1); 738 } 739 740 ecc = (status >> 4) & 0x07; 741 742 if (ecc < 4) 743 ret = SFC_NAND_ECC_OK; 744 else if (ecc == 4) 745 ret = SFC_NAND_ECC_REFRESH; 746 else 747 ret = (u32)SFC_NAND_ECC_ERROR; 748 749 return ret; 750 } 751 752 /* 753 * ecc spectial type9: 754 * ecc bits: 0xC0[4,5] 755 * 0b00, No bit errors were detected 756 * 0b01, 1-2Bit errors were detected and corrected. 757 * 0b10, 3-4Bit errors were detected and corrected. 758 * 0b11, 11 can be used as uncorrectable 759 */ 760 static u32 sfc_nand_get_ecc_status9(void) 761 { 762 u32 ret; 763 u32 i; 764 u8 ecc; 765 u8 status; 766 u32 timeout = 1000 * 1000; 767 768 for (i = 0; i < timeout; i++) { 769 ret = sfc_nand_read_feature(0xC0, &status); 770 771 if (ret != SFC_OK) 772 return SFC_NAND_ECC_ERROR; 773 774 if (!(status & (1 << 0))) 775 break; 776 777 sfc_delay(1); 778 } 779 780 ecc = (status >> 4) & 0x03; 781 782 if (ecc <= 1) 783 ret = SFC_NAND_ECC_OK; 784 else if (ecc == 2) 785 ret = SFC_NAND_ECC_REFRESH; 786 else 787 ret = (u32)SFC_NAND_ECC_ERROR; 788 789 return ret; 790 } 791 792 u32 sfc_nand_erase_block(u8 cs, u32 addr) 793 { 794 int ret; 795 struct rk_sfc_op op; 796 u8 status; 797 798 rkflash_print_dio("%s %x\n", __func__, addr); 799 op.sfcmd.d32 = 0; 800 op.sfcmd.b.cmd = 0xd8; 801 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 802 op.sfcmd.b.rw = SFC_WRITE; 803 804 op.sfctrl.d32 = 0; 805 806 sfc_nand_write_en(); 807 ret = sfc_request(&op, addr, NULL, 0); 808 809 if (ret != SFC_OK) 810 return ret; 811 812 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 813 814 if (status & (1 << 2)) 815 return SFC_NAND_PROG_ERASE_ERROR; 816 817 return ret; 818 } 819 820 static u32 sfc_nand_read_cache(u32 row, u32 *p_page_buf, u32 column, u32 len) 821 { 822 int ret; 823 u32 plane; 824 struct rk_sfc_op op; 825 826 op.sfcmd.d32 = 0; 827 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 828 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 829 op.sfcmd.b.dummybits = 8; 830 831 op.sfctrl.d32 = 0; 832 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 833 op.sfctrl.b.addrbits = 16; 834 835 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 836 837 ret = sfc_request(&op, plane | column, p_page_buf, len); 838 if (ret != SFC_OK) 839 return SFC_NAND_HW_ERROR; 840 841 return ret; 842 } 843 844 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 845 { 846 int ret; 847 u32 plane; 848 struct rk_sfc_op op; 849 u8 status; 850 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 851 u32 data_area_size = SFC_NAND_SECTOR_SIZE * p_nand_info->sec_per_page; 852 853 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 854 sfc_nand_write_en(); 855 856 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 857 p_nand_info->feature & FEA_SOFT_QOP_BIT && 858 sfc_get_version() < SFC_VER_3) 859 sfc_nand_rw_preset(); 860 861 op.sfcmd.d32 = 0; 862 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 863 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 864 op.sfcmd.b.rw = SFC_WRITE; 865 866 op.sfctrl.d32 = 0; 867 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 868 op.sfctrl.b.addrbits = 16; 869 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 870 sfc_request(&op, plane, p_page_buf, page_size); 871 872 /* 873 * At the moment of power lost or dev running in harsh environment, flash 874 * maybe work in a unkonw state and result in bit flip, when this situation 875 * is detected by cache recheck, it's better to wait a second for a reliable 876 * hardware environment to avoid abnormal data written to flash array. 877 */ 878 if (p_nand_info->id0 == MID_GIGADEV) { 879 sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size); 880 if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) { 881 rkflash_print_error("%s %x cache bitflip\n", __func__, addr); 882 mdelay(1000); 883 sfc_request(&op, plane, p_page_buf, page_size); 884 } 885 } 886 887 op.sfcmd.d32 = 0; 888 op.sfcmd.b.cmd = 0x10; 889 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 890 op.sfcmd.b.rw = SFC_WRITE; 891 892 op.sfctrl.d32 = 0; 893 ret = sfc_request(&op, addr, p_page_buf, 0); 894 895 if (ret != SFC_OK) 896 return ret; 897 898 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 899 if (status & (1 << 3)) 900 return SFC_NAND_PROG_ERASE_ERROR; 901 902 return ret; 903 } 904 905 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 906 { 907 int ret; 908 u32 sec_per_page = p_nand_info->sec_per_page; 909 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 910 struct nand_mega_area *meta = &p_nand_info->meta; 911 912 memcpy(gp_page_buf, p_data, data_size); 913 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 914 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 915 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 916 917 if (sec_per_page == 8) { 918 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 919 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 920 } 921 922 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 923 924 return ret; 925 } 926 927 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 928 { 929 int ret; 930 u32 plane; 931 struct rk_sfc_op op; 932 u32 ecc_result; 933 u8 status; 934 935 op.sfcmd.d32 = 0; 936 op.sfcmd.b.cmd = 0x13; 937 op.sfcmd.b.rw = SFC_WRITE; 938 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 939 940 op.sfctrl.d32 = 0; 941 942 sfc_request(&op, row, p_page_buf, 0); 943 944 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 945 p_nand_info->feature & FEA_SOFT_QOP_BIT && 946 sfc_get_version() < SFC_VER_3) 947 sfc_nand_rw_preset(); 948 949 sfc_nand_wait_busy(&status, 1000 * 1000); 950 ecc_result = p_nand_info->ecc_status(); 951 952 op.sfcmd.d32 = 0; 953 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 954 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 955 op.sfcmd.b.dummybits = 8; 956 957 op.sfctrl.d32 = 0; 958 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 959 op.sfctrl.b.addrbits = 16; 960 961 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 962 ret = sfc_request(&op, plane | column, p_page_buf, len); 963 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 964 965 if (ret != SFC_OK) 966 return SFC_NAND_HW_ERROR; 967 968 return ecc_result; 969 } 970 971 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 972 { 973 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 974 975 return sfc_nand_read(addr, p_page_buf, 0, page_size); 976 } 977 978 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 979 { 980 u32 ret; 981 u32 sec_per_page = p_nand_info->sec_per_page; 982 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 983 struct nand_mega_area *meta = &p_nand_info->meta; 984 985 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 986 memcpy(p_data, gp_page_buf, data_size); 987 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 988 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 989 990 if (p_nand_info->sec_per_page == 8) { 991 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 992 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 993 } 994 995 if (ret == SFC_NAND_HW_ERROR) 996 ret = SFC_NAND_ECC_ERROR; 997 998 if (ret != SFC_NAND_ECC_OK) { 999 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 1000 1001 if (p_data) 1002 rkflash_print_hex("data:", p_data, 4, 8); 1003 1004 if (p_spare) 1005 rkflash_print_hex("spare:", p_spare, 4, 2); 1006 } 1007 1008 return ret; 1009 } 1010 1011 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 1012 { 1013 u32 ret; 1014 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 1015 u32 marker = 0; 1016 1017 ret = sfc_nand_read(addr, &marker, data_size, 2); 1018 1019 /* unify with mtd framework */ 1020 if (ret == SFC_NAND_ECC_ERROR || (u16)marker != 0xffff) 1021 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 1022 __func__, addr, ret, marker); 1023 1024 /* Original bad block */ 1025 if ((u16)marker != 0xffff) 1026 return true; 1027 1028 return false; 1029 } 1030 1031 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 1032 { 1033 u32 ret; 1034 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 1035 1036 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 1037 1038 if (ret) 1039 return SFC_NAND_HW_ERROR; 1040 1041 gp_page_buf[data_size / 4] = 0x0; 1042 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 1043 1044 if (ret) 1045 return SFC_NAND_HW_ERROR; 1046 1047 return ret; 1048 } 1049 1050 int sfc_nand_read_id(u8 *data) 1051 { 1052 int ret; 1053 struct rk_sfc_op op; 1054 1055 op.sfcmd.d32 = 0; 1056 op.sfcmd.b.cmd = CMD_READ_JEDECID; 1057 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 1058 1059 op.sfctrl.d32 = 0; 1060 op.sfctrl.b.addrbits = 8; 1061 1062 ret = sfc_request(&op, 0, data, 3); 1063 1064 return ret; 1065 } 1066 1067 /* 1068 * Read the 1st page's 1st byte of a phy_blk 1069 * If not FF, it's bad blk 1070 */ 1071 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 1072 { 1073 u32 bad_cnt, page; 1074 u32 blk_per_die; 1075 u16 blk; 1076 1077 rkflash_print_info("%s\n", __func__); 1078 1079 bad_cnt = 0; 1080 blk_per_die = p_nand_info->plane_per_die * 1081 p_nand_info->blk_per_plane; 1082 1083 for (blk = 0; blk < blk_per_die; blk++) { 1084 page = (blk + blk_per_die * die) * 1085 p_nand_info->page_per_blk; 1086 1087 if (sfc_nand_check_bad_block(die, page)) { 1088 table[bad_cnt++] = blk; 1089 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 1090 } 1091 } 1092 1093 return (int)bad_cnt; 1094 } 1095 1096 void sfc_nand_ftl_ops_init(void) 1097 { 1098 /* para init */ 1099 g_nand_phy_info.nand_type = 1; 1100 g_nand_phy_info.die_num = 1; 1101 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 1102 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 1103 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 1104 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 1105 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 1106 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 1107 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 1108 p_nand_info->page_per_blk; 1109 g_nand_phy_info.reserved_blk = 8; 1110 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 1111 p_nand_info->blk_per_plane; 1112 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 1113 1114 /* driver register */ 1115 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 1116 g_nand_ops.erase_blk = sfc_nand_erase_block; 1117 g_nand_ops.prog_page = sfc_nand_prog_page; 1118 g_nand_ops.read_page = sfc_nand_read_page; 1119 g_nand_ops.bch_sel = NULL; 1120 } 1121 1122 static int sfc_nand_enable_QE(void) 1123 { 1124 int ret = SFC_OK; 1125 u8 status; 1126 1127 ret = sfc_nand_read_feature(0xB0, &status); 1128 1129 if (ret != SFC_OK) 1130 return ret; 1131 1132 if (status & 1) /* is QE bit set */ 1133 return SFC_OK; 1134 1135 status |= 1; 1136 1137 return sfc_nand_write_feature(0xB0, status); 1138 } 1139 1140 u32 sfc_nand_init(void) 1141 { 1142 u8 status, id_byte[8]; 1143 1144 sfc_nand_read_id(id_byte); 1145 rkflash_print_error("sfc_nand id: %x %x %x\n", 1146 id_byte[0], id_byte[1], id_byte[2]); 1147 1148 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 1149 return (u32)FTL_NO_FLASH; 1150 1151 p_nand_info = sfc_nand_get_info(id_byte); 1152 1153 if (!p_nand_info) { 1154 pr_err("The device not support yet!\n"); 1155 1156 return (u32)FTL_UNSUPPORTED_FLASH; 1157 } 1158 1159 sfc_nand_dev.manufacturer = id_byte[0]; 1160 sfc_nand_dev.mem_type = id_byte[1]; 1161 sfc_nand_dev.capacity = p_nand_info->density; 1162 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 1163 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 1164 1165 /* disable block lock */ 1166 sfc_nand_write_feature(0xA0, 0); 1167 sfc_nand_dev.read_lines = DATA_LINES_X1; 1168 sfc_nand_dev.prog_lines = DATA_LINES_X1; 1169 sfc_nand_dev.page_read_cmd = 0x03; 1170 sfc_nand_dev.page_prog_cmd = 0x02; 1171 sfc_nand_dev.recheck_buffer = ftl_malloc(SFC_NAND_PAGE_MAX_SIZE); 1172 if (!sfc_nand_dev.recheck_buffer) { 1173 rkflash_print_error("%s recheck_buffer alloc failed\n", __func__); 1174 return -1; 1175 } 1176 1177 if (p_nand_info->feature & FEA_4BIT_READ) { 1178 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 1179 !p_nand_info->has_qe_bits) { 1180 sfc_nand_dev.read_lines = DATA_LINES_X4; 1181 sfc_nand_dev.page_read_cmd = 0x6b; 1182 } 1183 } 1184 1185 if (p_nand_info->feature & FEA_4BIT_PROG && 1186 sfc_nand_dev.read_lines == DATA_LINES_X4) { 1187 sfc_nand_dev.prog_lines = DATA_LINES_X4; 1188 sfc_nand_dev.page_prog_cmd = 0x32; 1189 } 1190 1191 sfc_nand_read_feature(0xA0, &status); 1192 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 1193 sfc_nand_read_feature(0xB0, &status); 1194 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 1195 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 1196 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 1197 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 1198 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 1199 1200 return SFC_OK; 1201 } 1202 1203 void sfc_nand_deinit(void) 1204 { 1205 /* to-do */ 1206 kfree(sfc_nand_dev.recheck_buffer); 1207 } 1208 1209 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 1210 { 1211 return &sfc_nand_dev; 1212 } 1213 1214