1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static struct nand_info spi_nand_tbl[] = { 18 /* TC58CVG0S0HxAIx */ 19 {0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xFF, 0xFF, 4, 8, NULL}, 20 /* TC58CVG1S0HxAIx */ 21 {0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xFF, 0xFF, 4, 8, NULL}, 22 /* MX35LF1GE4AB */ 23 {0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 24 /* MX35LF2GE4AB */ 25 {0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 26 /* GD5F1GQ4UAYIG */ 27 {0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, NULL}, 28 /* MT29F1G01ZAC */ 29 {0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 30 /* GD5F2GQ40BY2GR */ 31 {0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 32 /* GD5F1GQ4U */ 33 {0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 34 /* IS37SML01G1 */ 35 {0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xFF, 0xFF, 8, 12, &sfc_nand_ecc_status_sp1}, 36 /* W25N01GV */ 37 {0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 4, 20, &sfc_nand_ecc_status_sp1}, 38 /* HYF2GQ4UAACAE */ 39 {0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 40 /* HYF2GQ4UDACAE */ 41 {0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, NULL}, 42 /* HYF2GQ4UHCCAE */ 43 {0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 44 /* HYF1GQ4UDACAE */ 45 {0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, NULL}, 46 /* F50L1G41LB */ 47 {0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 20, 36, &sfc_nand_ecc_status_sp1}, 48 /* XT26G02A */ 49 {0x0BE2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 50 /* XT26G01A */ 51 {0x0BE1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 52 /* FS35ND01G-S1 */ 53 {0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 16, 20, &sfc_nand_ecc_status_sp5}, 54 /* FS35ND02G-S2 */ 55 {0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, 16, 20, &sfc_nand_ecc_status_sp5}, 56 /* DS35Q1GA-1B */ 57 {0xE571, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 58 /* DS35Q2GA-1B */ 59 {0xE572, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 60 /* EM73C044SNC-G */ 61 {0xD522, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0x0, 4, 20, NULL}, 62 /* EM73D044SNB-G */ 63 {0xD520, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0x0, 4, 20, NULL}, 64 /* ATO25D1GA */ 65 {0x9B12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x40, 18, 1, 0xB0, 0x0, 20, 36, &sfc_nand_ecc_status_sp1}, 66 /* XT26G02B */ 67 {0x0BF2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 68 /* XT26G01B */ 69 {0x0BF1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 70 /* HYF4GQ4UAACBE */ 71 {0xC9D4, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 4, 0xB0, 0, 32, 64, NULL}, 72 /* FM25S01 */ 73 {0xA1A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0, 0, 4, &sfc_nand_ecc_status_sp1}, 74 /* HYF1GQ4UPACAE */ 75 {0xC9A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp1}, 76 /* EM73E044SNA-G */ 77 {0xD503, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 8, 0xB0, 0, 4, 40, NULL}, 78 /* GD5F2GQ5UEYIG */ 79 {0xC852, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp2}, 80 }; 81 82 static u8 id_byte[8]; 83 static struct nand_info *p_nand_info; 84 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 85 static struct SFNAND_DEV sfc_nand_dev; 86 87 static struct nand_info *spi_nand_get_info(u8 *nand_id) 88 { 89 u32 i; 90 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 91 92 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 93 if (spi_nand_tbl[i].id == id) 94 return &spi_nand_tbl[i]; 95 } 96 return NULL; 97 } 98 99 static int sfc_nand_write_en(void) 100 { 101 int ret; 102 union SFCCMD_DATA sfcmd; 103 104 sfcmd.d32 = 0; 105 sfcmd.b.cmd = CMD_WRITE_EN; 106 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 107 return ret; 108 } 109 110 static int sfc_nand_rw_preset(void) 111 { 112 int ret; 113 union SFCCTRL_DATA sfctrl; 114 union SFCCMD_DATA sfcmd; 115 u8 status = 0xFF; 116 117 sfcmd.d32 = 0; 118 sfcmd.b.cmd = 0; 119 sfcmd.b.datasize = 1; 120 sfcmd.b.rw = SFC_WRITE; 121 122 sfctrl.b.datalines = 2; 123 ret = sfc_request(sfcmd.d32, sfctrl.d32, 0, &status); 124 return ret; 125 } 126 127 static int sfc_nand_read_feature(u8 addr, u8 *data) 128 { 129 int ret; 130 union SFCCMD_DATA sfcmd; 131 132 sfcmd.d32 = 0; 133 sfcmd.b.cmd = 0x0F; 134 sfcmd.b.datasize = 1; 135 sfcmd.b.addrbits = SFC_ADDR_XBITS; 136 *data = 0; 137 138 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, data); 139 if (ret != SFC_OK) 140 return ret; 141 return SFC_OK; 142 } 143 144 static int sfc_nand_write_feature(u32 addr, u8 status) 145 { 146 int ret; 147 union SFCCMD_DATA sfcmd; 148 149 sfc_nand_write_en(); 150 151 sfcmd.d32 = 0; 152 sfcmd.b.cmd = 0x1F; 153 sfcmd.b.datasize = 1; 154 sfcmd.b.addrbits = SFC_ADDR_XBITS; 155 sfcmd.b.rw = SFC_WRITE; 156 157 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, &status); 158 if (ret != SFC_OK) 159 return ret; 160 return ret; 161 } 162 163 static int sfc_nand_wait_busy(u8 *data, int timeout) 164 { 165 int ret; 166 int i; 167 u8 status; 168 169 *data = 0; 170 for (i = 0; i < timeout; i++) { 171 ret = sfc_nand_read_feature(0xC0, &status); 172 if (ret != SFC_OK) 173 return ret; 174 *data = status; 175 if (!(status & (1 << 0))) 176 return SFC_OK; 177 sfc_delay(1); 178 } 179 return -1; 180 } 181 182 /* 183 * ecc default: 184 * 0, No bit errors were detected 185 * 1, Bit errors were detected and corrected. 186 * 2, Multiple bit errors were detected and not corrected. 187 * 3, Bits errors were detected and corrected, bit error count 188 * exceed the bit flip detection threshold 189 */ 190 static u32 sfc_nand_ecc_status(void) 191 { 192 int ret; 193 u32 i; 194 u8 ecc; 195 u8 status; 196 u32 timeout = 1000 * 1000; 197 198 for (i = 0; i < timeout; i++) { 199 ret = sfc_nand_read_feature(0xC0, &status); 200 if (ret != SFC_OK) 201 return SFC_NAND_ECC_ERROR; 202 if (!(status & (1 << 0))) 203 break; 204 sfc_delay(1); 205 } 206 207 ecc = (status >> 4) & 0x03; 208 209 if (ecc <= 1) 210 ret = SFC_NAND_ECC_OK; 211 else if (ecc == 2) 212 ret = SFC_NAND_ECC_ERROR; 213 else 214 ret = SFC_NAND_ECC_REFRESH; 215 216 return ret; 217 } 218 219 /* 220 * ecc spectial type1: 221 * 0x00, No bit errors were detected; 222 * 0x01, Bits errors were detected and corrected, bit error count 223 * may reach the bit flip detection threshold; 224 * 0x10, Multiple bit errors were detected and not corrected; 225 * 0x11, Reserved. 226 */ 227 u32 sfc_nand_ecc_status_sp1(void) 228 { 229 int ret; 230 u32 i; 231 u8 ecc; 232 u8 status; 233 u32 timeout = 1000 * 1000; 234 235 for (i = 0; i < timeout; i++) { 236 ret = sfc_nand_read_feature(0xC0, &status); 237 if (ret != SFC_OK) 238 return SFC_NAND_ECC_ERROR; 239 if (!(status & (1 << 0))) 240 break; 241 sfc_delay(1); 242 } 243 244 ecc = (status >> 4) & 0x03; 245 246 if (ecc == 0) 247 ret = SFC_NAND_ECC_OK; 248 else if (ecc == 1) 249 ret = SFC_NAND_ECC_REFRESH; 250 else 251 ret = SFC_NAND_ECC_ERROR; 252 253 return ret; 254 } 255 256 /* 257 * ecc spectial type2: 258 * [0x0000, 0x0011], No bit errors were detected; 259 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 260 * reach Flipping Bits; 261 * [0x1000, 0x1011], Multiple bit errors were detected and 262 * not corrected; 263 * [0x1100, 0x1111], reserved. 264 */ 265 u32 sfc_nand_ecc_status_sp2(void) 266 { 267 int ret; 268 u32 i; 269 u8 ecc; 270 u8 status, status1; 271 u32 timeout = 1000 * 1000; 272 273 for (i = 0; i < timeout; i++) { 274 ret = sfc_nand_read_feature(0xC0, &status); 275 if (ret != SFC_OK) 276 return SFC_NAND_ECC_ERROR; 277 ret = sfc_nand_read_feature(0xF0, &status1); 278 if (ret != SFC_OK) 279 return SFC_NAND_ECC_ERROR; 280 if (!(status & (1 << 0))) 281 break; 282 sfc_delay(1); 283 } 284 285 ecc = (status >> 4) & 0x03; 286 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 287 if (ecc < 7) 288 ret = SFC_NAND_ECC_OK; 289 else if (ecc == 7) 290 ret = SFC_NAND_ECC_REFRESH; 291 else 292 ret = SFC_NAND_ECC_ERROR; 293 294 return ret; 295 } 296 297 /* 298 * ecc spectial type3: 299 * [0x0000, 0x0011], No bit errors were detected; 300 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 301 * reach Flipping Bits; 302 * [0x1000, 0x1011], Multiple bit errors were detected and 303 * not corrected. 304 * [0x1100, 0x1111], Bit error count equals the bit flip 305 * detectionthreshold 306 */ 307 u32 sfc_nand_ecc_status_sp3(void) 308 { 309 int ret; 310 u32 i; 311 u8 ecc; 312 u8 status, status1; 313 u32 timeout = 1000 * 1000; 314 315 for (i = 0; i < timeout; i++) { 316 ret = sfc_nand_read_feature(0xC0, &status); 317 if (ret != SFC_OK) 318 return SFC_NAND_ECC_ERROR; 319 ret = sfc_nand_read_feature(0xF0, &status1); 320 if (ret != SFC_OK) 321 return SFC_NAND_ECC_ERROR; 322 if (!(status & (1 << 0))) 323 break; 324 sfc_delay(1); 325 } 326 327 ecc = (status >> 4) & 0x03; 328 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 329 if (ecc < 7) 330 ret = SFC_NAND_ECC_OK; 331 else if (ecc == 7 || ecc >= 12) 332 ret = SFC_NAND_ECC_REFRESH; 333 else 334 ret = SFC_NAND_ECC_ERROR; 335 336 return ret; 337 } 338 339 /* 340 * ecc spectial type4: 341 * [0x0000], No bit errors were detected; 342 * [0x0001, 0x0111], Bit errors were detected and corrected. Not 343 * reach Flipping Bits; 344 * [0x1000], Multiple bit errors were detected and 345 * not corrected. 346 * [0x1100], Bit error count equals the bit flip 347 * detectionthreshold 348 * else, reserved 349 */ 350 u32 sfc_nand_ecc_status_sp4(void) 351 { 352 int ret; 353 u32 i; 354 u8 ecc; 355 u8 status; 356 u32 timeout = 1000 * 1000; 357 358 for (i = 0; i < timeout; i++) { 359 ret = sfc_nand_read_feature(0xC0, &status); 360 if (ret != SFC_OK) 361 return SFC_NAND_ECC_ERROR; 362 if (!(status & (1 << 0))) 363 break; 364 sfc_delay(1); 365 } 366 367 ecc = (status >> 2) & 0x0f; 368 if (ecc < 7) 369 ret = SFC_NAND_ECC_OK; 370 else if (ecc == 7 || ecc == 12) 371 ret = SFC_NAND_ECC_REFRESH; 372 else 373 ret = SFC_NAND_ECC_ERROR; 374 375 return ret; 376 } 377 378 /* 379 * ecc spectial type5: 380 * [0x0], No bit errors were detected; 381 * [0x001, 0x011], Bit errors were detected and corrected. Not 382 * reach Flipping Bits; 383 * [0x100], Bit error count equals the bit flip 384 * detectionthreshold 385 * [0x101, 0x110], Reserved; 386 * [0x111], Multiple bit errors were detected and 387 * not corrected. 388 */ 389 u32 sfc_nand_ecc_status_sp5(void) 390 { 391 int ret; 392 u32 i; 393 u8 ecc; 394 u8 status; 395 u32 timeout = 1000 * 1000; 396 397 for (i = 0; i < timeout; i++) { 398 ret = sfc_nand_read_feature(0xC0, &status); 399 if (ret != SFC_OK) 400 return SFC_NAND_ECC_ERROR; 401 if (!(status & (1 << 0))) 402 break; 403 sfc_delay(1); 404 } 405 406 ecc = (status >> 4) & 0x07; 407 if (ecc < 4) 408 ret = SFC_NAND_ECC_OK; 409 else if (ecc == 4) 410 ret = SFC_NAND_ECC_REFRESH; 411 else 412 ret = SFC_NAND_ECC_ERROR; 413 414 return ret; 415 } 416 417 static u32 sfc_nand_erase_block(u8 cs, u32 addr) 418 { 419 int ret; 420 union SFCCMD_DATA sfcmd; 421 u8 status; 422 423 sfcmd.d32 = 0; 424 sfcmd.b.cmd = p_nand_info->block_erase_cmd; 425 sfcmd.b.addrbits = SFC_ADDR_24BITS; 426 sfc_nand_write_en(); 427 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 428 if (ret != SFC_OK) 429 return ret; 430 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 431 if (status & (1 << 2)) 432 return SFC_NAND_PROG_ERASE_ERROR; 433 return ret; 434 } 435 436 static u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 437 { 438 int ret; 439 u32 plane; 440 union SFCCMD_DATA sfcmd; 441 union SFCCTRL_DATA sfctrl; 442 u8 status; 443 u32 sec_per_page = p_nand_info->sec_per_page; 444 u32 spare_offs_1 = p_nand_info->spare_offs_1; 445 u32 spare_offs_2 = p_nand_info->spare_offs_2; 446 u32 data_size = sec_per_page * 512; 447 448 PRINT_SFC_I("%s %x %x %x\n", __func__, addr, p_data[0], p_spare[0]); 449 memcpy(gp_page_buf, p_data, data_size); 450 ftl_memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 451 gp_page_buf[(data_size + spare_offs_1) / 4] = p_spare[0]; 452 gp_page_buf[(data_size + spare_offs_2) / 4] = p_spare[1]; 453 if (sec_per_page == 8) { 454 gp_page_buf[(data_size + spare_offs_1) / 4 + 1] = p_spare[2]; 455 gp_page_buf[(data_size + spare_offs_2) / 4 + 1] = p_spare[3]; 456 } 457 sfc_nand_write_en(); 458 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 459 p_nand_info->feature & FEA_SOFT_QOP_BIT && 460 sfc_get_version() < SFC_VER_3) 461 sfc_nand_rw_preset(); 462 463 sfcmd.d32 = 0; 464 sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 465 sfcmd.b.addrbits = SFC_ADDR_XBITS; 466 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 467 sfcmd.b.rw = SFC_WRITE; 468 469 sfctrl.d32 = 0; 470 sfctrl.b.datalines = sfc_nand_dev.prog_lines; 471 sfctrl.b.addrbits = 16; 472 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 473 sfc_request(sfcmd.d32, sfctrl.d32, plane, gp_page_buf); 474 475 sfcmd.d32 = 0; 476 sfcmd.b.cmd = p_nand_info->page_prog_cmd; 477 sfcmd.b.addrbits = SFC_ADDR_24BITS; 478 sfcmd.b.datasize = 0; 479 sfcmd.b.rw = SFC_WRITE; 480 ret = sfc_request(sfcmd.d32, 0, addr, p_data); 481 if (ret != SFC_OK) 482 return ret; 483 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 484 if (status & (1 << 3)) 485 return SFC_NAND_PROG_ERASE_ERROR; 486 return ret; 487 } 488 489 static u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 490 { 491 int ret; 492 u32 plane; 493 union SFCCMD_DATA sfcmd; 494 union SFCCTRL_DATA sfctrl; 495 u32 ecc_result; 496 u32 spare_offs_1 = p_nand_info->spare_offs_1; 497 u32 spare_offs_2 = p_nand_info->spare_offs_2; 498 u32 sec_per_page = p_nand_info->sec_per_page; 499 u32 data_size = sec_per_page * 512; 500 501 PRINT_SFC_I("%s %x %x %x\n", __func__, addr, p_data[0], p_spare[0]); 502 sfcmd.d32 = 0; 503 sfcmd.b.cmd = p_nand_info->page_read_cmd; 504 sfcmd.b.datasize = 0; 505 sfcmd.b.addrbits = SFC_ADDR_24BITS; 506 sfc_request(sfcmd.d32, 0, addr, p_data); 507 508 if (p_nand_info->ecc_status) 509 ecc_result = p_nand_info->ecc_status(); 510 else 511 ecc_result = sfc_nand_ecc_status(); 512 513 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 514 p_nand_info->feature & FEA_SOFT_QOP_BIT && 515 sfc_get_version() < SFC_VER_3) 516 sfc_nand_rw_preset(); 517 518 sfcmd.d32 = 0; 519 sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 520 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 521 sfcmd.b.addrbits = SFC_ADDR_24BITS; 522 sfctrl.d32 = 0; 523 sfctrl.b.datalines = sfc_nand_dev.read_lines; 524 525 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 526 ret = sfc_request(sfcmd.d32, sfctrl.d32, plane << 8, gp_page_buf); 527 memcpy(p_data, gp_page_buf, data_size); 528 p_spare[0] = gp_page_buf[(data_size + spare_offs_1) / 4]; 529 p_spare[1] = gp_page_buf[(data_size + spare_offs_2) / 4]; 530 if (p_nand_info->sec_per_page == 8) { 531 p_spare[2] = gp_page_buf[(data_size + spare_offs_1) / 4 + 1]; 532 p_spare[3] = gp_page_buf[(data_size + spare_offs_2) / 4 + 1]; 533 } 534 if (ret != SFC_OK) 535 return SFC_NAND_ECC_ERROR; 536 537 if (ecc_result != SFC_NAND_ECC_OK) { 538 PRINT_SFC_E("%s[0x%x], ret=0x%x\n", __func__, addr, ecc_result); 539 if (p_data) 540 PRINT_SFC_HEX("data:", p_data, 4, 8); 541 if (p_spare) 542 PRINT_SFC_HEX("spare:", p_spare, 4, 2); 543 } 544 545 return ecc_result; 546 } 547 548 static int sfc_nand_read_id_raw(u8 *data) 549 { 550 int ret; 551 union SFCCMD_DATA sfcmd; 552 553 sfcmd.d32 = 0; 554 sfcmd.b.cmd = CMD_READ_JEDECID; 555 sfcmd.b.datasize = 3; 556 sfcmd.b.addrbits = SFC_ADDR_XBITS; 557 558 ret = sfc_request(sfcmd.d32, 0x8 << 16, 0, data); 559 560 return ret; 561 } 562 563 /* 564 * Read the 1st page's 1st byte of a phy_blk 565 * If not FF, it's bad blk 566 */ 567 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 568 { 569 u16 blk; 570 u32 bad_cnt, page; 571 u32 blk_per_die; 572 u32 *pread; 573 u32 *pspare_read; 574 575 PRINT_SFC_E("%s\n", __func__); 576 pread = ftl_malloc(2048); 577 pspare_read = ftl_malloc(8); 578 bad_cnt = 0; 579 blk_per_die = p_nand_info->plane_per_die * 580 p_nand_info->blk_per_plane; 581 for (blk = 0; blk < blk_per_die; blk++) { 582 page = (blk + blk_per_die * die) * 583 p_nand_info->page_per_blk; 584 sfc_nand_read_page(0, page, pread, pspare_read); 585 586 if (pread[0] != 0xFFFFFFFF || 587 pspare_read[0] != 0xFFFFFFFF) { 588 table[bad_cnt++] = blk; 589 PRINT_SFC_E("die[%d], bad_blk[%d]\n", die, blk); 590 } 591 } 592 ftl_free(pread); 593 ftl_free(pspare_read); 594 return (int)bad_cnt; 595 } 596 597 #if SFC_NAND_STRESS_TEST_EN 598 599 #define SFC_NAND_PAGE_SIZE 2048 600 #define SFC_NAND_SPARE_SIZE 8 601 602 static u16 bad_blk_list[1024]; 603 static u32 pwrite[SFC_NAND_PAGE_SIZE / 4]; 604 static u32 pread[SFC_NAND_PAGE_SIZE / 4]; 605 static u32 pspare_write[SFC_NAND_SPARE_SIZE / 4]; 606 static u32 pspare_read[SFC_NAND_SPARE_SIZE / 4]; 607 static u32 bad_blk_num; 608 static u32 bad_page_num; 609 610 static void sfc_nand_test(void) 611 { 612 u32 i, blk, page, bad_cnt, page_addr; 613 int ret; 614 u32 pages_num = 64; 615 u32 blk_addr = 64; 616 u32 is_bad_blk = 0; 617 618 PRINT_SFC_E("%s\n", __func__); 619 620 bad_blk_num = 0; 621 bad_page_num = 0; 622 bad_cnt = sfc_nand_get_bad_block_list(bad_blk_list, 0); 623 624 for (blk = 0; blk < 1024; blk++) { 625 for (i = 0; i < bad_cnt; i++) { 626 if (bad_blk_list[i] == blk) 627 break; 628 } 629 if (i < bad_cnt) 630 continue; 631 is_bad_blk = 0; 632 PRINT_SFC_E("Flash prog block: %x\n", blk); 633 sfc_nand_erase_block(0, blk * blk_addr); 634 for (page = 0; page < pages_num; page++) { 635 page_addr = blk * blk_addr + page; 636 for (i = 0; i < 512; i++) 637 pwrite[i] = (page_addr << 16) + i; 638 pspare_write[0] = pwrite[0] + 0x5AF0; 639 pspare_write[1] = pspare_write[0] + 1; 640 sfc_nand_prog_page(0, page_addr, pwrite, pspare_write); 641 memset(pread, 0, 2048); 642 memset(pspare_read, 0, 8); 643 ret = sfc_nand_read_page(0, page_addr, pread, 644 pspare_read); 645 if (ret != SFC_NAND_ECC_OK) 646 is_bad_blk = 1; 647 for (i = 0; i < 512; i++) { 648 if (pwrite[i] != pread[i]) { 649 is_bad_blk = 1; 650 break; 651 } 652 } 653 for (i = 0; i < 2; i++) { 654 if (pspare_write[i] != pspare_read[i]) { 655 is_bad_blk = 1; 656 break; 657 } 658 } 659 if (is_bad_blk) { 660 bad_page_num++; 661 PRINT_SFC_E("ERR:page%x, ret=%x\n", 662 page_addr, ret); 663 PRINT_SFC_HEX("data:", pread, 4, 8); 664 PRINT_SFC_HEX("spare:", pspare_read, 4, 2); 665 } 666 } 667 sfc_nand_erase_block(0, blk * blk_addr); 668 if (is_bad_blk) 669 bad_blk_num++; 670 } 671 PRINT_SFC_E("bad_blk_num = %d, bad_page_num = %d\n", 672 bad_blk_num, bad_page_num); 673 674 PRINT_SFC_E("Flash Test Finish!!!\n"); 675 while (1) 676 ; 677 } 678 #endif 679 680 static void ftl_flash_init(void) 681 { 682 /* para init */ 683 g_nand_phy_info.nand_type = 1; 684 g_nand_phy_info.die_num = 1; 685 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 686 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 687 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 688 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 689 g_nand_phy_info.byte_per_sec = 512; 690 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 691 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 692 p_nand_info->page_per_blk; 693 g_nand_phy_info.reserved_blk = 8; 694 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 695 p_nand_info->blk_per_plane; 696 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 697 698 /* driver register */ 699 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 700 g_nand_ops.erase_blk = sfc_nand_erase_block; 701 g_nand_ops.prog_page = sfc_nand_prog_page; 702 g_nand_ops.read_page = sfc_nand_read_page; 703 g_nand_ops.bch_sel = NULL; 704 } 705 706 static int spi_nand_enable_QE(void) 707 { 708 int ret = SFC_OK; 709 u8 status; 710 int bit_offset = p_nand_info->QE_bits; 711 712 if (bit_offset == 0xFF) 713 return SFC_OK; 714 715 ret = sfc_nand_read_feature(p_nand_info->QE_address, &status); 716 if (ret != SFC_OK) 717 return ret; 718 719 if (status & (1 << bit_offset)) /* is QE bit set */ 720 return SFC_OK; 721 722 status |= (1 << bit_offset); 723 return sfc_nand_write_feature(p_nand_info->QE_address, status); 724 725 return ret; 726 } 727 728 u32 sfc_nand_init(void) 729 { 730 PRINT_SFC_I("...%s enter...\n", __func__); 731 732 sfc_nand_read_id_raw(id_byte); 733 PRINT_SFC_E("sfc_nand id: %x %x %x\n", 734 id_byte[0], id_byte[1], id_byte[2]); 735 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 736 return FTL_NO_FLASH; 737 738 p_nand_info = spi_nand_get_info(id_byte); 739 if (!p_nand_info) 740 return FTL_UNSUPPORTED_FLASH; 741 742 sfc_nand_dev.manufacturer = id_byte[0]; 743 sfc_nand_dev.mem_type = id_byte[1]; 744 745 /* disable block lock */ 746 sfc_nand_write_feature(0xA0, 0); 747 sfc_nand_dev.read_lines = DATA_LINES_X1; 748 sfc_nand_dev.prog_lines = DATA_LINES_X1; 749 sfc_nand_dev.page_read_cmd = p_nand_info->read_cache_cmd_1; 750 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_1; 751 if (p_nand_info->feature & FEA_4BIT_READ) { 752 if (spi_nand_enable_QE() == SFC_OK) { 753 sfc_nand_dev.read_lines = DATA_LINES_X4; 754 sfc_nand_dev.page_read_cmd = 755 p_nand_info->read_cache_cmd_4; 756 } 757 } 758 759 if (p_nand_info->feature & FEA_4BIT_PROG && 760 sfc_nand_dev.read_lines == DATA_LINES_X4) { 761 sfc_nand_dev.prog_lines = DATA_LINES_X4; 762 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_4; 763 } 764 765 if (1) { 766 u8 status; 767 768 sfc_nand_read_feature(0xA0, &status); 769 PRINT_SFC_I("sfc_nand A0 = 0x%x\n", status); 770 sfc_nand_read_feature(0xB0, &status); 771 PRINT_SFC_I("sfc_nand B0 = 0x%x\n", status); 772 sfc_nand_read_feature(0xC0, &status); 773 PRINT_SFC_I("sfc_nand C0 = 0x%x\n", status); 774 PRINT_SFC_I("read_lines = %x\n", sfc_nand_dev.read_lines); 775 PRINT_SFC_I("prog_lines = %x\n", sfc_nand_dev.prog_lines); 776 PRINT_SFC_I("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 777 PRINT_SFC_I("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 778 } 779 ftl_flash_init(); 780 781 #if SFC_NAND_STRESS_TEST_EN 782 sfc_nand_test(); 783 #endif 784 785 return SFC_OK; 786 } 787 788 int sfc_nand_read_id(u8 *data) 789 { 790 memcpy(data, id_byte, 3); 791 return 0; 792 } 793