1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static struct nand_info spi_nand_tbl[] = { 18 /* TC58CVG0S0HxAIx */ 19 {0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xFF, 0xFF, 4, 8, NULL}, 20 /* TC58CVG1S0HxAIx */ 21 {0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xFF, 0xFF, 4, 8, NULL}, 22 /* MX35LF1GE4AB */ 23 {0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 24 /* MX35LF2GE4AB */ 25 {0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 26 /* GD5F1GQ4UAYIG */ 27 {0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, NULL}, 28 /* MT29F1G01ZAC */ 29 {0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 30 /* GD5F2GQ40BY2GR */ 31 {0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 32 /* GD5F1GQ4U */ 33 {0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 34 /* IS37SML01G1 */ 35 {0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xFF, 0xFF, 8, 12, &sfc_nand_ecc_status_sp1}, 36 /* W25N01GV */ 37 {0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 4, 20, &sfc_nand_ecc_status_sp1}, 38 /* HYF2GQ4UAACAE */ 39 {0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 40 /* HYF2GQ4UDACAE */ 41 {0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, NULL}, 42 /* HYF2GQ4UHCCAE */ 43 {0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 44 /* HYF1GQ4UDACAE */ 45 {0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, NULL}, 46 /* F50L1G41LB */ 47 {0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 20, 36, &sfc_nand_ecc_status_sp1}, 48 /* XT26G02A */ 49 {0x0BE2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 50 /* XT26G01A */ 51 {0x0BE1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 52 /* FS35ND01G-S1 */ 53 {0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 16, 20, &sfc_nand_ecc_status_sp5}, 54 /* FS35ND02G-S2 */ 55 {0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, 16, 20, &sfc_nand_ecc_status_sp5}, 56 /* DS35Q1GA-1B */ 57 {0xE571, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 58 /* DS35Q2GA-1B */ 59 {0xE572, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 60 /* EM73C044SNC-G */ 61 {0xD522, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0x0, 4, 20, NULL}, 62 /* EM73D044SNB-G */ 63 {0xD520, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0x0, 4, 20, NULL}, 64 /* ATO25D1GA */ 65 {0x9B12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x40, 18, 1, 0xB0, 0x0, 20, 36, &sfc_nand_ecc_status_sp1}, 66 /* XT26G02B */ 67 {0x0BF2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 68 /* XT26G01B */ 69 {0x0BF1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 70 /* HYF4GQ4UAACBE */ 71 {0xC9D4, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 4, 0xB0, 0, 32, 64, NULL}, 72 /* FM25S01 */ 73 {0xA1A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0, 0, 4, &sfc_nand_ecc_status_sp1}, 74 /* HYF1GQ4UPACAE */ 75 {0xC9A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp1}, 76 /* EM73E044SNA-G */ 77 {0xD503, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 8, 0xB0, 0, 4, 40, NULL}, 78 /* GD5F2GQ5UEYIG */ 79 {0xC852, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp2}, 80 /* GD5F1GQ4R */ 81 {0xC8C1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 82 }; 83 84 static struct nand_info *p_nand_info; 85 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 86 static struct SFNAND_DEV sfc_nand_dev; 87 88 static struct nand_info *spi_nand_get_info(u8 *nand_id) 89 { 90 u32 i; 91 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 92 93 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 94 if (spi_nand_tbl[i].id == id) 95 return &spi_nand_tbl[i]; 96 } 97 return NULL; 98 } 99 100 static int sfc_nand_write_en(void) 101 { 102 int ret; 103 union SFCCMD_DATA sfcmd; 104 105 sfcmd.d32 = 0; 106 sfcmd.b.cmd = CMD_WRITE_EN; 107 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 108 return ret; 109 } 110 111 static int sfc_nand_rw_preset(void) 112 { 113 int ret; 114 union SFCCTRL_DATA sfctrl; 115 union SFCCMD_DATA sfcmd; 116 u8 status = 0xFF; 117 118 sfcmd.d32 = 0; 119 sfcmd.b.cmd = 0; 120 sfcmd.b.datasize = 1; 121 sfcmd.b.rw = SFC_WRITE; 122 123 sfctrl.b.datalines = 2; 124 ret = sfc_request(sfcmd.d32, sfctrl.d32, 0, &status); 125 return ret; 126 } 127 128 static int sfc_nand_read_feature(u8 addr, u8 *data) 129 { 130 int ret; 131 union SFCCMD_DATA sfcmd; 132 133 sfcmd.d32 = 0; 134 sfcmd.b.cmd = 0x0F; 135 sfcmd.b.datasize = 1; 136 sfcmd.b.addrbits = SFC_ADDR_XBITS; 137 *data = 0; 138 139 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, data); 140 if (ret != SFC_OK) 141 return ret; 142 return SFC_OK; 143 } 144 145 static int sfc_nand_write_feature(u32 addr, u8 status) 146 { 147 int ret; 148 union SFCCMD_DATA sfcmd; 149 150 sfc_nand_write_en(); 151 152 sfcmd.d32 = 0; 153 sfcmd.b.cmd = 0x1F; 154 sfcmd.b.datasize = 1; 155 sfcmd.b.addrbits = SFC_ADDR_XBITS; 156 sfcmd.b.rw = SFC_WRITE; 157 158 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, &status); 159 if (ret != SFC_OK) 160 return ret; 161 return ret; 162 } 163 164 static int sfc_nand_wait_busy(u8 *data, int timeout) 165 { 166 int ret; 167 int i; 168 u8 status; 169 170 *data = 0; 171 for (i = 0; i < timeout; i++) { 172 ret = sfc_nand_read_feature(0xC0, &status); 173 if (ret != SFC_OK) 174 return ret; 175 *data = status; 176 if (!(status & (1 << 0))) 177 return SFC_OK; 178 sfc_delay(1); 179 } 180 return -1; 181 } 182 183 /* 184 * ecc default: 185 * 0x00, No bit errors were detected 186 * 0x01, Bit errors were detected and corrected. 187 * 0x10, Multiple bit errors were detected and not corrected. 188 * 0x11, Bits errors were detected and corrected, bit error count 189 * exceed the bit flip detection threshold 190 */ 191 static u32 sfc_nand_ecc_status(void) 192 { 193 int ret; 194 u32 i; 195 u8 ecc; 196 u8 status; 197 u32 timeout = 1000 * 1000; 198 199 for (i = 0; i < timeout; i++) { 200 ret = sfc_nand_read_feature(0xC0, &status); 201 if (ret != SFC_OK) 202 return SFC_NAND_ECC_ERROR; 203 if (!(status & (1 << 0))) 204 break; 205 sfc_delay(1); 206 } 207 208 ecc = (status >> 4) & 0x03; 209 210 if (ecc <= 1) 211 ret = SFC_NAND_ECC_OK; 212 else if (ecc == 2) 213 ret = SFC_NAND_ECC_ERROR; 214 else 215 ret = SFC_NAND_ECC_REFRESH; 216 217 return ret; 218 } 219 220 /* 221 * ecc spectial type1: 222 * 0x00, No bit errors were detected; 223 * 0x01, Bits errors were detected and corrected, bit error count 224 * may reach the bit flip detection threshold; 225 * 0x10, Multiple bit errors were detected and not corrected; 226 * 0x11, Reserved. 227 */ 228 u32 sfc_nand_ecc_status_sp1(void) 229 { 230 int ret; 231 u32 i; 232 u8 ecc; 233 u8 status; 234 u32 timeout = 1000 * 1000; 235 236 for (i = 0; i < timeout; i++) { 237 ret = sfc_nand_read_feature(0xC0, &status); 238 if (ret != SFC_OK) 239 return SFC_NAND_ECC_ERROR; 240 if (!(status & (1 << 0))) 241 break; 242 sfc_delay(1); 243 } 244 245 ecc = (status >> 4) & 0x03; 246 247 if (ecc == 0) 248 ret = SFC_NAND_ECC_OK; 249 else if (ecc == 1) 250 ret = SFC_NAND_ECC_REFRESH; 251 else 252 ret = SFC_NAND_ECC_ERROR; 253 254 return ret; 255 } 256 257 /* 258 * ecc spectial type2: 259 * [0x0000, 0x0011], No bit errors were detected; 260 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 261 * reach Flipping Bits; 262 * [0x1000, 0x1011], Multiple bit errors were detected and 263 * not corrected. 264 * [0x1100, 0x1111], reserved. 265 */ 266 u32 sfc_nand_ecc_status_sp2(void) 267 { 268 int ret; 269 u32 i; 270 u8 ecc; 271 u8 status, status1; 272 u32 timeout = 1000 * 1000; 273 274 for (i = 0; i < timeout; i++) { 275 ret = sfc_nand_read_feature(0xC0, &status); 276 if (ret != SFC_OK) 277 return SFC_NAND_ECC_ERROR; 278 ret = sfc_nand_read_feature(0xF0, &status1); 279 if (ret != SFC_OK) 280 return SFC_NAND_ECC_ERROR; 281 if (!(status & (1 << 0))) 282 break; 283 sfc_delay(1); 284 } 285 286 ecc = (status >> 4) & 0x03; 287 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 288 if (ecc < 7) 289 ret = SFC_NAND_ECC_OK; 290 else if (ecc == 7) 291 ret = SFC_NAND_ECC_REFRESH; 292 else 293 ret = SFC_NAND_ECC_ERROR; 294 295 return ret; 296 } 297 298 /* 299 * ecc spectial type3: 300 * [0x0000, 0x0011], No bit errors were detected; 301 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 302 * reach Flipping Bits; 303 * [0x1000, 0x1011], Multiple bit errors were detected and 304 * not corrected. 305 * [0x1100, 0x1111], Bit error count equals the bit flip 306 * detectionthreshold 307 */ 308 u32 sfc_nand_ecc_status_sp3(void) 309 { 310 int ret; 311 u32 i; 312 u8 ecc; 313 u8 status, status1; 314 u32 timeout = 1000 * 1000; 315 316 for (i = 0; i < timeout; i++) { 317 ret = sfc_nand_read_feature(0xC0, &status); 318 if (ret != SFC_OK) 319 return SFC_NAND_ECC_ERROR; 320 ret = sfc_nand_read_feature(0xF0, &status1); 321 if (ret != SFC_OK) 322 return SFC_NAND_ECC_ERROR; 323 if (!(status & (1 << 0))) 324 break; 325 sfc_delay(1); 326 } 327 328 ecc = (status >> 4) & 0x03; 329 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 330 if (ecc < 7) 331 ret = SFC_NAND_ECC_OK; 332 else if (ecc == 7 || ecc >= 12) 333 ret = SFC_NAND_ECC_REFRESH; 334 else 335 ret = SFC_NAND_ECC_ERROR; 336 337 return ret; 338 } 339 340 /* 341 * ecc spectial type4: 342 * [0x0000], No bit errors were detected; 343 * [0x0001, 0x0111], Bit errors were detected and corrected. Not 344 * reach Flipping Bits; 345 * [0x1000], Multiple bit errors were detected and 346 * not corrected. 347 * [0x1100], Bit error count equals the bit flip 348 * detectionthreshold 349 * else, reserved 350 */ 351 u32 sfc_nand_ecc_status_sp4(void) 352 { 353 int ret; 354 u32 i; 355 u8 ecc; 356 u8 status; 357 u32 timeout = 1000 * 1000; 358 359 for (i = 0; i < timeout; i++) { 360 ret = sfc_nand_read_feature(0xC0, &status); 361 if (ret != SFC_OK) 362 return SFC_NAND_ECC_ERROR; 363 if (!(status & (1 << 0))) 364 break; 365 sfc_delay(1); 366 } 367 368 ecc = (status >> 2) & 0x0f; 369 if (ecc < 7) 370 ret = SFC_NAND_ECC_OK; 371 else if (ecc == 7 || ecc == 12) 372 ret = SFC_NAND_ECC_REFRESH; 373 else 374 ret = SFC_NAND_ECC_ERROR; 375 376 return ret; 377 } 378 379 /* 380 * ecc spectial type5: 381 * [0x0], No bit errors were detected; 382 * [0x001, 0x011], Bit errors were detected and corrected. Not 383 * reach Flipping Bits; 384 * [0x100], Bit error count equals the bit flip 385 * detectionthreshold 386 * [0x101, 0x110], Reserved; 387 * [0x111], Multiple bit errors were detected and 388 * not corrected. 389 */ 390 u32 sfc_nand_ecc_status_sp5(void) 391 { 392 int ret; 393 u32 i; 394 u8 ecc; 395 u8 status; 396 u32 timeout = 1000 * 1000; 397 398 for (i = 0; i < timeout; i++) { 399 ret = sfc_nand_read_feature(0xC0, &status); 400 if (ret != SFC_OK) 401 return SFC_NAND_ECC_ERROR; 402 if (!(status & (1 << 0))) 403 break; 404 sfc_delay(1); 405 } 406 407 ecc = (status >> 4) & 0x07; 408 if (ecc < 4) 409 ret = SFC_NAND_ECC_OK; 410 else if (ecc == 4) 411 ret = SFC_NAND_ECC_REFRESH; 412 else 413 ret = SFC_NAND_ECC_ERROR; 414 415 return ret; 416 } 417 418 u32 sfc_nand_erase_block(u8 cs, u32 addr) 419 { 420 int ret; 421 union SFCCMD_DATA sfcmd; 422 u8 status; 423 424 rkflash_print_dio("%s %x\n", __func__, addr); 425 sfcmd.d32 = 0; 426 sfcmd.b.cmd = p_nand_info->block_erase_cmd; 427 sfcmd.b.addrbits = SFC_ADDR_24BITS; 428 sfc_nand_write_en(); 429 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 430 if (ret != SFC_OK) 431 return ret; 432 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 433 if (status & (1 << 2)) 434 return SFC_NAND_PROG_ERASE_ERROR; 435 436 return ret; 437 } 438 439 static u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 440 { 441 int ret; 442 u32 plane; 443 union SFCCMD_DATA sfcmd; 444 union SFCCTRL_DATA sfctrl; 445 u8 status; 446 u32 sec_per_page = p_nand_info->sec_per_page; 447 448 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 449 sfc_nand_write_en(); 450 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 451 p_nand_info->feature & FEA_SOFT_QOP_BIT && 452 sfc_get_version() < SFC_VER_3) 453 sfc_nand_rw_preset(); 454 455 sfcmd.d32 = 0; 456 sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 457 sfcmd.b.addrbits = SFC_ADDR_XBITS; 458 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 459 sfcmd.b.rw = SFC_WRITE; 460 461 sfctrl.d32 = 0; 462 sfctrl.b.datalines = sfc_nand_dev.prog_lines; 463 sfctrl.b.addrbits = 16; 464 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 465 sfc_request(sfcmd.d32, sfctrl.d32, plane, p_page_buf); 466 467 sfcmd.d32 = 0; 468 sfcmd.b.cmd = p_nand_info->page_prog_cmd; 469 sfcmd.b.addrbits = SFC_ADDR_24BITS; 470 sfcmd.b.datasize = 0; 471 sfcmd.b.rw = SFC_WRITE; 472 ret = sfc_request(sfcmd.d32, 0, addr, p_page_buf); 473 if (ret != SFC_OK) 474 return ret; 475 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 476 if (status & (1 << 3)) 477 return SFC_NAND_PROG_ERASE_ERROR; 478 479 return ret; 480 } 481 482 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 483 { 484 int ret; 485 u32 sec_per_page = p_nand_info->sec_per_page; 486 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 487 u32 spare_offs_1 = p_nand_info->spare_offs_1; 488 u32 spare_offs_2 = p_nand_info->spare_offs_2; 489 490 memcpy(gp_page_buf, p_data, data_size); 491 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 492 gp_page_buf[(data_size + spare_offs_1) / 4] = p_spare[0]; 493 gp_page_buf[(data_size + spare_offs_2) / 4] = p_spare[1]; 494 if (sec_per_page == 8) { 495 gp_page_buf[(data_size + spare_offs_1) / 4 + 1] = p_spare[2]; 496 gp_page_buf[(data_size + spare_offs_2) / 4 + 1] = p_spare[3]; 497 } 498 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 499 500 return ret; 501 } 502 503 static u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 504 { 505 int ret; 506 u32 plane; 507 union SFCCMD_DATA sfcmd; 508 union SFCCTRL_DATA sfctrl; 509 u32 ecc_result; 510 u32 sec_per_page = p_nand_info->sec_per_page; 511 512 sfcmd.d32 = 0; 513 sfcmd.b.cmd = p_nand_info->page_read_cmd; 514 sfcmd.b.datasize = 0; 515 sfcmd.b.addrbits = SFC_ADDR_24BITS; 516 sfc_request(sfcmd.d32, 0, addr, p_page_buf); 517 518 if (p_nand_info->ecc_status) 519 ecc_result = p_nand_info->ecc_status(); 520 else 521 ecc_result = sfc_nand_ecc_status(); 522 523 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 524 p_nand_info->feature & FEA_SOFT_QOP_BIT && 525 sfc_get_version() < SFC_VER_3) 526 sfc_nand_rw_preset(); 527 528 sfcmd.d32 = 0; 529 sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 530 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 531 sfcmd.b.addrbits = SFC_ADDR_24BITS; 532 sfctrl.d32 = 0; 533 sfctrl.b.datalines = sfc_nand_dev.read_lines; 534 535 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 536 ret = sfc_request(sfcmd.d32, sfctrl.d32, plane << 8, p_page_buf); 537 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 538 539 if (ret != SFC_OK) 540 return SFC_NAND_HW_ERROR; 541 542 return ecc_result; 543 } 544 545 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 546 { 547 int ret; 548 u32 sec_per_page = p_nand_info->sec_per_page; 549 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 550 u32 spare_offs_1 = p_nand_info->spare_offs_1; 551 u32 spare_offs_2 = p_nand_info->spare_offs_2; 552 553 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 554 memcpy(p_data, gp_page_buf, data_size); 555 p_spare[0] = gp_page_buf[(data_size + spare_offs_1) / 4]; 556 p_spare[1] = gp_page_buf[(data_size + spare_offs_2) / 4]; 557 if (p_nand_info->sec_per_page == 8) { 558 p_spare[2] = gp_page_buf[(data_size + spare_offs_1) / 4 + 1]; 559 p_spare[3] = gp_page_buf[(data_size + spare_offs_2) / 4 + 1]; 560 } 561 562 if (ret != SFC_NAND_ECC_OK) { 563 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 564 if (p_data) 565 rkflash_print_hex("data:", p_data, 4, 8); 566 if (p_spare) 567 rkflash_print_hex("spare:", p_spare, 4, 2); 568 } 569 570 return ret; 571 } 572 573 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 574 { 575 u32 ret; 576 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 577 578 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 579 if (ret) 580 return true; 581 /* Original bad block */ 582 if ((gp_page_buf[data_size / 4] & 0xFF) != 0xFF) 583 return true; 584 585 return false; 586 } 587 588 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 589 { 590 u32 ret; 591 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 592 593 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 594 if (ret) 595 return SFC_NAND_HW_ERROR; 596 gp_page_buf[data_size / 4] = 0x0; 597 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 598 if (ret) 599 return SFC_NAND_HW_ERROR; 600 601 return ret; 602 } 603 604 int sfc_nand_read_id(u8 *data) 605 { 606 int ret; 607 union SFCCMD_DATA sfcmd; 608 609 sfcmd.d32 = 0; 610 sfcmd.b.cmd = CMD_READ_JEDECID; 611 sfcmd.b.datasize = 3; 612 sfcmd.b.addrbits = SFC_ADDR_XBITS; 613 614 ret = sfc_request(sfcmd.d32, 0x8 << 16, 0, data); 615 616 return ret; 617 } 618 619 /* 620 * Read the 1st page's 1st byte of a phy_blk 621 * If not FF, it's bad blk 622 */ 623 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 624 { 625 u16 blk; 626 u32 bad_cnt, page; 627 u32 blk_per_die; 628 u32 *pread; 629 u32 *pspare_read; 630 631 rkflash_print_info("%s\n", __func__); 632 pread = ftl_malloc(SFC_NAND_PAGE_MAX_SIZE); 633 pspare_read = ftl_malloc(8); 634 if (!pread || !pspare_read) { 635 kfree(pread); 636 kfree(pspare_read); 637 return -1; 638 } 639 640 bad_cnt = 0; 641 blk_per_die = p_nand_info->plane_per_die * 642 p_nand_info->blk_per_plane; 643 for (blk = 0; blk < blk_per_die; blk++) { 644 page = (blk + blk_per_die * die) * 645 p_nand_info->page_per_blk; 646 sfc_nand_read_page(0, page, pread, pspare_read); 647 648 if (pread[0] != 0xFFFFFFFF || 649 pspare_read[0] != 0xFFFFFFFF) { 650 table[bad_cnt++] = blk; 651 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 652 } 653 } 654 ftl_free(pread); 655 ftl_free(pspare_read); 656 657 return (int)bad_cnt; 658 } 659 660 void sfc_nand_ftl_ops_init(void) 661 { 662 /* para init */ 663 g_nand_phy_info.nand_type = 1; 664 g_nand_phy_info.die_num = 1; 665 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 666 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 667 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 668 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 669 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 670 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 671 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 672 p_nand_info->page_per_blk; 673 g_nand_phy_info.reserved_blk = 8; 674 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 675 p_nand_info->blk_per_plane; 676 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 677 678 /* driver register */ 679 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 680 g_nand_ops.erase_blk = sfc_nand_erase_block; 681 g_nand_ops.prog_page = sfc_nand_prog_page; 682 g_nand_ops.read_page = sfc_nand_read_page; 683 g_nand_ops.bch_sel = NULL; 684 } 685 686 static int spi_nand_enable_QE(void) 687 { 688 int ret = SFC_OK; 689 u8 status; 690 int bit_offset = p_nand_info->QE_bits; 691 692 if (bit_offset == 0xFF) 693 return SFC_OK; 694 695 ret = sfc_nand_read_feature(p_nand_info->QE_address, &status); 696 if (ret != SFC_OK) 697 return ret; 698 699 if (status & (1 << bit_offset)) /* is QE bit set */ 700 return SFC_OK; 701 702 status |= (1 << bit_offset); 703 return sfc_nand_write_feature(p_nand_info->QE_address, status); 704 705 return ret; 706 } 707 708 u32 sfc_nand_init(void) 709 { 710 u8 status, id_byte[8]; 711 712 sfc_nand_read_id(id_byte); 713 rkflash_print_error("sfc_nand id: %x %x %x\n", 714 id_byte[0], id_byte[1], id_byte[2]); 715 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 716 return FTL_NO_FLASH; 717 718 p_nand_info = spi_nand_get_info(id_byte); 719 if (!p_nand_info) 720 return FTL_UNSUPPORTED_FLASH; 721 722 sfc_nand_dev.manufacturer = id_byte[0]; 723 sfc_nand_dev.mem_type = id_byte[1]; 724 sfc_nand_dev.capacity = p_nand_info->density; 725 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 726 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 727 728 /* disable block lock */ 729 sfc_nand_write_feature(0xA0, 0); 730 sfc_nand_dev.read_lines = DATA_LINES_X1; 731 sfc_nand_dev.prog_lines = DATA_LINES_X1; 732 sfc_nand_dev.page_read_cmd = p_nand_info->read_cache_cmd_1; 733 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_1; 734 if (p_nand_info->feature & FEA_4BIT_READ) { 735 if (spi_nand_enable_QE() == SFC_OK) { 736 sfc_nand_dev.read_lines = DATA_LINES_X4; 737 sfc_nand_dev.page_read_cmd = 738 p_nand_info->read_cache_cmd_4; 739 } 740 } 741 742 if (p_nand_info->feature & FEA_4BIT_PROG && 743 sfc_nand_dev.read_lines == DATA_LINES_X4) { 744 sfc_nand_dev.prog_lines = DATA_LINES_X4; 745 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_4; 746 } 747 748 sfc_nand_read_feature(0xA0, &status); 749 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 750 sfc_nand_read_feature(0xB0, &status); 751 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 752 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 753 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 754 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 755 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 756 757 return SFC_OK; 758 } 759 760 void sfc_nand_deinit(void) 761 { 762 /* to-do */ 763 } 764 765 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 766 { 767 return &sfc_nand_dev; 768 } 769 770