1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 25 static struct nand_info spi_nand_tbl[] = { 26 /* TC58CVG0S0HxAIx */ 27 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 28 /* TC58CVG1S0HxAIx */ 29 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 30 /* TC58CVG2S0HRAIJ */ 31 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 32 /* TC58CVG1S3HRAIJ */ 33 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 34 /* TC58CVG0S3HRAIJ */ 35 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 36 37 /* MX35LF1GE4AB */ 38 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 39 /* MX35LF2GE4AB */ 40 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 41 /* MX35LF2GE4AD */ 42 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 43 /* MX35LF4GE4AD */ 44 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 45 /* MT29F1G01ZAC */ 46 { 0x2C, 0x12, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 47 48 /* GD5F1GQ4UAYIG */ 49 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 50 /* GD5F1GQ4RB9IGR */ 51 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 52 /* GD5F2GQ40BY2GR */ 53 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 54 /* GD5F1GQ5UEYIG */ 55 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 56 /* GD5F2GQ5UEYIG */ 57 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 58 /* GD5F1GQ4R */ 59 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 60 61 /* W25N01GV */ 62 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 63 /* W25N02KVZEIR */ 64 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 65 /* W25N01GW */ 66 { 0xEF, 0xBA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 67 68 /* HYF2GQ4UAACAE */ 69 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 70 /* HYF1GQ4UDACAE */ 71 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 72 /* HYF1GQ4UPACAE */ 73 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 74 /* HYF2GQ4UDACAE */ 75 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 76 /* HYF2GQ4UHCCAE */ 77 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 78 /* HYF4GQ4UAACBE */ 79 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 80 81 /* FS35ND01G-S1 */ 82 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 83 /* FS35ND02G-S2 */ 84 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 85 /* FS35ND01G-S1Y2 */ 86 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 87 /* FS35ND02G-S3Y2 */ 88 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 89 /* FS35ND04G-S2Y2 1*4096 */ 90 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 91 92 /* DS35Q1GA-IB */ 93 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 94 /* DS35Q2GA-IB */ 95 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 96 /* DS35M1GA-1B */ 97 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 98 99 /* EM73C044VCC-H */ 100 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 101 /* EM73D044VCE-H */ 102 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 103 /* EM73E044SNA-G */ 104 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 105 106 /* XT26G02A */ 107 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 108 /* XT26G01A */ 109 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 110 /* XT26G04A */ 111 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 112 /* XT26G01B */ 113 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 114 /* XT26G02B */ 115 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 116 117 /* MT29F2G1ABA, XT26G02E, F50L2G41XA */ 118 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 119 120 /* FM25S01 */ 121 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 122 /* FM25S01A */ 123 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 124 /* FM25S02A */ 125 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 126 127 /* IS37SML01G1 */ 128 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 129 /* F50L1G41LB */ 130 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 131 /* ATO25D1GA */ 132 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 133 }; 134 135 static struct nand_info *p_nand_info; 136 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 137 static struct SFNAND_DEV sfc_nand_dev; 138 139 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 140 { 141 u32 i; 142 143 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 144 if (spi_nand_tbl[i].id0 == nand_id[0] && 145 spi_nand_tbl[i].id1 == nand_id[1]) { 146 if (spi_nand_tbl[i].id2 && 147 spi_nand_tbl[i].id2 != nand_id[2]) 148 continue; 149 150 return &spi_nand_tbl[i]; 151 } 152 } 153 154 return NULL; 155 } 156 157 static int sfc_nand_write_en(void) 158 { 159 int ret; 160 struct rk_sfc_op op; 161 162 op.sfcmd.d32 = 0; 163 op.sfcmd.b.cmd = CMD_WRITE_EN; 164 165 op.sfctrl.d32 = 0; 166 167 ret = sfc_request(&op, 0, NULL, 0); 168 return ret; 169 } 170 171 static int sfc_nand_rw_preset(void) 172 { 173 int ret; 174 struct rk_sfc_op op; 175 176 op.sfcmd.d32 = 0; 177 op.sfcmd.b.cmd = 0xff; 178 op.sfcmd.b.cs = 2; 179 180 op.sfctrl.d32 = 0; 181 op.sfctrl.b.datalines = 2; 182 op.sfctrl.b.cmdlines = 2; 183 op.sfctrl.b.addrlines = 2; 184 185 ret = sfc_request(&op, 0, NULL, 0); 186 return ret; 187 } 188 189 static int sfc_nand_read_feature(u8 addr, u8 *data) 190 { 191 int ret; 192 struct rk_sfc_op op; 193 194 op.sfcmd.d32 = 0; 195 op.sfcmd.b.cmd = 0x0F; 196 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 197 198 op.sfctrl.d32 = 0; 199 op.sfctrl.b.addrbits = 8; 200 201 *data = 0; 202 203 ret = sfc_request(&op, addr, data, 1); 204 205 if (ret != SFC_OK) 206 return ret; 207 208 return SFC_OK; 209 } 210 211 static int sfc_nand_write_feature(u32 addr, u8 status) 212 { 213 int ret; 214 struct rk_sfc_op op; 215 216 sfc_nand_write_en(); 217 218 op.sfcmd.d32 = 0; 219 op.sfcmd.b.cmd = 0x1F; 220 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 221 op.sfcmd.b.rw = SFC_WRITE; 222 223 op.sfctrl.d32 = 0; 224 op.sfctrl.b.addrbits = 8; 225 226 ret = sfc_request(&op, addr, &status, 1); 227 228 if (ret != SFC_OK) 229 return ret; 230 231 return ret; 232 } 233 234 static int sfc_nand_wait_busy(u8 *data, int timeout) 235 { 236 int ret; 237 int i; 238 u8 status; 239 240 *data = 0; 241 242 for (i = 0; i < timeout; i++) { 243 ret = sfc_nand_read_feature(0xC0, &status); 244 245 if (ret != SFC_OK) 246 return ret; 247 248 *data = status; 249 250 if (!(status & (1 << 0))) 251 return SFC_OK; 252 253 sfc_delay(1); 254 } 255 256 return SFC_NAND_WAIT_TIME_OUT; 257 } 258 259 /* 260 * ecc default: 261 * ecc bits: 0xC0[4,5] 262 * 0b00, No bit errors were detected 263 * 0b01, Bit errors were detected and corrected. 264 * 0b10, Multiple bit errors were detected and not corrected. 265 * 0b11, Bits errors were detected and corrected, bit error count 266 * exceed the bit flip detection threshold 267 */ 268 static u32 sfc_nand_get_ecc_status0(void) 269 { 270 u32 ret; 271 u32 i; 272 u8 ecc; 273 u8 status; 274 u32 timeout = 1000 * 1000; 275 276 for (i = 0; i < timeout; i++) { 277 ret = sfc_nand_read_feature(0xC0, &status); 278 279 if (ret != SFC_OK) 280 return SFC_NAND_ECC_ERROR; 281 282 if (!(status & (1 << 0))) 283 break; 284 285 sfc_delay(1); 286 } 287 288 ecc = (status >> 4) & 0x03; 289 290 if (ecc <= 1) 291 ret = SFC_NAND_ECC_OK; 292 else if (ecc == 2) 293 ret = (u32)SFC_NAND_ECC_ERROR; 294 else 295 ret = SFC_NAND_ECC_REFRESH; 296 297 return ret; 298 } 299 300 /* 301 * ecc spectial type1: 302 * ecc bits: 0xC0[4,5] 303 * 0b00, No bit errors were detected; 304 * 0b01, Bits errors were detected and corrected, bit error count 305 * may reach the bit flip detection threshold; 306 * 0b10, Multiple bit errors were detected and not corrected; 307 * 0b11, Reserved. 308 */ 309 static u32 sfc_nand_get_ecc_status1(void) 310 { 311 u32 ret; 312 u32 i; 313 u8 ecc; 314 u8 status; 315 u32 timeout = 1000 * 1000; 316 317 for (i = 0; i < timeout; i++) { 318 ret = sfc_nand_read_feature(0xC0, &status); 319 320 if (ret != SFC_OK) 321 return SFC_NAND_ECC_ERROR; 322 323 if (!(status & (1 << 0))) 324 break; 325 326 sfc_delay(1); 327 } 328 329 ecc = (status >> 4) & 0x03; 330 331 if (ecc == 0) 332 ret = SFC_NAND_ECC_OK; 333 else if (ecc == 1) 334 ret = SFC_NAND_ECC_REFRESH; 335 else 336 ret = (u32)SFC_NAND_ECC_ERROR; 337 338 return ret; 339 } 340 341 /* 342 * ecc spectial type2: 343 * ecc bits: 0xC0[4,5] 0xF0[4,5] 344 * [0b0000, 0b0011], No bit errors were detected; 345 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 346 * reach Flipping Bits; 347 * [0b1000, 0b1011], Multiple bit errors were detected and 348 * not corrected. 349 * [0b1100, 0b1111], reserved. 350 */ 351 static u32 sfc_nand_get_ecc_status2(void) 352 { 353 u32 ret; 354 u32 i; 355 u8 ecc; 356 u8 status, status1; 357 u32 timeout = 1000 * 1000; 358 359 for (i = 0; i < timeout; i++) { 360 ret = sfc_nand_read_feature(0xC0, &status); 361 362 if (ret != SFC_OK) 363 return SFC_NAND_ECC_ERROR; 364 365 ret = sfc_nand_read_feature(0xF0, &status1); 366 367 if (ret != SFC_OK) 368 return SFC_NAND_ECC_ERROR; 369 370 if (!(status & (1 << 0))) 371 break; 372 373 sfc_delay(1); 374 } 375 376 ecc = (status >> 4) & 0x03; 377 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 378 379 if (ecc < 7) 380 ret = SFC_NAND_ECC_OK; 381 else if (ecc == 7) 382 ret = SFC_NAND_ECC_REFRESH; 383 else 384 ret = (u32)SFC_NAND_ECC_ERROR; 385 386 return ret; 387 } 388 389 /* 390 * ecc spectial type3: 391 * ecc bits: 0xC0[4,5] 0xF0[4,5] 392 * [0b0000, 0b0011], No bit errors were detected; 393 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 394 * reach Flipping Bits; 395 * [0b1000, 0b1011], Multiple bit errors were detected and 396 * not corrected. 397 * [0b1100, 0b1111], Bit error count equals the bit flip 398 * detectio nthreshold 399 */ 400 static u32 sfc_nand_get_ecc_status3(void) 401 { 402 u32 ret; 403 u32 i; 404 u8 ecc; 405 u8 status, status1; 406 u32 timeout = 1000 * 1000; 407 408 for (i = 0; i < timeout; i++) { 409 ret = sfc_nand_read_feature(0xC0, &status); 410 411 if (ret != SFC_OK) 412 return SFC_NAND_ECC_ERROR; 413 414 ret = sfc_nand_read_feature(0xF0, &status1); 415 416 if (ret != SFC_OK) 417 return SFC_NAND_ECC_ERROR; 418 419 if (!(status & (1 << 0))) 420 break; 421 422 sfc_delay(1); 423 } 424 425 ecc = (status >> 4) & 0x03; 426 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 427 428 if (ecc < 7) 429 ret = SFC_NAND_ECC_OK; 430 else if (ecc == 7 || ecc >= 12) 431 ret = SFC_NAND_ECC_REFRESH; 432 else 433 ret = (u32)SFC_NAND_ECC_ERROR; 434 435 return ret; 436 } 437 438 /* 439 * ecc spectial type4: 440 * ecc bits: 0xC0[2,5] 441 * [0b0000], No bit errors were detected; 442 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 443 * reach Flipping Bits; 444 * [0b1000], Multiple bit errors were detected and 445 * not corrected. 446 * [0b1100], Bit error count equals the bit flip 447 * detectionthreshold 448 * else, reserved 449 */ 450 static u32 sfc_nand_get_ecc_status4(void) 451 { 452 u32 ret; 453 u32 i; 454 u8 ecc; 455 u8 status; 456 u32 timeout = 1000 * 1000; 457 458 for (i = 0; i < timeout; i++) { 459 ret = sfc_nand_read_feature(0xC0, &status); 460 461 if (ret != SFC_OK) 462 return SFC_NAND_ECC_ERROR; 463 464 if (!(status & (1 << 0))) 465 break; 466 467 sfc_delay(1); 468 } 469 470 ecc = (status >> 2) & 0x0f; 471 472 if (ecc < 7) 473 ret = SFC_NAND_ECC_OK; 474 else if (ecc == 7 || ecc == 12) 475 ret = SFC_NAND_ECC_REFRESH; 476 else 477 ret = (u32)SFC_NAND_ECC_ERROR; 478 479 return ret; 480 } 481 482 /* 483 * ecc spectial type5: 484 * ecc bits: 0xC0[4,6] 485 * [0b000], No bit errors were detected; 486 * [0b001, 0b011], Bit errors were detected and corrected. Not 487 * reach Flipping Bits; 488 * [0b100], Bit error count equals the bit flip 489 * detectionthreshold 490 * [0b101, 0b110], Reserved; 491 * [0b111], Multiple bit errors were detected and 492 * not corrected. 493 */ 494 static u32 sfc_nand_get_ecc_status5(void) 495 { 496 u32 ret; 497 u32 i; 498 u8 ecc; 499 u8 status; 500 u32 timeout = 1000 * 1000; 501 502 for (i = 0; i < timeout; i++) { 503 ret = sfc_nand_read_feature(0xC0, &status); 504 505 if (ret != SFC_OK) 506 return SFC_NAND_ECC_ERROR; 507 508 if (!(status & (1 << 0))) 509 break; 510 511 sfc_delay(1); 512 } 513 514 ecc = (status >> 4) & 0x07; 515 516 if (ecc < 4) 517 ret = SFC_NAND_ECC_OK; 518 else if (ecc == 4) 519 ret = SFC_NAND_ECC_REFRESH; 520 else 521 ret = (u32)SFC_NAND_ECC_ERROR; 522 523 return ret; 524 } 525 526 /* 527 * ecc spectial type6: 528 * ecc bits: 0xC0[4,6] 529 * [0b000], No bit errors were detected; 530 * [0b001], 1-3 Bit errors were detected and corrected. Not 531 * reach Flipping Bits; 532 * [0b010], Multiple bit errors were detected and 533 * not corrected. 534 * [0b011], 4-6 Bit errors were detected and corrected. Not 535 * reach Flipping Bits; 536 * [0b101], Bit error count equals the bit flip 537 * detectionthreshold 538 * others, Reserved. 539 */ 540 static u32 sfc_nand_get_ecc_status6(void) 541 { 542 u32 ret; 543 u32 i; 544 u8 ecc; 545 u8 status; 546 u32 timeout = 1000 * 1000; 547 548 for (i = 0; i < timeout; i++) { 549 ret = sfc_nand_read_feature(0xC0, &status); 550 551 if (ret != SFC_OK) 552 return SFC_NAND_ECC_ERROR; 553 554 if (!(status & (1 << 0))) 555 break; 556 557 sfc_delay(1); 558 } 559 560 ecc = (status >> 4) & 0x07; 561 562 if (ecc == 0 || ecc == 1 || ecc == 3) 563 ret = SFC_NAND_ECC_OK; 564 else if (ecc == 5) 565 ret = SFC_NAND_ECC_REFRESH; 566 else 567 ret = (u32)SFC_NAND_ECC_ERROR; 568 569 return ret; 570 } 571 572 u32 sfc_nand_erase_block(u8 cs, u32 addr) 573 { 574 int ret; 575 struct rk_sfc_op op; 576 u8 status; 577 578 rkflash_print_dio("%s %x\n", __func__, addr); 579 op.sfcmd.d32 = 0; 580 op.sfcmd.b.cmd = 0xd8; 581 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 582 op.sfcmd.b.rw = SFC_WRITE; 583 584 op.sfctrl.d32 = 0; 585 586 sfc_nand_write_en(); 587 ret = sfc_request(&op, addr, NULL, 0); 588 589 if (ret != SFC_OK) 590 return ret; 591 592 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 593 594 if (status & (1 << 2)) 595 return SFC_NAND_PROG_ERASE_ERROR; 596 597 return ret; 598 } 599 600 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 601 { 602 int ret; 603 u32 plane; 604 struct rk_sfc_op op; 605 u8 status; 606 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 607 608 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 609 sfc_nand_write_en(); 610 611 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 612 p_nand_info->feature & FEA_SOFT_QOP_BIT && 613 sfc_get_version() < SFC_VER_3) 614 sfc_nand_rw_preset(); 615 616 op.sfcmd.d32 = 0; 617 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 618 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 619 op.sfcmd.b.rw = SFC_WRITE; 620 621 op.sfctrl.d32 = 0; 622 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 623 op.sfctrl.b.addrbits = 16; 624 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 625 sfc_request(&op, plane, p_page_buf, page_size); 626 627 op.sfcmd.d32 = 0; 628 op.sfcmd.b.cmd = 0x10; 629 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 630 op.sfcmd.b.rw = SFC_WRITE; 631 632 op.sfctrl.d32 = 0; 633 ret = sfc_request(&op, addr, p_page_buf, 0); 634 635 if (ret != SFC_OK) 636 return ret; 637 638 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 639 640 if (status & (1 << 3)) 641 return SFC_NAND_PROG_ERASE_ERROR; 642 643 return ret; 644 } 645 646 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 647 { 648 int ret; 649 u32 sec_per_page = p_nand_info->sec_per_page; 650 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 651 struct nand_mega_area *meta = &p_nand_info->meta; 652 653 memcpy(gp_page_buf, p_data, data_size); 654 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 655 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 656 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 657 658 if (sec_per_page == 8) { 659 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 660 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 661 } 662 663 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 664 665 return ret; 666 } 667 668 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 669 { 670 int ret; 671 u32 plane; 672 struct rk_sfc_op op; 673 u32 ecc_result; 674 u8 status; 675 676 op.sfcmd.d32 = 0; 677 op.sfcmd.b.cmd = 0x13; 678 op.sfcmd.b.rw = SFC_WRITE; 679 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 680 681 op.sfctrl.d32 = 0; 682 683 sfc_request(&op, row, p_page_buf, 0); 684 685 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 686 p_nand_info->feature & FEA_SOFT_QOP_BIT && 687 sfc_get_version() < SFC_VER_3) 688 sfc_nand_rw_preset(); 689 690 sfc_nand_wait_busy(&status, 1000 * 1000); 691 ecc_result = p_nand_info->ecc_status(); 692 693 op.sfcmd.d32 = 0; 694 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 695 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 696 op.sfcmd.b.dummybits = 8; 697 698 op.sfctrl.d32 = 0; 699 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 700 op.sfctrl.b.addrbits = 16; 701 702 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 703 ret = sfc_request(&op, plane | column, p_page_buf, len); 704 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 705 706 if (ret != SFC_OK) 707 return SFC_NAND_HW_ERROR; 708 709 return ecc_result; 710 } 711 712 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 713 { 714 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 715 716 return sfc_nand_read(addr, p_page_buf, 0, page_size); 717 } 718 719 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 720 { 721 u32 ret; 722 u32 sec_per_page = p_nand_info->sec_per_page; 723 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 724 struct nand_mega_area *meta = &p_nand_info->meta; 725 726 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 727 memcpy(p_data, gp_page_buf, data_size); 728 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 729 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 730 731 if (p_nand_info->sec_per_page == 8) { 732 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 733 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 734 } 735 736 if (ret == SFC_NAND_HW_ERROR) 737 ret = SFC_NAND_ECC_ERROR; 738 739 if (ret != SFC_NAND_ECC_OK) { 740 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 741 742 if (p_data) 743 rkflash_print_hex("data:", p_data, 4, 8); 744 745 if (p_spare) 746 rkflash_print_hex("spare:", p_spare, 4, 2); 747 } 748 749 return ret; 750 } 751 752 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 753 { 754 u32 ret; 755 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 756 u32 marker = 0; 757 758 ret = sfc_nand_read(addr, &marker, data_size, 2); 759 760 /* unify with mtd framework */ 761 if (ret == SFC_NAND_ECC_ERROR) 762 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 763 __func__, addr, ret, marker); 764 765 /* Original bad block */ 766 if ((u16)marker != 0xffff) 767 return true; 768 769 return false; 770 } 771 772 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 773 { 774 u32 ret; 775 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 776 777 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 778 779 if (ret) 780 return SFC_NAND_HW_ERROR; 781 782 gp_page_buf[data_size / 4] = 0x0; 783 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 784 785 if (ret) 786 return SFC_NAND_HW_ERROR; 787 788 return ret; 789 } 790 791 int sfc_nand_read_id(u8 *data) 792 { 793 int ret; 794 struct rk_sfc_op op; 795 796 op.sfcmd.d32 = 0; 797 op.sfcmd.b.cmd = CMD_READ_JEDECID; 798 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 799 800 op.sfctrl.d32 = 0; 801 op.sfctrl.b.addrbits = 8; 802 803 ret = sfc_request(&op, 0, data, 3); 804 805 return ret; 806 } 807 808 /* 809 * Read the 1st page's 1st byte of a phy_blk 810 * If not FF, it's bad blk 811 */ 812 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 813 { 814 u32 bad_cnt, page; 815 u32 blk_per_die; 816 u16 blk; 817 818 rkflash_print_info("%s\n", __func__); 819 820 bad_cnt = 0; 821 blk_per_die = p_nand_info->plane_per_die * 822 p_nand_info->blk_per_plane; 823 824 for (blk = 0; blk < blk_per_die; blk++) { 825 page = (blk + blk_per_die * die) * 826 p_nand_info->page_per_blk; 827 828 if (sfc_nand_check_bad_block(die, page)) { 829 table[bad_cnt++] = blk; 830 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 831 } 832 } 833 834 return (int)bad_cnt; 835 } 836 837 void sfc_nand_ftl_ops_init(void) 838 { 839 /* para init */ 840 g_nand_phy_info.nand_type = 1; 841 g_nand_phy_info.die_num = 1; 842 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 843 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 844 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 845 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 846 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 847 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 848 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 849 p_nand_info->page_per_blk; 850 g_nand_phy_info.reserved_blk = 8; 851 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 852 p_nand_info->blk_per_plane; 853 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 854 855 /* driver register */ 856 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 857 g_nand_ops.erase_blk = sfc_nand_erase_block; 858 g_nand_ops.prog_page = sfc_nand_prog_page; 859 g_nand_ops.read_page = sfc_nand_read_page; 860 g_nand_ops.bch_sel = NULL; 861 } 862 863 static int sfc_nand_enable_QE(void) 864 { 865 int ret = SFC_OK; 866 u8 status; 867 868 ret = sfc_nand_read_feature(0xB0, &status); 869 870 if (ret != SFC_OK) 871 return ret; 872 873 if (status & 1) /* is QE bit set */ 874 return SFC_OK; 875 876 status |= 1; 877 878 return sfc_nand_write_feature(0xB0, status); 879 } 880 881 u32 sfc_nand_init(void) 882 { 883 u8 status, id_byte[8]; 884 885 sfc_nand_read_id(id_byte); 886 rkflash_print_error("sfc_nand id: %x %x %x\n", 887 id_byte[0], id_byte[1], id_byte[2]); 888 889 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 890 return (u32)FTL_NO_FLASH; 891 892 p_nand_info = sfc_nand_get_info(id_byte); 893 894 if (!p_nand_info) 895 return (u32)FTL_UNSUPPORTED_FLASH; 896 897 sfc_nand_dev.manufacturer = id_byte[0]; 898 sfc_nand_dev.mem_type = id_byte[1]; 899 sfc_nand_dev.capacity = p_nand_info->density; 900 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 901 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 902 903 /* disable block lock */ 904 sfc_nand_write_feature(0xA0, 0); 905 sfc_nand_dev.read_lines = DATA_LINES_X1; 906 sfc_nand_dev.prog_lines = DATA_LINES_X1; 907 sfc_nand_dev.page_read_cmd = 0x03; 908 sfc_nand_dev.page_prog_cmd = 0x02; 909 910 if (p_nand_info->feature & FEA_4BIT_READ) { 911 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 912 !p_nand_info->has_qe_bits) { 913 sfc_nand_dev.read_lines = DATA_LINES_X4; 914 sfc_nand_dev.page_read_cmd = 0x6b; 915 } 916 } 917 918 if (p_nand_info->feature & FEA_4BIT_PROG && 919 sfc_nand_dev.read_lines == DATA_LINES_X4) { 920 sfc_nand_dev.prog_lines = DATA_LINES_X4; 921 sfc_nand_dev.page_prog_cmd = 0x32; 922 } 923 924 sfc_nand_read_feature(0xA0, &status); 925 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 926 sfc_nand_read_feature(0xB0, &status); 927 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 928 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 929 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 930 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 931 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 932 933 return SFC_OK; 934 } 935 936 void sfc_nand_deinit(void) 937 { 938 /* to-do */ 939 } 940 941 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 942 { 943 return &sfc_nand_dev; 944 } 945 946