1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static struct nand_info spi_nand_tbl[] = { 18 /* TC58CVG0S0HxAIx */ 19 {0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xFF, 0xFF, 4, 8, NULL}, 20 /* TC58CVG1S0HxAIx */ 21 {0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xFF, 0xFF, 4, 8, NULL}, 22 /* MX35LF1GE4AB */ 23 {0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 24 /* MX35LF2GE4AB */ 25 {0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 26 /* GD5F1GQ4UAYIG */ 27 {0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, NULL}, 28 /* MT29F1G01ZAC */ 29 {0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 30 /* GD5F2GQ40BY2GR */ 31 {0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 32 /* GD5F1GQ4U */ 33 {0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 34 /* IS37SML01G1 */ 35 {0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xFF, 0xFF, 8, 12, &sfc_nand_ecc_status_sp1}, 36 /* W25N01GV */ 37 {0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 4, 20, &sfc_nand_ecc_status_sp1}, 38 /* HYF2GQ4UAACAE */ 39 {0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 40 /* HYF2GQ4UDACAE */ 41 {0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, NULL}, 42 /* HYF2GQ4UHCCAE */ 43 {0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 44 /* HYF1GQ4UDACAE */ 45 {0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, NULL}, 46 /* F50L1G41LB */ 47 {0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 20, 36, &sfc_nand_ecc_status_sp1}, 48 /* XT26G02A */ 49 {0x0BE2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 50 /* XT26G01A */ 51 {0x0BE1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 52 /* FS35ND01G-S1 */ 53 {0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 16, 20, &sfc_nand_ecc_status_sp5}, 54 /* FS35ND02G-S2 */ 55 {0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, 16, 20, &sfc_nand_ecc_status_sp5}, 56 /* DS35Q1GA-1B */ 57 {0xE571, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 58 /* DS35Q2GA-1B */ 59 {0xE572, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 60 /* EM73C044SNC-G */ 61 {0xD522, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0x0, 4, 20, NULL}, 62 /* EM73D044SNB-G */ 63 {0xD520, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0x0, 4, 20, NULL}, 64 /* ATO25D1GA */ 65 {0x9B12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x40, 18, 1, 0xB0, 0x0, 20, 36, &sfc_nand_ecc_status_sp1}, 66 /* XT26G02B */ 67 {0x0BF2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 68 /* XT26G01B */ 69 {0x0BF1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 70 /* HYF4GQ4UAACBE */ 71 {0xC9D4, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 4, 0xB0, 0, 32, 64, NULL}, 72 /* FM25S01 */ 73 {0xA1A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0, 0, 4, &sfc_nand_ecc_status_sp1}, 74 /* HYF1GQ4UPACAE */ 75 {0xC9A1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp1}, 76 /* EM73E044SNA-G */ 77 {0xD503, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 8, 0xB0, 0, 4, 40, NULL}, 78 /* GD5F2GQ5UEYIG */ 79 {0xC852, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, &sfc_nand_ecc_status_sp2}, 80 /* GD5F1GQ4R */ 81 {0xC8C1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 82 }; 83 84 static u8 id_byte[8]; 85 static struct nand_info *p_nand_info; 86 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 87 static struct SFNAND_DEV sfc_nand_dev; 88 89 static struct nand_info *spi_nand_get_info(u8 *nand_id) 90 { 91 u32 i; 92 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 93 94 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 95 if (spi_nand_tbl[i].id == id) 96 return &spi_nand_tbl[i]; 97 } 98 return NULL; 99 } 100 101 static int sfc_nand_write_en(void) 102 { 103 int ret; 104 union SFCCMD_DATA sfcmd; 105 106 sfcmd.d32 = 0; 107 sfcmd.b.cmd = CMD_WRITE_EN; 108 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 109 return ret; 110 } 111 112 static int sfc_nand_rw_preset(void) 113 { 114 int ret; 115 union SFCCTRL_DATA sfctrl; 116 union SFCCMD_DATA sfcmd; 117 u8 status = 0xFF; 118 119 sfcmd.d32 = 0; 120 sfcmd.b.cmd = 0; 121 sfcmd.b.datasize = 1; 122 sfcmd.b.rw = SFC_WRITE; 123 124 sfctrl.b.datalines = 2; 125 ret = sfc_request(sfcmd.d32, sfctrl.d32, 0, &status); 126 return ret; 127 } 128 129 static int sfc_nand_read_feature(u8 addr, u8 *data) 130 { 131 int ret; 132 union SFCCMD_DATA sfcmd; 133 134 sfcmd.d32 = 0; 135 sfcmd.b.cmd = 0x0F; 136 sfcmd.b.datasize = 1; 137 sfcmd.b.addrbits = SFC_ADDR_XBITS; 138 *data = 0; 139 140 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, data); 141 if (ret != SFC_OK) 142 return ret; 143 return SFC_OK; 144 } 145 146 static int sfc_nand_write_feature(u32 addr, u8 status) 147 { 148 int ret; 149 union SFCCMD_DATA sfcmd; 150 151 sfc_nand_write_en(); 152 153 sfcmd.d32 = 0; 154 sfcmd.b.cmd = 0x1F; 155 sfcmd.b.datasize = 1; 156 sfcmd.b.addrbits = SFC_ADDR_XBITS; 157 sfcmd.b.rw = SFC_WRITE; 158 159 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, &status); 160 if (ret != SFC_OK) 161 return ret; 162 return ret; 163 } 164 165 static int sfc_nand_wait_busy(u8 *data, int timeout) 166 { 167 int ret; 168 int i; 169 u8 status; 170 171 *data = 0; 172 for (i = 0; i < timeout; i++) { 173 ret = sfc_nand_read_feature(0xC0, &status); 174 if (ret != SFC_OK) 175 return ret; 176 *data = status; 177 if (!(status & (1 << 0))) 178 return SFC_OK; 179 sfc_delay(1); 180 } 181 return -1; 182 } 183 184 /* 185 * ecc default: 186 * 0, No bit errors were detected 187 * 1, Bit errors were detected and corrected. 188 * 2, Multiple bit errors were detected and not corrected. 189 * 3, Bits errors were detected and corrected, bit error count 190 * exceed the bit flip detection threshold 191 */ 192 static u32 sfc_nand_ecc_status(void) 193 { 194 int ret; 195 u32 i; 196 u8 ecc; 197 u8 status; 198 u32 timeout = 1000 * 1000; 199 200 for (i = 0; i < timeout; i++) { 201 ret = sfc_nand_read_feature(0xC0, &status); 202 if (ret != SFC_OK) 203 return SFC_NAND_ECC_ERROR; 204 if (!(status & (1 << 0))) 205 break; 206 sfc_delay(1); 207 } 208 209 ecc = (status >> 4) & 0x03; 210 211 if (ecc <= 1) 212 ret = SFC_NAND_ECC_OK; 213 else if (ecc == 2) 214 ret = SFC_NAND_ECC_ERROR; 215 else 216 ret = SFC_NAND_ECC_REFRESH; 217 218 return ret; 219 } 220 221 /* 222 * ecc spectial type1: 223 * 0x00, No bit errors were detected; 224 * 0x01, Bits errors were detected and corrected, bit error count 225 * may reach the bit flip detection threshold; 226 * 0x10, Multiple bit errors were detected and not corrected; 227 * 0x11, Reserved. 228 */ 229 u32 sfc_nand_ecc_status_sp1(void) 230 { 231 int ret; 232 u32 i; 233 u8 ecc; 234 u8 status; 235 u32 timeout = 1000 * 1000; 236 237 for (i = 0; i < timeout; i++) { 238 ret = sfc_nand_read_feature(0xC0, &status); 239 if (ret != SFC_OK) 240 return SFC_NAND_ECC_ERROR; 241 if (!(status & (1 << 0))) 242 break; 243 sfc_delay(1); 244 } 245 246 ecc = (status >> 4) & 0x03; 247 248 if (ecc == 0) 249 ret = SFC_NAND_ECC_OK; 250 else if (ecc == 1) 251 ret = SFC_NAND_ECC_REFRESH; 252 else 253 ret = SFC_NAND_ECC_ERROR; 254 255 return ret; 256 } 257 258 /* 259 * ecc spectial type2: 260 * [0x0000, 0x0011], No bit errors were detected; 261 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 262 * reach Flipping Bits; 263 * [0x1000, 0x1011], Multiple bit errors were detected and 264 * not corrected; 265 * [0x1100, 0x1111], reserved. 266 */ 267 u32 sfc_nand_ecc_status_sp2(void) 268 { 269 int ret; 270 u32 i; 271 u8 ecc; 272 u8 status, status1; 273 u32 timeout = 1000 * 1000; 274 275 for (i = 0; i < timeout; i++) { 276 ret = sfc_nand_read_feature(0xC0, &status); 277 if (ret != SFC_OK) 278 return SFC_NAND_ECC_ERROR; 279 ret = sfc_nand_read_feature(0xF0, &status1); 280 if (ret != SFC_OK) 281 return SFC_NAND_ECC_ERROR; 282 if (!(status & (1 << 0))) 283 break; 284 sfc_delay(1); 285 } 286 287 ecc = (status >> 4) & 0x03; 288 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 289 if (ecc < 7) 290 ret = SFC_NAND_ECC_OK; 291 else if (ecc == 7) 292 ret = SFC_NAND_ECC_REFRESH; 293 else 294 ret = SFC_NAND_ECC_ERROR; 295 296 return ret; 297 } 298 299 /* 300 * ecc spectial type3: 301 * [0x0000, 0x0011], No bit errors were detected; 302 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 303 * reach Flipping Bits; 304 * [0x1000, 0x1011], Multiple bit errors were detected and 305 * not corrected. 306 * [0x1100, 0x1111], Bit error count equals the bit flip 307 * detectionthreshold 308 */ 309 u32 sfc_nand_ecc_status_sp3(void) 310 { 311 int ret; 312 u32 i; 313 u8 ecc; 314 u8 status, status1; 315 u32 timeout = 1000 * 1000; 316 317 for (i = 0; i < timeout; i++) { 318 ret = sfc_nand_read_feature(0xC0, &status); 319 if (ret != SFC_OK) 320 return SFC_NAND_ECC_ERROR; 321 ret = sfc_nand_read_feature(0xF0, &status1); 322 if (ret != SFC_OK) 323 return SFC_NAND_ECC_ERROR; 324 if (!(status & (1 << 0))) 325 break; 326 sfc_delay(1); 327 } 328 329 ecc = (status >> 4) & 0x03; 330 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 331 if (ecc < 7) 332 ret = SFC_NAND_ECC_OK; 333 else if (ecc == 7 || ecc >= 12) 334 ret = SFC_NAND_ECC_REFRESH; 335 else 336 ret = SFC_NAND_ECC_ERROR; 337 338 return ret; 339 } 340 341 /* 342 * ecc spectial type4: 343 * [0x0000], No bit errors were detected; 344 * [0x0001, 0x0111], Bit errors were detected and corrected. Not 345 * reach Flipping Bits; 346 * [0x1000], Multiple bit errors were detected and 347 * not corrected. 348 * [0x1100], Bit error count equals the bit flip 349 * detectionthreshold 350 * else, reserved 351 */ 352 u32 sfc_nand_ecc_status_sp4(void) 353 { 354 int ret; 355 u32 i; 356 u8 ecc; 357 u8 status; 358 u32 timeout = 1000 * 1000; 359 360 for (i = 0; i < timeout; i++) { 361 ret = sfc_nand_read_feature(0xC0, &status); 362 if (ret != SFC_OK) 363 return SFC_NAND_ECC_ERROR; 364 if (!(status & (1 << 0))) 365 break; 366 sfc_delay(1); 367 } 368 369 ecc = (status >> 2) & 0x0f; 370 if (ecc < 7) 371 ret = SFC_NAND_ECC_OK; 372 else if (ecc == 7 || ecc == 12) 373 ret = SFC_NAND_ECC_REFRESH; 374 else 375 ret = SFC_NAND_ECC_ERROR; 376 377 return ret; 378 } 379 380 /* 381 * ecc spectial type5: 382 * [0x0], No bit errors were detected; 383 * [0x001, 0x011], Bit errors were detected and corrected. Not 384 * reach Flipping Bits; 385 * [0x100], Bit error count equals the bit flip 386 * detectionthreshold 387 * [0x101, 0x110], Reserved; 388 * [0x111], Multiple bit errors were detected and 389 * not corrected. 390 */ 391 u32 sfc_nand_ecc_status_sp5(void) 392 { 393 int ret; 394 u32 i; 395 u8 ecc; 396 u8 status; 397 u32 timeout = 1000 * 1000; 398 399 for (i = 0; i < timeout; i++) { 400 ret = sfc_nand_read_feature(0xC0, &status); 401 if (ret != SFC_OK) 402 return SFC_NAND_ECC_ERROR; 403 if (!(status & (1 << 0))) 404 break; 405 sfc_delay(1); 406 } 407 408 ecc = (status >> 4) & 0x07; 409 if (ecc < 4) 410 ret = SFC_NAND_ECC_OK; 411 else if (ecc == 4) 412 ret = SFC_NAND_ECC_REFRESH; 413 else 414 ret = SFC_NAND_ECC_ERROR; 415 416 return ret; 417 } 418 419 static u32 sfc_nand_erase_block(u8 cs, u32 addr) 420 { 421 int ret; 422 union SFCCMD_DATA sfcmd; 423 u8 status; 424 425 sfcmd.d32 = 0; 426 sfcmd.b.cmd = p_nand_info->block_erase_cmd; 427 sfcmd.b.addrbits = SFC_ADDR_24BITS; 428 sfc_nand_write_en(); 429 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 430 if (ret != SFC_OK) 431 return ret; 432 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 433 if (status & (1 << 2)) 434 return SFC_NAND_PROG_ERASE_ERROR; 435 return ret; 436 } 437 438 static u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 439 { 440 int ret; 441 u32 plane; 442 union SFCCMD_DATA sfcmd; 443 union SFCCTRL_DATA sfctrl; 444 u8 status; 445 u32 sec_per_page = p_nand_info->sec_per_page; 446 u32 spare_offs_1 = p_nand_info->spare_offs_1; 447 u32 spare_offs_2 = p_nand_info->spare_offs_2; 448 u32 data_size = sec_per_page * 512; 449 450 PRINT_SFC_I("%s %x %x %x\n", __func__, addr, p_data[0], p_spare[0]); 451 memcpy(gp_page_buf, p_data, data_size); 452 ftl_memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 453 gp_page_buf[(data_size + spare_offs_1) / 4] = p_spare[0]; 454 gp_page_buf[(data_size + spare_offs_2) / 4] = p_spare[1]; 455 if (sec_per_page == 8) { 456 gp_page_buf[(data_size + spare_offs_1) / 4 + 1] = p_spare[2]; 457 gp_page_buf[(data_size + spare_offs_2) / 4 + 1] = p_spare[3]; 458 } 459 sfc_nand_write_en(); 460 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 461 p_nand_info->feature & FEA_SOFT_QOP_BIT && 462 sfc_get_version() < SFC_VER_3) 463 sfc_nand_rw_preset(); 464 465 sfcmd.d32 = 0; 466 sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 467 sfcmd.b.addrbits = SFC_ADDR_XBITS; 468 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 469 sfcmd.b.rw = SFC_WRITE; 470 471 sfctrl.d32 = 0; 472 sfctrl.b.datalines = sfc_nand_dev.prog_lines; 473 sfctrl.b.addrbits = 16; 474 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 475 sfc_request(sfcmd.d32, sfctrl.d32, plane, gp_page_buf); 476 477 sfcmd.d32 = 0; 478 sfcmd.b.cmd = p_nand_info->page_prog_cmd; 479 sfcmd.b.addrbits = SFC_ADDR_24BITS; 480 sfcmd.b.datasize = 0; 481 sfcmd.b.rw = SFC_WRITE; 482 ret = sfc_request(sfcmd.d32, 0, addr, p_data); 483 if (ret != SFC_OK) 484 return ret; 485 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 486 if (status & (1 << 3)) 487 return SFC_NAND_PROG_ERASE_ERROR; 488 return ret; 489 } 490 491 static u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 492 { 493 int ret; 494 u32 plane; 495 union SFCCMD_DATA sfcmd; 496 union SFCCTRL_DATA sfctrl; 497 u32 ecc_result; 498 u32 spare_offs_1 = p_nand_info->spare_offs_1; 499 u32 spare_offs_2 = p_nand_info->spare_offs_2; 500 u32 sec_per_page = p_nand_info->sec_per_page; 501 u32 data_size = sec_per_page * 512; 502 503 PRINT_SFC_I("%s %x %x %x\n", __func__, addr, p_data[0], p_spare[0]); 504 sfcmd.d32 = 0; 505 sfcmd.b.cmd = p_nand_info->page_read_cmd; 506 sfcmd.b.datasize = 0; 507 sfcmd.b.addrbits = SFC_ADDR_24BITS; 508 sfc_request(sfcmd.d32, 0, addr, p_data); 509 510 if (p_nand_info->ecc_status) 511 ecc_result = p_nand_info->ecc_status(); 512 else 513 ecc_result = sfc_nand_ecc_status(); 514 515 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 516 p_nand_info->feature & FEA_SOFT_QOP_BIT && 517 sfc_get_version() < SFC_VER_3) 518 sfc_nand_rw_preset(); 519 520 sfcmd.d32 = 0; 521 sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 522 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 523 sfcmd.b.addrbits = SFC_ADDR_24BITS; 524 sfctrl.d32 = 0; 525 sfctrl.b.datalines = sfc_nand_dev.read_lines; 526 527 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 528 ret = sfc_request(sfcmd.d32, sfctrl.d32, plane << 8, gp_page_buf); 529 memcpy(p_data, gp_page_buf, data_size); 530 p_spare[0] = gp_page_buf[(data_size + spare_offs_1) / 4]; 531 p_spare[1] = gp_page_buf[(data_size + spare_offs_2) / 4]; 532 if (p_nand_info->sec_per_page == 8) { 533 p_spare[2] = gp_page_buf[(data_size + spare_offs_1) / 4 + 1]; 534 p_spare[3] = gp_page_buf[(data_size + spare_offs_2) / 4 + 1]; 535 } 536 if (ret != SFC_OK) 537 return SFC_NAND_ECC_ERROR; 538 539 if (ecc_result != SFC_NAND_ECC_OK) { 540 PRINT_SFC_E("%s[0x%x], ret=0x%x\n", __func__, addr, ecc_result); 541 if (p_data) 542 PRINT_SFC_HEX("data:", p_data, 4, 8); 543 if (p_spare) 544 PRINT_SFC_HEX("spare:", p_spare, 4, 2); 545 } 546 547 return ecc_result; 548 } 549 550 static int sfc_nand_read_id_raw(u8 *data) 551 { 552 int ret; 553 union SFCCMD_DATA sfcmd; 554 555 sfcmd.d32 = 0; 556 sfcmd.b.cmd = CMD_READ_JEDECID; 557 sfcmd.b.datasize = 3; 558 sfcmd.b.addrbits = SFC_ADDR_XBITS; 559 560 ret = sfc_request(sfcmd.d32, 0x8 << 16, 0, data); 561 562 return ret; 563 } 564 565 /* 566 * Read the 1st page's 1st byte of a phy_blk 567 * If not FF, it's bad blk 568 */ 569 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 570 { 571 u16 blk; 572 u32 bad_cnt, page; 573 u32 blk_per_die; 574 u32 *pread; 575 u32 *pspare_read; 576 577 PRINT_SFC_E("%s\n", __func__); 578 pread = ftl_malloc(2048); 579 pspare_read = ftl_malloc(8); 580 bad_cnt = 0; 581 blk_per_die = p_nand_info->plane_per_die * 582 p_nand_info->blk_per_plane; 583 for (blk = 0; blk < blk_per_die; blk++) { 584 page = (blk + blk_per_die * die) * 585 p_nand_info->page_per_blk; 586 sfc_nand_read_page(0, page, pread, pspare_read); 587 588 if (pread[0] != 0xFFFFFFFF || 589 pspare_read[0] != 0xFFFFFFFF) { 590 table[bad_cnt++] = blk; 591 PRINT_SFC_E("die[%d], bad_blk[%d]\n", die, blk); 592 } 593 } 594 ftl_free(pread); 595 ftl_free(pspare_read); 596 return (int)bad_cnt; 597 } 598 599 #if SFC_NAND_STRESS_TEST_EN 600 601 #define SFC_NAND_PAGE_SIZE 2048 602 #define SFC_NAND_SPARE_SIZE 8 603 604 static u16 bad_blk_list[1024]; 605 static u32 pwrite[SFC_NAND_PAGE_SIZE / 4]; 606 static u32 pread[SFC_NAND_PAGE_SIZE / 4]; 607 static u32 pspare_write[SFC_NAND_SPARE_SIZE / 4]; 608 static u32 pspare_read[SFC_NAND_SPARE_SIZE / 4]; 609 static u32 bad_blk_num; 610 static u32 bad_page_num; 611 612 static void sfc_nand_test(void) 613 { 614 u32 i, blk, page, bad_cnt, page_addr; 615 int ret; 616 u32 pages_num = 64; 617 u32 blk_addr = 64; 618 u32 is_bad_blk = 0; 619 620 PRINT_SFC_E("%s\n", __func__); 621 622 bad_blk_num = 0; 623 bad_page_num = 0; 624 bad_cnt = sfc_nand_get_bad_block_list(bad_blk_list, 0); 625 626 for (blk = 0; blk < 1024; blk++) { 627 for (i = 0; i < bad_cnt; i++) { 628 if (bad_blk_list[i] == blk) 629 break; 630 } 631 if (i < bad_cnt) 632 continue; 633 is_bad_blk = 0; 634 PRINT_SFC_E("Flash prog block: %x\n", blk); 635 sfc_nand_erase_block(0, blk * blk_addr); 636 for (page = 0; page < pages_num; page++) { 637 page_addr = blk * blk_addr + page; 638 for (i = 0; i < 512; i++) 639 pwrite[i] = (page_addr << 16) + i; 640 pspare_write[0] = pwrite[0] + 0x5AF0; 641 pspare_write[1] = pspare_write[0] + 1; 642 sfc_nand_prog_page(0, page_addr, pwrite, pspare_write); 643 memset(pread, 0, 2048); 644 memset(pspare_read, 0, 8); 645 ret = sfc_nand_read_page(0, page_addr, pread, 646 pspare_read); 647 if (ret != SFC_NAND_ECC_OK) 648 is_bad_blk = 1; 649 for (i = 0; i < 512; i++) { 650 if (pwrite[i] != pread[i]) { 651 is_bad_blk = 1; 652 break; 653 } 654 } 655 for (i = 0; i < 2; i++) { 656 if (pspare_write[i] != pspare_read[i]) { 657 is_bad_blk = 1; 658 break; 659 } 660 } 661 if (is_bad_blk) { 662 bad_page_num++; 663 PRINT_SFC_E("ERR:page%x, ret=%x\n", 664 page_addr, ret); 665 PRINT_SFC_HEX("data:", pread, 4, 8); 666 PRINT_SFC_HEX("spare:", pspare_read, 4, 2); 667 } 668 } 669 sfc_nand_erase_block(0, blk * blk_addr); 670 if (is_bad_blk) 671 bad_blk_num++; 672 } 673 PRINT_SFC_E("bad_blk_num = %d, bad_page_num = %d\n", 674 bad_blk_num, bad_page_num); 675 676 PRINT_SFC_E("Flash Test Finish!!!\n"); 677 while (1) 678 ; 679 } 680 #endif 681 682 static void ftl_flash_init(void) 683 { 684 /* para init */ 685 g_nand_phy_info.nand_type = 1; 686 g_nand_phy_info.die_num = 1; 687 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 688 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 689 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 690 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 691 g_nand_phy_info.byte_per_sec = 512; 692 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 693 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 694 p_nand_info->page_per_blk; 695 g_nand_phy_info.reserved_blk = 8; 696 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 697 p_nand_info->blk_per_plane; 698 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 699 700 /* driver register */ 701 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 702 g_nand_ops.erase_blk = sfc_nand_erase_block; 703 g_nand_ops.prog_page = sfc_nand_prog_page; 704 g_nand_ops.read_page = sfc_nand_read_page; 705 g_nand_ops.bch_sel = NULL; 706 } 707 708 static int spi_nand_enable_QE(void) 709 { 710 int ret = SFC_OK; 711 u8 status; 712 int bit_offset = p_nand_info->QE_bits; 713 714 if (bit_offset == 0xFF) 715 return SFC_OK; 716 717 ret = sfc_nand_read_feature(p_nand_info->QE_address, &status); 718 if (ret != SFC_OK) 719 return ret; 720 721 if (status & (1 << bit_offset)) /* is QE bit set */ 722 return SFC_OK; 723 724 status |= (1 << bit_offset); 725 return sfc_nand_write_feature(p_nand_info->QE_address, status); 726 727 return ret; 728 } 729 730 u32 sfc_nand_init(void) 731 { 732 PRINT_SFC_I("...%s enter...\n", __func__); 733 734 sfc_nand_read_id_raw(id_byte); 735 PRINT_SFC_E("sfc_nand id: %x %x %x\n", 736 id_byte[0], id_byte[1], id_byte[2]); 737 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 738 return FTL_NO_FLASH; 739 740 p_nand_info = spi_nand_get_info(id_byte); 741 if (!p_nand_info) 742 return FTL_UNSUPPORTED_FLASH; 743 744 sfc_nand_dev.manufacturer = id_byte[0]; 745 sfc_nand_dev.mem_type = id_byte[1]; 746 747 /* disable block lock */ 748 sfc_nand_write_feature(0xA0, 0); 749 sfc_nand_dev.read_lines = DATA_LINES_X1; 750 sfc_nand_dev.prog_lines = DATA_LINES_X1; 751 sfc_nand_dev.page_read_cmd = p_nand_info->read_cache_cmd_1; 752 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_1; 753 if (p_nand_info->feature & FEA_4BIT_READ) { 754 if (spi_nand_enable_QE() == SFC_OK) { 755 sfc_nand_dev.read_lines = DATA_LINES_X4; 756 sfc_nand_dev.page_read_cmd = 757 p_nand_info->read_cache_cmd_4; 758 } 759 } 760 761 if (p_nand_info->feature & FEA_4BIT_PROG && 762 sfc_nand_dev.read_lines == DATA_LINES_X4) { 763 sfc_nand_dev.prog_lines = DATA_LINES_X4; 764 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_4; 765 } 766 767 if (1) { 768 u8 status; 769 770 sfc_nand_read_feature(0xA0, &status); 771 PRINT_SFC_I("sfc_nand A0 = 0x%x\n", status); 772 sfc_nand_read_feature(0xB0, &status); 773 PRINT_SFC_I("sfc_nand B0 = 0x%x\n", status); 774 sfc_nand_read_feature(0xC0, &status); 775 PRINT_SFC_I("sfc_nand C0 = 0x%x\n", status); 776 PRINT_SFC_I("read_lines = %x\n", sfc_nand_dev.read_lines); 777 PRINT_SFC_I("prog_lines = %x\n", sfc_nand_dev.prog_lines); 778 PRINT_SFC_I("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 779 PRINT_SFC_I("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 780 } 781 ftl_flash_init(); 782 783 #if SFC_NAND_STRESS_TEST_EN 784 sfc_nand_test(); 785 #endif 786 787 return SFC_OK; 788 } 789 790 int sfc_nand_read_id(u8 *data) 791 { 792 memcpy(data, id_byte, 3); 793 return 0; 794 } 795