1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 static u32 sfc_nand_get_ecc_status7(void); 25 static u32 sfc_nand_get_ecc_status8(void); 26 static u32 sfc_nand_get_ecc_status9(void); 27 28 static struct nand_info spi_nand_tbl[] = { 29 /* TC58CVG0S0HxAIx */ 30 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 31 /* TC58CVG1S0HxAIx */ 32 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 33 /* TC58CVG2S0HRAIJ */ 34 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 35 /* TC58CVG1S3HRAIJ */ 36 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 37 /* TC58CVG0S3HRAIJ */ 38 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 39 40 /* MX35LF1GE4AB */ 41 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 42 /* MX35LF2GE4AB */ 43 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 44 /* MX35LF2GE4AD */ 45 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 46 /* MX35LF4GE4AD */ 47 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 48 /* MX35UF1GE4AC */ 49 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 50 /* MX35UF2GE4AC */ 51 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 52 /* MX35UF1GE4AD */ 53 { 0xC2, 0x96, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 54 /* MX35UF2GE4AD */ 55 { 0xC2, 0xA6, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 56 /* MX35UF4GE4AD */ 57 { 0xC2, 0xB7, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 58 59 /* GD5F1GQ4UAYIG */ 60 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 61 /* GD5F1GQ4RB9IGR */ 62 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 63 /* GD5F2GQ40BY2GR */ 64 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 65 /* GD5F1GQ5UEYIG */ 66 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 67 /* GD5F2GQ5UEYIG */ 68 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 69 /* GD5F1GQ4R */ 70 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 71 /* GD5F4GQ6RExxG 1*4096 */ 72 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, 73 /* GD5F4GQ6UExxG 1*4096 */ 74 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, 75 /* GD5F1GQ4UExxH */ 76 { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 77 /* GD5F1GQ5REYIG */ 78 { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 79 /* GD5F2GQ5REYIG */ 80 { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 81 /* GD5F2GM7RxG */ 82 { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 83 /* GD5F2GM7UxG */ 84 { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 85 /* GD5F1GM7UxG */ 86 { 0xC8, 0x91, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 87 /* GD5F4GQ4UAYIG 1*4096 */ 88 { 0xC8, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 89 90 /* W25N01GV */ 91 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 92 /* W25N02KVZEIR */ 93 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 94 /* W25N04KVZEIR */ 95 { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 }, 96 /* W25N01GW */ 97 { 0xEF, 0xBA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 98 /* W25N02KW */ 99 { 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 100 /* W25N512GVEIG */ 101 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 102 /* W25N01KV */ 103 { 0xEF, 0xAE, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 104 105 /* HYF2GQ4UAACAE */ 106 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 107 /* HYF1GQ4UDACAE */ 108 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 109 /* HYF1GQ4UPACAE */ 110 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 111 /* HYF2GQ4UDACAE */ 112 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 113 /* HYF2GQ4UHCCAE */ 114 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 115 /* HYF4GQ4UAACBE */ 116 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 117 118 /* FS35ND01G-S1 */ 119 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 120 /* FS35ND02G-S2 */ 121 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 122 /* FS35ND01G-S1Y2 */ 123 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 124 /* FS35ND02G-S3Y2 */ 125 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 126 /* FS35ND04G-S2Y2 1*4096 */ 127 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 128 /* F35SQA001G */ 129 { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 130 /* F35SQA002G */ 131 { 0xCD, 0x72, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 132 /* F35SQA512M */ 133 { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 134 /* F35UQA512M */ 135 { 0xCD, 0x60, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 136 137 /* DS35Q1GA-IB */ 138 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 139 /* DS35Q2GA-IB */ 140 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 141 /* DS35M1GA-1B */ 142 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 143 /* DS35M2GA-IB */ 144 { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 145 /* DS35Q1GB-IB */ 146 { 0xE5, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 147 /* DS35Q2GB-IB */ 148 { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 149 /* DS35Q4GM */ 150 { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 151 /* DS35M1GB-IB */ 152 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 153 /* DS35Q12B-IB */ 154 { 0xE5, 0xF5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 155 /* DS35M12B-IB */ 156 { 0xE5, 0xA5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 157 158 /* EM73C044VCC-H */ 159 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 160 /* EM73D044VCE-H */ 161 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 162 /* EM73E044SNA-G */ 163 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 164 /* EM73C044VCF-H */ 165 { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 166 167 /* XT26G02A */ 168 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 169 /* XT26G01A */ 170 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 171 /* XT26G04A */ 172 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 173 /* XT26G01B */ 174 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 175 /* XT26G02B */ 176 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 177 /* XT26G01C */ 178 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 179 /* XT26G02C */ 180 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 181 /* XT26G04C */ 182 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, 183 /* XT26G11C */ 184 { 0x0B, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 185 186 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ 187 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 188 /* MT29F1G01ABA, F50L1G41XA */ 189 { 0x2C, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 190 191 /* FM25S01 */ 192 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 193 /* FM25S01A */ 194 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 195 /* FM25S02A */ 196 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 197 /* FM25LS01 */ 198 { 0xA1, 0xA5, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 199 200 /* IS37SML01G1 */ 201 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 202 /* F50L1G41LB */ 203 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 204 /* ATO25D1GA */ 205 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 206 /* BWJX08K-2Gb */ 207 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 208 /* JS28U1GQSCAHG-83 */ 209 { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 210 /* SGM7000I-S24W1GH */ 211 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 212 /* TX25G01 */ 213 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 214 /* ANV1GCP0CLG */ 215 { 0x01, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status9 }, 216 /* S35ML02G3, ANV1GCP0CLG */ 217 { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, 218 /* S35ML04G3 */ 219 { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, 220 }; 221 222 static struct nand_info *p_nand_info; 223 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 224 static struct SFNAND_DEV sfc_nand_dev; 225 226 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 227 { 228 u32 i; 229 230 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 231 if (spi_nand_tbl[i].id0 == nand_id[0] && 232 spi_nand_tbl[i].id1 == nand_id[1]) { 233 if (spi_nand_tbl[i].id2 && 234 spi_nand_tbl[i].id2 != nand_id[2]) 235 continue; 236 237 return &spi_nand_tbl[i]; 238 } 239 } 240 241 return NULL; 242 } 243 244 static int sfc_nand_write_en(void) 245 { 246 int ret; 247 struct rk_sfc_op op; 248 249 op.sfcmd.d32 = 0; 250 op.sfcmd.b.cmd = CMD_WRITE_EN; 251 252 op.sfctrl.d32 = 0; 253 254 ret = sfc_request(&op, 0, NULL, 0); 255 return ret; 256 } 257 258 static int sfc_nand_rw_preset(void) 259 { 260 int ret; 261 struct rk_sfc_op op; 262 263 op.sfcmd.d32 = 0; 264 op.sfcmd.b.cmd = 0xff; 265 op.sfcmd.b.cs = 2; 266 267 op.sfctrl.d32 = 0; 268 op.sfctrl.b.datalines = 2; 269 op.sfctrl.b.cmdlines = 2; 270 op.sfctrl.b.addrlines = 2; 271 272 ret = sfc_request(&op, 0, NULL, 0); 273 return ret; 274 } 275 276 static int sfc_nand_read_feature(u8 addr, u8 *data) 277 { 278 int ret; 279 struct rk_sfc_op op; 280 281 op.sfcmd.d32 = 0; 282 op.sfcmd.b.cmd = 0x0F; 283 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 284 285 op.sfctrl.d32 = 0; 286 op.sfctrl.b.addrbits = 8; 287 288 *data = 0; 289 290 ret = sfc_request(&op, addr, data, 1); 291 292 if (ret != SFC_OK) 293 return ret; 294 295 return SFC_OK; 296 } 297 298 static int sfc_nand_write_feature(u32 addr, u8 status) 299 { 300 int ret; 301 struct rk_sfc_op op; 302 303 sfc_nand_write_en(); 304 305 op.sfcmd.d32 = 0; 306 op.sfcmd.b.cmd = 0x1F; 307 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 308 op.sfcmd.b.rw = SFC_WRITE; 309 310 op.sfctrl.d32 = 0; 311 op.sfctrl.b.addrbits = 8; 312 313 ret = sfc_request(&op, addr, &status, 1); 314 315 if (ret != SFC_OK) 316 return ret; 317 318 return ret; 319 } 320 321 static int sfc_nand_wait_busy(u8 *data, int timeout) 322 { 323 int ret; 324 int i; 325 u8 status; 326 327 *data = 0; 328 329 for (i = 0; i < timeout; i++) { 330 ret = sfc_nand_read_feature(0xC0, &status); 331 332 if (ret != SFC_OK) 333 return ret; 334 335 *data = status; 336 337 if (!(status & (1 << 0))) 338 return SFC_OK; 339 340 sfc_delay(1); 341 } 342 343 return SFC_NAND_WAIT_TIME_OUT; 344 } 345 346 /* 347 * ecc default: 348 * ecc bits: 0xC0[4,5] 349 * 0b00, No bit errors were detected 350 * 0b01, Bit errors were detected and corrected. 351 * 0b10, Multiple bit errors were detected and not corrected. 352 * 0b11, Bits errors were detected and corrected, bit error count 353 * reach the bit flip detection threshold 354 */ 355 static u32 sfc_nand_get_ecc_status0(void) 356 { 357 u32 ret; 358 u32 i; 359 u8 ecc; 360 u8 status; 361 u32 timeout = 1000 * 1000; 362 363 for (i = 0; i < timeout; i++) { 364 ret = sfc_nand_read_feature(0xC0, &status); 365 366 if (ret != SFC_OK) 367 return SFC_NAND_ECC_ERROR; 368 369 if (!(status & (1 << 0))) 370 break; 371 372 sfc_delay(1); 373 } 374 375 ecc = (status >> 4) & 0x03; 376 377 if (ecc <= 1) 378 ret = SFC_NAND_ECC_OK; 379 else if (ecc == 2) 380 ret = (u32)SFC_NAND_ECC_ERROR; 381 else 382 ret = SFC_NAND_ECC_REFRESH; 383 384 return ret; 385 } 386 387 /* 388 * ecc spectial type1: 389 * ecc bits: 0xC0[4,5] 390 * 0b00, No bit errors were detected; 391 * 0b01, Bits errors were detected and corrected, bit error count 392 * may reach the bit flip detection threshold; 393 * 0b10, Multiple bit errors were detected and not corrected; 394 * 0b11, Reserved. 395 */ 396 static u32 sfc_nand_get_ecc_status1(void) 397 { 398 u32 ret; 399 u32 i; 400 u8 ecc; 401 u8 status; 402 u32 timeout = 1000 * 1000; 403 404 for (i = 0; i < timeout; i++) { 405 ret = sfc_nand_read_feature(0xC0, &status); 406 407 if (ret != SFC_OK) 408 return SFC_NAND_ECC_ERROR; 409 410 if (!(status & (1 << 0))) 411 break; 412 413 sfc_delay(1); 414 } 415 416 ecc = (status >> 4) & 0x03; 417 418 if (ecc == 0) 419 ret = SFC_NAND_ECC_OK; 420 else if (ecc == 1) 421 ret = SFC_NAND_ECC_REFRESH; 422 else 423 ret = (u32)SFC_NAND_ECC_ERROR; 424 425 return ret; 426 } 427 428 /* 429 * ecc spectial type2: 430 * ecc bits: 0xC0[4,5] 0xF0[4,5] 431 * [0b0000, 0b0011], No bit errors were detected; 432 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 433 * reach Flipping Bits; 434 * [0b1000, 0b1011], Multiple bit errors were detected and 435 * not corrected. 436 * [0b1100, 0b1111], reserved. 437 */ 438 static u32 sfc_nand_get_ecc_status2(void) 439 { 440 u32 ret; 441 u32 i; 442 u8 ecc; 443 u8 status, status1; 444 u32 timeout = 1000 * 1000; 445 446 for (i = 0; i < timeout; i++) { 447 ret = sfc_nand_read_feature(0xC0, &status); 448 449 if (ret != SFC_OK) 450 return SFC_NAND_ECC_ERROR; 451 452 ret = sfc_nand_read_feature(0xF0, &status1); 453 454 if (ret != SFC_OK) 455 return SFC_NAND_ECC_ERROR; 456 457 if (!(status & (1 << 0))) 458 break; 459 460 sfc_delay(1); 461 } 462 463 ecc = (status >> 4) & 0x03; 464 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 465 466 if (ecc < 7) 467 ret = SFC_NAND_ECC_OK; 468 else if (ecc == 7) 469 ret = SFC_NAND_ECC_REFRESH; 470 else 471 ret = (u32)SFC_NAND_ECC_ERROR; 472 473 return ret; 474 } 475 476 /* 477 * ecc spectial type3: 478 * ecc bits: 0xC0[4,5] 0xF0[4,5] 479 * [0b0000, 0b0011], No bit errors were detected; 480 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 481 * reach Flipping Bits; 482 * [0b1000, 0b1011], Multiple bit errors were detected and 483 * not corrected. 484 * [0b1100, 0b1111], Bit error count equals the bit flip 485 * detectio nthreshold 486 */ 487 static u32 sfc_nand_get_ecc_status3(void) 488 { 489 u32 ret; 490 u32 i; 491 u8 ecc; 492 u8 status, status1; 493 u32 timeout = 1000 * 1000; 494 495 for (i = 0; i < timeout; i++) { 496 ret = sfc_nand_read_feature(0xC0, &status); 497 498 if (ret != SFC_OK) 499 return SFC_NAND_ECC_ERROR; 500 501 ret = sfc_nand_read_feature(0xF0, &status1); 502 503 if (ret != SFC_OK) 504 return SFC_NAND_ECC_ERROR; 505 506 if (!(status & (1 << 0))) 507 break; 508 509 sfc_delay(1); 510 } 511 512 ecc = (status >> 4) & 0x03; 513 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 514 515 if (ecc < 7) 516 ret = SFC_NAND_ECC_OK; 517 else if (ecc == 7 || ecc >= 12) 518 ret = SFC_NAND_ECC_REFRESH; 519 else 520 ret = (u32)SFC_NAND_ECC_ERROR; 521 522 return ret; 523 } 524 525 /* 526 * ecc spectial type4: 527 * ecc bits: 0xC0[2,5] 528 * [0b0000], No bit errors were detected; 529 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 530 * reach Flipping Bits; 531 * [0b1000], Multiple bit errors were detected and 532 * not corrected. 533 * [0b1100], Bit error count equals the bit flip 534 * detection threshold 535 * else, reserved 536 */ 537 static u32 sfc_nand_get_ecc_status4(void) 538 { 539 u32 ret; 540 u32 i; 541 u8 ecc; 542 u8 status; 543 u32 timeout = 1000 * 1000; 544 545 for (i = 0; i < timeout; i++) { 546 ret = sfc_nand_read_feature(0xC0, &status); 547 548 if (ret != SFC_OK) 549 return SFC_NAND_ECC_ERROR; 550 551 if (!(status & (1 << 0))) 552 break; 553 554 sfc_delay(1); 555 } 556 557 ecc = (status >> 2) & 0x0f; 558 559 if (ecc < 7) 560 ret = SFC_NAND_ECC_OK; 561 else if (ecc == 7 || ecc == 12) 562 ret = SFC_NAND_ECC_REFRESH; 563 else 564 ret = (u32)SFC_NAND_ECC_ERROR; 565 566 return ret; 567 } 568 569 /* 570 * ecc spectial type5: 571 * ecc bits: 0xC0[4,6] 572 * [0b000], No bit errors were detected; 573 * [0b001, 0b011], Bit errors were detected and corrected. Not 574 * reach Flipping Bits; 575 * [0b100], Bit error count equals the bit flip 576 * detection threshold 577 * [0b101, 0b110], Reserved; 578 * [0b111], Multiple bit errors were detected and 579 * not corrected. 580 */ 581 static u32 sfc_nand_get_ecc_status5(void) 582 { 583 u32 ret; 584 u32 i; 585 u8 ecc; 586 u8 status; 587 u32 timeout = 1000 * 1000; 588 589 for (i = 0; i < timeout; i++) { 590 ret = sfc_nand_read_feature(0xC0, &status); 591 592 if (ret != SFC_OK) 593 return SFC_NAND_ECC_ERROR; 594 595 if (!(status & (1 << 0))) 596 break; 597 598 sfc_delay(1); 599 } 600 601 ecc = (status >> 4) & 0x07; 602 603 if (ecc < 4) 604 ret = SFC_NAND_ECC_OK; 605 else if (ecc == 4) 606 ret = SFC_NAND_ECC_REFRESH; 607 else 608 ret = (u32)SFC_NAND_ECC_ERROR; 609 610 return ret; 611 } 612 613 /* 614 * ecc spectial type6: 615 * ecc bits: 0xC0[4,6] 616 * [0b000], No bit errors were detected; 617 * [0b001], 1-3 Bit errors were detected and corrected. Not 618 * reach Flipping Bits; 619 * [0b010], Multiple bit errors were detected and 620 * not corrected. 621 * [0b011], 4-6 Bit errors were detected and corrected. Not 622 * reach Flipping Bits; 623 * [0b101], Bit error count equals the bit flip 624 * detectionthreshold 625 * others, Reserved. 626 */ 627 static u32 sfc_nand_get_ecc_status6(void) 628 { 629 u32 ret; 630 u32 i; 631 u8 ecc; 632 u8 status; 633 u32 timeout = 1000 * 1000; 634 635 for (i = 0; i < timeout; i++) { 636 ret = sfc_nand_read_feature(0xC0, &status); 637 638 if (ret != SFC_OK) 639 return SFC_NAND_ECC_ERROR; 640 641 if (!(status & (1 << 0))) 642 break; 643 644 sfc_delay(1); 645 } 646 647 ecc = (status >> 4) & 0x07; 648 649 if (ecc == 0 || ecc == 1 || ecc == 3) 650 ret = SFC_NAND_ECC_OK; 651 else if (ecc == 5) 652 ret = SFC_NAND_ECC_REFRESH; 653 else 654 ret = (u32)SFC_NAND_ECC_ERROR; 655 656 return ret; 657 } 658 659 /* 660 * ecc spectial type7: 661 * ecc bits: 0xC0[4,7] 662 * [0b0000], No bit errors were detected; 663 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not 664 * reach Flipping Bits; 665 * [0b1000], 8 Bit errors were detected and corrected. Bit error count 666 * equals the bit flip detectionthreshold; 667 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; 668 * others, Reserved. 669 */ 670 static u32 sfc_nand_get_ecc_status7(void) 671 { 672 u32 ret; 673 u32 i; 674 u8 ecc; 675 u8 status; 676 u32 timeout = 1000 * 1000; 677 678 for (i = 0; i < timeout; i++) { 679 ret = sfc_nand_read_feature(0xC0, &status); 680 681 if (ret != SFC_OK) 682 return SFC_NAND_ECC_ERROR; 683 684 if (!(status & (1 << 0))) 685 break; 686 687 sfc_delay(1); 688 } 689 690 ecc = (status >> 4) & 0xf; 691 692 if (ecc < 7) 693 ret = SFC_NAND_ECC_OK; 694 else if (ecc == 7 || ecc == 8) 695 ret = SFC_NAND_ECC_REFRESH; 696 else 697 ret = (u32)SFC_NAND_ECC_ERROR; 698 699 return ret; 700 } 701 702 /* 703 * ecc spectial type8: 704 * ecc bits: 0xC0[4,6] 705 * [0b000], No bit errors were detected; 706 * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not 707 * reach Flipping Bits; 708 * [0b100], Bit error count equals the bit flip 709 * detection threshold 710 * others, Reserved. 711 */ 712 static u32 sfc_nand_get_ecc_status8(void) 713 { 714 u32 ret; 715 u32 i; 716 u8 ecc; 717 u8 status; 718 u32 timeout = 1000 * 1000; 719 720 for (i = 0; i < timeout; i++) { 721 ret = sfc_nand_read_feature(0xC0, &status); 722 723 if (ret != SFC_OK) 724 return SFC_NAND_ECC_ERROR; 725 726 if (!(status & (1 << 0))) 727 break; 728 729 sfc_delay(1); 730 } 731 732 ecc = (status >> 4) & 0x07; 733 734 if (ecc < 4) 735 ret = SFC_NAND_ECC_OK; 736 else if (ecc == 4) 737 ret = SFC_NAND_ECC_REFRESH; 738 else 739 ret = (u32)SFC_NAND_ECC_ERROR; 740 741 return ret; 742 } 743 744 /* 745 * ecc spectial type9: 746 * ecc bits: 0xC0[4,5] 747 * 0b00, No bit errors were detected 748 * 0b01, 1-2Bit errors were detected and corrected. 749 * 0b10, 3-4Bit errors were detected and corrected. 750 * 0b11, 11 can be used as uncorrectable 751 */ 752 static u32 sfc_nand_get_ecc_status9(void) 753 { 754 u32 ret; 755 u32 i; 756 u8 ecc; 757 u8 status; 758 u32 timeout = 1000 * 1000; 759 760 for (i = 0; i < timeout; i++) { 761 ret = sfc_nand_read_feature(0xC0, &status); 762 763 if (ret != SFC_OK) 764 return SFC_NAND_ECC_ERROR; 765 766 if (!(status & (1 << 0))) 767 break; 768 769 sfc_delay(1); 770 } 771 772 ecc = (status >> 4) & 0x03; 773 774 if (ecc <= 1) 775 ret = SFC_NAND_ECC_OK; 776 else if (ecc == 2) 777 ret = SFC_NAND_ECC_REFRESH; 778 else 779 ret = (u32)SFC_NAND_ECC_ERROR; 780 781 return ret; 782 } 783 784 u32 sfc_nand_erase_block(u8 cs, u32 addr) 785 { 786 int ret; 787 struct rk_sfc_op op; 788 u8 status; 789 790 rkflash_print_dio("%s %x\n", __func__, addr); 791 op.sfcmd.d32 = 0; 792 op.sfcmd.b.cmd = 0xd8; 793 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 794 op.sfcmd.b.rw = SFC_WRITE; 795 796 op.sfctrl.d32 = 0; 797 798 sfc_nand_write_en(); 799 ret = sfc_request(&op, addr, NULL, 0); 800 801 if (ret != SFC_OK) 802 return ret; 803 804 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 805 806 if (status & (1 << 2)) 807 return SFC_NAND_PROG_ERASE_ERROR; 808 809 return ret; 810 } 811 812 static u32 sfc_nand_read_cache(u32 row, u32 *p_page_buf, u32 column, u32 len) 813 { 814 int ret; 815 u32 plane; 816 struct rk_sfc_op op; 817 818 op.sfcmd.d32 = 0; 819 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 820 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 821 op.sfcmd.b.dummybits = 8; 822 823 op.sfctrl.d32 = 0; 824 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 825 op.sfctrl.b.addrbits = 16; 826 827 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 828 829 ret = sfc_request(&op, plane | column, p_page_buf, len); 830 if (ret != SFC_OK) 831 return SFC_NAND_HW_ERROR; 832 833 return ret; 834 } 835 836 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 837 { 838 int ret; 839 u32 plane; 840 struct rk_sfc_op op; 841 u8 status; 842 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 843 u32 data_area_size = SFC_NAND_SECTOR_SIZE * p_nand_info->sec_per_page; 844 845 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 846 sfc_nand_write_en(); 847 848 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 849 p_nand_info->feature & FEA_SOFT_QOP_BIT && 850 sfc_get_version() < SFC_VER_3) 851 sfc_nand_rw_preset(); 852 853 op.sfcmd.d32 = 0; 854 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 855 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 856 op.sfcmd.b.rw = SFC_WRITE; 857 858 op.sfctrl.d32 = 0; 859 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 860 op.sfctrl.b.addrbits = 16; 861 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 862 sfc_request(&op, plane, p_page_buf, page_size); 863 864 /* 865 * At the moment of power lost or dev running in harsh environment, flash 866 * maybe work in a unkonw state and result in bit flip, when this situation 867 * is detected by cache recheck, it's better to wait a second for a reliable 868 * hardware environment to avoid abnormal data written to flash array. 869 */ 870 if (p_nand_info->id0 == MID_GIGADEV) { 871 sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size); 872 if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) { 873 rkflash_print_error("%s %x cache bitflip\n", __func__, addr); 874 mdelay(1000); 875 sfc_request(&op, plane, p_page_buf, page_size); 876 } 877 } 878 879 op.sfcmd.d32 = 0; 880 op.sfcmd.b.cmd = 0x10; 881 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 882 op.sfcmd.b.rw = SFC_WRITE; 883 884 op.sfctrl.d32 = 0; 885 ret = sfc_request(&op, addr, p_page_buf, 0); 886 887 if (ret != SFC_OK) 888 return ret; 889 890 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 891 if (status & (1 << 3)) 892 return SFC_NAND_PROG_ERASE_ERROR; 893 894 return ret; 895 } 896 897 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 898 { 899 int ret; 900 u32 sec_per_page = p_nand_info->sec_per_page; 901 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 902 struct nand_mega_area *meta = &p_nand_info->meta; 903 904 memcpy(gp_page_buf, p_data, data_size); 905 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 906 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 907 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 908 909 if (sec_per_page == 8) { 910 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 911 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 912 } 913 914 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 915 916 return ret; 917 } 918 919 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 920 { 921 int ret; 922 u32 plane; 923 struct rk_sfc_op op; 924 u32 ecc_result; 925 u8 status; 926 927 op.sfcmd.d32 = 0; 928 op.sfcmd.b.cmd = 0x13; 929 op.sfcmd.b.rw = SFC_WRITE; 930 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 931 932 op.sfctrl.d32 = 0; 933 934 sfc_request(&op, row, p_page_buf, 0); 935 936 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 937 p_nand_info->feature & FEA_SOFT_QOP_BIT && 938 sfc_get_version() < SFC_VER_3) 939 sfc_nand_rw_preset(); 940 941 sfc_nand_wait_busy(&status, 1000 * 1000); 942 ecc_result = p_nand_info->ecc_status(); 943 944 op.sfcmd.d32 = 0; 945 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 946 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 947 op.sfcmd.b.dummybits = 8; 948 949 op.sfctrl.d32 = 0; 950 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 951 op.sfctrl.b.addrbits = 16; 952 953 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 954 ret = sfc_request(&op, plane | column, p_page_buf, len); 955 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 956 957 if (ret != SFC_OK) 958 return SFC_NAND_HW_ERROR; 959 960 return ecc_result; 961 } 962 963 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 964 { 965 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 966 967 return sfc_nand_read(addr, p_page_buf, 0, page_size); 968 } 969 970 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 971 { 972 u32 ret; 973 u32 sec_per_page = p_nand_info->sec_per_page; 974 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 975 struct nand_mega_area *meta = &p_nand_info->meta; 976 977 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 978 memcpy(p_data, gp_page_buf, data_size); 979 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 980 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 981 982 if (p_nand_info->sec_per_page == 8) { 983 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 984 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 985 } 986 987 if (ret == SFC_NAND_HW_ERROR) 988 ret = SFC_NAND_ECC_ERROR; 989 990 if (ret != SFC_NAND_ECC_OK) { 991 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 992 993 if (p_data) 994 rkflash_print_hex("data:", p_data, 4, 8); 995 996 if (p_spare) 997 rkflash_print_hex("spare:", p_spare, 4, 2); 998 } 999 1000 return ret; 1001 } 1002 1003 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 1004 { 1005 u32 ret; 1006 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 1007 u32 marker = 0; 1008 1009 ret = sfc_nand_read(addr, &marker, data_size, 2); 1010 1011 /* unify with mtd framework */ 1012 if (ret == SFC_NAND_ECC_ERROR || (u16)marker != 0xffff) 1013 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 1014 __func__, addr, ret, marker); 1015 1016 /* Original bad block */ 1017 if ((u16)marker != 0xffff) 1018 return true; 1019 1020 return false; 1021 } 1022 1023 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 1024 { 1025 u32 ret; 1026 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 1027 1028 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 1029 1030 if (ret) 1031 return SFC_NAND_HW_ERROR; 1032 1033 gp_page_buf[data_size / 4] = 0x0; 1034 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 1035 1036 if (ret) 1037 return SFC_NAND_HW_ERROR; 1038 1039 return ret; 1040 } 1041 1042 int sfc_nand_read_id(u8 *data) 1043 { 1044 int ret; 1045 struct rk_sfc_op op; 1046 1047 op.sfcmd.d32 = 0; 1048 op.sfcmd.b.cmd = CMD_READ_JEDECID; 1049 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 1050 1051 op.sfctrl.d32 = 0; 1052 op.sfctrl.b.addrbits = 8; 1053 1054 ret = sfc_request(&op, 0, data, 3); 1055 1056 return ret; 1057 } 1058 1059 /* 1060 * Read the 1st page's 1st byte of a phy_blk 1061 * If not FF, it's bad blk 1062 */ 1063 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 1064 { 1065 u32 bad_cnt, page; 1066 u32 blk_per_die; 1067 u16 blk; 1068 1069 rkflash_print_info("%s\n", __func__); 1070 1071 bad_cnt = 0; 1072 blk_per_die = p_nand_info->plane_per_die * 1073 p_nand_info->blk_per_plane; 1074 1075 for (blk = 0; blk < blk_per_die; blk++) { 1076 page = (blk + blk_per_die * die) * 1077 p_nand_info->page_per_blk; 1078 1079 if (sfc_nand_check_bad_block(die, page)) { 1080 table[bad_cnt++] = blk; 1081 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 1082 } 1083 } 1084 1085 return (int)bad_cnt; 1086 } 1087 1088 void sfc_nand_ftl_ops_init(void) 1089 { 1090 /* para init */ 1091 g_nand_phy_info.nand_type = 1; 1092 g_nand_phy_info.die_num = 1; 1093 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 1094 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 1095 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 1096 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 1097 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 1098 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 1099 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 1100 p_nand_info->page_per_blk; 1101 g_nand_phy_info.reserved_blk = 8; 1102 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 1103 p_nand_info->blk_per_plane; 1104 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 1105 1106 /* driver register */ 1107 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 1108 g_nand_ops.erase_blk = sfc_nand_erase_block; 1109 g_nand_ops.prog_page = sfc_nand_prog_page; 1110 g_nand_ops.read_page = sfc_nand_read_page; 1111 g_nand_ops.bch_sel = NULL; 1112 } 1113 1114 static int sfc_nand_enable_QE(void) 1115 { 1116 int ret = SFC_OK; 1117 u8 status; 1118 1119 ret = sfc_nand_read_feature(0xB0, &status); 1120 1121 if (ret != SFC_OK) 1122 return ret; 1123 1124 if (status & 1) /* is QE bit set */ 1125 return SFC_OK; 1126 1127 status |= 1; 1128 1129 return sfc_nand_write_feature(0xB0, status); 1130 } 1131 1132 u32 sfc_nand_init(void) 1133 { 1134 u8 status, id_byte[8]; 1135 1136 sfc_nand_read_id(id_byte); 1137 rkflash_print_error("sfc_nand id: %x %x %x\n", 1138 id_byte[0], id_byte[1], id_byte[2]); 1139 1140 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 1141 return (u32)FTL_NO_FLASH; 1142 1143 p_nand_info = sfc_nand_get_info(id_byte); 1144 1145 if (!p_nand_info) { 1146 pr_err("The device not support yet!\n"); 1147 1148 return (u32)FTL_UNSUPPORTED_FLASH; 1149 } 1150 1151 sfc_nand_dev.manufacturer = id_byte[0]; 1152 sfc_nand_dev.mem_type = id_byte[1]; 1153 sfc_nand_dev.capacity = p_nand_info->density; 1154 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 1155 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 1156 1157 /* disable block lock */ 1158 sfc_nand_write_feature(0xA0, 0); 1159 sfc_nand_dev.read_lines = DATA_LINES_X1; 1160 sfc_nand_dev.prog_lines = DATA_LINES_X1; 1161 sfc_nand_dev.page_read_cmd = 0x03; 1162 sfc_nand_dev.page_prog_cmd = 0x02; 1163 sfc_nand_dev.recheck_buffer = ftl_malloc(SFC_NAND_PAGE_MAX_SIZE); 1164 if (!sfc_nand_dev.recheck_buffer) { 1165 rkflash_print_error("%s recheck_buffer alloc failed\n", __func__); 1166 return -1; 1167 } 1168 1169 if (p_nand_info->feature & FEA_4BIT_READ) { 1170 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 1171 !p_nand_info->has_qe_bits) { 1172 sfc_nand_dev.read_lines = DATA_LINES_X4; 1173 sfc_nand_dev.page_read_cmd = 0x6b; 1174 } 1175 } 1176 1177 if (p_nand_info->feature & FEA_4BIT_PROG && 1178 sfc_nand_dev.read_lines == DATA_LINES_X4) { 1179 sfc_nand_dev.prog_lines = DATA_LINES_X4; 1180 sfc_nand_dev.page_prog_cmd = 0x32; 1181 } 1182 1183 sfc_nand_read_feature(0xA0, &status); 1184 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 1185 sfc_nand_read_feature(0xB0, &status); 1186 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 1187 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 1188 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 1189 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 1190 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 1191 1192 return SFC_OK; 1193 } 1194 1195 void sfc_nand_deinit(void) 1196 { 1197 /* to-do */ 1198 kfree(sfc_nand_dev.recheck_buffer); 1199 } 1200 1201 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 1202 { 1203 return &sfc_nand_dev; 1204 } 1205 1206