1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 static u32 sfc_nand_get_ecc_status7(void); 25 static u32 sfc_nand_get_ecc_status8(void); 26 27 static struct nand_info spi_nand_tbl[] = { 28 /* TC58CVG0S0HxAIx */ 29 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 30 /* TC58CVG1S0HxAIx */ 31 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 32 /* TC58CVG2S0HRAIJ */ 33 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 34 /* TC58CVG1S3HRAIJ */ 35 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 36 /* TC58CVG0S3HRAIJ */ 37 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 38 39 /* MX35LF1GE4AB */ 40 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 41 /* MX35LF2GE4AB */ 42 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 43 /* MX35LF2GE4AD */ 44 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 45 /* MX35LF4GE4AD */ 46 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 47 /* MX35UF1GE4AC */ 48 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 49 /* MX35UF2GE4AC */ 50 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 51 52 /* GD5F1GQ4UAYIG */ 53 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 54 /* GD5F1GQ4RB9IGR */ 55 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 56 /* GD5F2GQ40BY2GR */ 57 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 58 /* GD5F1GQ5UEYIG */ 59 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 60 /* GD5F2GQ5UEYIG */ 61 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 62 /* GD5F1GQ4R */ 63 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 64 /* GD5F4GQ6RExxG 1*4096 */ 65 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 66 /* GD5F4GQ6UExxG 1*4096 */ 67 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 68 /* GD5F1GQ4UExxH */ 69 { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 70 /* GD5F1GQ5REYIG */ 71 { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 72 /* GD5F2GQ5REYIG */ 73 { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 74 /* GD5F2GM7RxG */ 75 { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 76 /* GD5F2GM7UxG */ 77 { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 78 /* GD5F1GM7UxG */ 79 { 0xC8, 0x91, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 80 81 /* W25N01GV */ 82 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 83 /* W25N02KVZEIR */ 84 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 85 /* W25N04KVZEIR */ 86 { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 }, 87 /* W25N01GW */ 88 { 0xEF, 0xBA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 89 /* W25N512GVEIG */ 90 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 91 92 /* HYF2GQ4UAACAE */ 93 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 94 /* HYF1GQ4UDACAE */ 95 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 96 /* HYF1GQ4UPACAE */ 97 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 98 /* HYF2GQ4UDACAE */ 99 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 100 /* HYF2GQ4UHCCAE */ 101 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 102 /* HYF4GQ4UAACBE */ 103 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 104 105 /* FS35ND01G-S1 */ 106 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 107 /* FS35ND02G-S2 */ 108 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 109 /* FS35ND01G-S1Y2 */ 110 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 111 /* FS35ND02G-S3Y2 */ 112 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 113 /* FS35ND04G-S2Y2 1*4096 */ 114 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 115 /* F35SQA001G */ 116 { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 117 /* F35SQA002G */ 118 { 0xCD, 0x72, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 119 120 /* DS35Q1GA-IB */ 121 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 122 /* DS35Q2GA-IB */ 123 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 124 /* DS35M1GA-1B */ 125 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 126 /* DS35M2GA-IB */ 127 { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 128 /* DS35Q2GB-IB */ 129 { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 130 /* DS35M1GB-IB */ 131 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 132 133 /* EM73C044VCC-H */ 134 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 135 /* EM73D044VCE-H */ 136 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 137 /* EM73E044SNA-G */ 138 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 139 /* EM73C044VCF-H */ 140 { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 141 142 /* XT26G02A */ 143 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 144 /* XT26G01A */ 145 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 146 /* XT26G04A */ 147 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 148 /* XT26G01B */ 149 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 150 /* XT26G02B */ 151 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 152 /* XT26G01C */ 153 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 154 /* XT26G02C */ 155 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 156 /* XT26G04C */ 157 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, 158 /* XT26G11C */ 159 { 0x0B, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 160 161 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ 162 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 163 /* MT29F1G01ABA, F50L1G41XA */ 164 { 0x2C, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 165 166 /* FM25S01 */ 167 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 168 /* FM25S01A */ 169 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 170 /* FM25S02A */ 171 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 172 173 /* IS37SML01G1 */ 174 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 175 /* F50L1G41LB */ 176 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 177 /* ATO25D1GA */ 178 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 179 /* BWJX08K-2Gb */ 180 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 181 /* JS28U1GQSCAHG-83 */ 182 { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 183 /* SGM7000I-S24W1GH */ 184 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 185 /* TX25G01 */ 186 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 187 }; 188 189 static struct nand_info *p_nand_info; 190 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 191 static struct SFNAND_DEV sfc_nand_dev; 192 193 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 194 { 195 u32 i; 196 197 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 198 if (spi_nand_tbl[i].id0 == nand_id[0] && 199 spi_nand_tbl[i].id1 == nand_id[1]) { 200 if (spi_nand_tbl[i].id2 && 201 spi_nand_tbl[i].id2 != nand_id[2]) 202 continue; 203 204 return &spi_nand_tbl[i]; 205 } 206 } 207 208 return NULL; 209 } 210 211 static int sfc_nand_write_en(void) 212 { 213 int ret; 214 struct rk_sfc_op op; 215 216 op.sfcmd.d32 = 0; 217 op.sfcmd.b.cmd = CMD_WRITE_EN; 218 219 op.sfctrl.d32 = 0; 220 221 ret = sfc_request(&op, 0, NULL, 0); 222 return ret; 223 } 224 225 static int sfc_nand_rw_preset(void) 226 { 227 int ret; 228 struct rk_sfc_op op; 229 230 op.sfcmd.d32 = 0; 231 op.sfcmd.b.cmd = 0xff; 232 op.sfcmd.b.cs = 2; 233 234 op.sfctrl.d32 = 0; 235 op.sfctrl.b.datalines = 2; 236 op.sfctrl.b.cmdlines = 2; 237 op.sfctrl.b.addrlines = 2; 238 239 ret = sfc_request(&op, 0, NULL, 0); 240 return ret; 241 } 242 243 static int sfc_nand_read_feature(u8 addr, u8 *data) 244 { 245 int ret; 246 struct rk_sfc_op op; 247 248 op.sfcmd.d32 = 0; 249 op.sfcmd.b.cmd = 0x0F; 250 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 251 252 op.sfctrl.d32 = 0; 253 op.sfctrl.b.addrbits = 8; 254 255 *data = 0; 256 257 ret = sfc_request(&op, addr, data, 1); 258 259 if (ret != SFC_OK) 260 return ret; 261 262 return SFC_OK; 263 } 264 265 static int sfc_nand_write_feature(u32 addr, u8 status) 266 { 267 int ret; 268 struct rk_sfc_op op; 269 270 sfc_nand_write_en(); 271 272 op.sfcmd.d32 = 0; 273 op.sfcmd.b.cmd = 0x1F; 274 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 275 op.sfcmd.b.rw = SFC_WRITE; 276 277 op.sfctrl.d32 = 0; 278 op.sfctrl.b.addrbits = 8; 279 280 ret = sfc_request(&op, addr, &status, 1); 281 282 if (ret != SFC_OK) 283 return ret; 284 285 return ret; 286 } 287 288 static int sfc_nand_wait_busy(u8 *data, int timeout) 289 { 290 int ret; 291 int i; 292 u8 status; 293 294 *data = 0; 295 296 for (i = 0; i < timeout; i++) { 297 ret = sfc_nand_read_feature(0xC0, &status); 298 299 if (ret != SFC_OK) 300 return ret; 301 302 *data = status; 303 304 if (!(status & (1 << 0))) 305 return SFC_OK; 306 307 sfc_delay(1); 308 } 309 310 return SFC_NAND_WAIT_TIME_OUT; 311 } 312 313 /* 314 * ecc default: 315 * ecc bits: 0xC0[4,5] 316 * 0b00, No bit errors were detected 317 * 0b01, Bit errors were detected and corrected. 318 * 0b10, Multiple bit errors were detected and not corrected. 319 * 0b11, Bits errors were detected and corrected, bit error count 320 * reach the bit flip detection threshold 321 */ 322 static u32 sfc_nand_get_ecc_status0(void) 323 { 324 u32 ret; 325 u32 i; 326 u8 ecc; 327 u8 status; 328 u32 timeout = 1000 * 1000; 329 330 for (i = 0; i < timeout; i++) { 331 ret = sfc_nand_read_feature(0xC0, &status); 332 333 if (ret != SFC_OK) 334 return SFC_NAND_ECC_ERROR; 335 336 if (!(status & (1 << 0))) 337 break; 338 339 sfc_delay(1); 340 } 341 342 ecc = (status >> 4) & 0x03; 343 344 if (ecc <= 1) 345 ret = SFC_NAND_ECC_OK; 346 else if (ecc == 2) 347 ret = (u32)SFC_NAND_ECC_ERROR; 348 else 349 ret = SFC_NAND_ECC_REFRESH; 350 351 return ret; 352 } 353 354 /* 355 * ecc spectial type1: 356 * ecc bits: 0xC0[4,5] 357 * 0b00, No bit errors were detected; 358 * 0b01, Bits errors were detected and corrected, bit error count 359 * may reach the bit flip detection threshold; 360 * 0b10, Multiple bit errors were detected and not corrected; 361 * 0b11, Reserved. 362 */ 363 static u32 sfc_nand_get_ecc_status1(void) 364 { 365 u32 ret; 366 u32 i; 367 u8 ecc; 368 u8 status; 369 u32 timeout = 1000 * 1000; 370 371 for (i = 0; i < timeout; i++) { 372 ret = sfc_nand_read_feature(0xC0, &status); 373 374 if (ret != SFC_OK) 375 return SFC_NAND_ECC_ERROR; 376 377 if (!(status & (1 << 0))) 378 break; 379 380 sfc_delay(1); 381 } 382 383 ecc = (status >> 4) & 0x03; 384 385 if (ecc == 0) 386 ret = SFC_NAND_ECC_OK; 387 else if (ecc == 1) 388 ret = SFC_NAND_ECC_REFRESH; 389 else 390 ret = (u32)SFC_NAND_ECC_ERROR; 391 392 return ret; 393 } 394 395 /* 396 * ecc spectial type2: 397 * ecc bits: 0xC0[4,5] 0xF0[4,5] 398 * [0b0000, 0b0011], No bit errors were detected; 399 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 400 * reach Flipping Bits; 401 * [0b1000, 0b1011], Multiple bit errors were detected and 402 * not corrected. 403 * [0b1100, 0b1111], reserved. 404 */ 405 static u32 sfc_nand_get_ecc_status2(void) 406 { 407 u32 ret; 408 u32 i; 409 u8 ecc; 410 u8 status, status1; 411 u32 timeout = 1000 * 1000; 412 413 for (i = 0; i < timeout; i++) { 414 ret = sfc_nand_read_feature(0xC0, &status); 415 416 if (ret != SFC_OK) 417 return SFC_NAND_ECC_ERROR; 418 419 ret = sfc_nand_read_feature(0xF0, &status1); 420 421 if (ret != SFC_OK) 422 return SFC_NAND_ECC_ERROR; 423 424 if (!(status & (1 << 0))) 425 break; 426 427 sfc_delay(1); 428 } 429 430 ecc = (status >> 4) & 0x03; 431 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 432 433 if (ecc < 7) 434 ret = SFC_NAND_ECC_OK; 435 else if (ecc == 7) 436 ret = SFC_NAND_ECC_REFRESH; 437 else 438 ret = (u32)SFC_NAND_ECC_ERROR; 439 440 return ret; 441 } 442 443 /* 444 * ecc spectial type3: 445 * ecc bits: 0xC0[4,5] 0xF0[4,5] 446 * [0b0000, 0b0011], No bit errors were detected; 447 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 448 * reach Flipping Bits; 449 * [0b1000, 0b1011], Multiple bit errors were detected and 450 * not corrected. 451 * [0b1100, 0b1111], Bit error count equals the bit flip 452 * detectio nthreshold 453 */ 454 static u32 sfc_nand_get_ecc_status3(void) 455 { 456 u32 ret; 457 u32 i; 458 u8 ecc; 459 u8 status, status1; 460 u32 timeout = 1000 * 1000; 461 462 for (i = 0; i < timeout; i++) { 463 ret = sfc_nand_read_feature(0xC0, &status); 464 465 if (ret != SFC_OK) 466 return SFC_NAND_ECC_ERROR; 467 468 ret = sfc_nand_read_feature(0xF0, &status1); 469 470 if (ret != SFC_OK) 471 return SFC_NAND_ECC_ERROR; 472 473 if (!(status & (1 << 0))) 474 break; 475 476 sfc_delay(1); 477 } 478 479 ecc = (status >> 4) & 0x03; 480 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 481 482 if (ecc < 7) 483 ret = SFC_NAND_ECC_OK; 484 else if (ecc == 7 || ecc >= 12) 485 ret = SFC_NAND_ECC_REFRESH; 486 else 487 ret = (u32)SFC_NAND_ECC_ERROR; 488 489 return ret; 490 } 491 492 /* 493 * ecc spectial type4: 494 * ecc bits: 0xC0[2,5] 495 * [0b0000], No bit errors were detected; 496 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 497 * reach Flipping Bits; 498 * [0b1000], Multiple bit errors were detected and 499 * not corrected. 500 * [0b1100], Bit error count equals the bit flip 501 * detection threshold 502 * else, reserved 503 */ 504 static u32 sfc_nand_get_ecc_status4(void) 505 { 506 u32 ret; 507 u32 i; 508 u8 ecc; 509 u8 status; 510 u32 timeout = 1000 * 1000; 511 512 for (i = 0; i < timeout; i++) { 513 ret = sfc_nand_read_feature(0xC0, &status); 514 515 if (ret != SFC_OK) 516 return SFC_NAND_ECC_ERROR; 517 518 if (!(status & (1 << 0))) 519 break; 520 521 sfc_delay(1); 522 } 523 524 ecc = (status >> 2) & 0x0f; 525 526 if (ecc < 7) 527 ret = SFC_NAND_ECC_OK; 528 else if (ecc == 7 || ecc == 12) 529 ret = SFC_NAND_ECC_REFRESH; 530 else 531 ret = (u32)SFC_NAND_ECC_ERROR; 532 533 return ret; 534 } 535 536 /* 537 * ecc spectial type5: 538 * ecc bits: 0xC0[4,6] 539 * [0b000], No bit errors were detected; 540 * [0b001, 0b011], Bit errors were detected and corrected. Not 541 * reach Flipping Bits; 542 * [0b100], Bit error count equals the bit flip 543 * detection threshold 544 * [0b101, 0b110], Reserved; 545 * [0b111], Multiple bit errors were detected and 546 * not corrected. 547 */ 548 static u32 sfc_nand_get_ecc_status5(void) 549 { 550 u32 ret; 551 u32 i; 552 u8 ecc; 553 u8 status; 554 u32 timeout = 1000 * 1000; 555 556 for (i = 0; i < timeout; i++) { 557 ret = sfc_nand_read_feature(0xC0, &status); 558 559 if (ret != SFC_OK) 560 return SFC_NAND_ECC_ERROR; 561 562 if (!(status & (1 << 0))) 563 break; 564 565 sfc_delay(1); 566 } 567 568 ecc = (status >> 4) & 0x07; 569 570 if (ecc < 4) 571 ret = SFC_NAND_ECC_OK; 572 else if (ecc == 4) 573 ret = SFC_NAND_ECC_REFRESH; 574 else 575 ret = (u32)SFC_NAND_ECC_ERROR; 576 577 return ret; 578 } 579 580 /* 581 * ecc spectial type6: 582 * ecc bits: 0xC0[4,6] 583 * [0b000], No bit errors were detected; 584 * [0b001], 1-3 Bit errors were detected and corrected. Not 585 * reach Flipping Bits; 586 * [0b010], Multiple bit errors were detected and 587 * not corrected. 588 * [0b011], 4-6 Bit errors were detected and corrected. Not 589 * reach Flipping Bits; 590 * [0b101], Bit error count equals the bit flip 591 * detectionthreshold 592 * others, Reserved. 593 */ 594 static u32 sfc_nand_get_ecc_status6(void) 595 { 596 u32 ret; 597 u32 i; 598 u8 ecc; 599 u8 status; 600 u32 timeout = 1000 * 1000; 601 602 for (i = 0; i < timeout; i++) { 603 ret = sfc_nand_read_feature(0xC0, &status); 604 605 if (ret != SFC_OK) 606 return SFC_NAND_ECC_ERROR; 607 608 if (!(status & (1 << 0))) 609 break; 610 611 sfc_delay(1); 612 } 613 614 ecc = (status >> 4) & 0x07; 615 616 if (ecc == 0 || ecc == 1 || ecc == 3) 617 ret = SFC_NAND_ECC_OK; 618 else if (ecc == 5) 619 ret = SFC_NAND_ECC_REFRESH; 620 else 621 ret = (u32)SFC_NAND_ECC_ERROR; 622 623 return ret; 624 } 625 626 /* 627 * ecc spectial type7: 628 * ecc bits: 0xC0[4,7] 629 * [0b0000], No bit errors were detected; 630 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not 631 * reach Flipping Bits; 632 * [0b1000], 8 Bit errors were detected and corrected. Bit error count 633 * equals the bit flip detectionthreshold; 634 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; 635 * others, Reserved. 636 */ 637 static u32 sfc_nand_get_ecc_status7(void) 638 { 639 u32 ret; 640 u32 i; 641 u8 ecc; 642 u8 status; 643 u32 timeout = 1000 * 1000; 644 645 for (i = 0; i < timeout; i++) { 646 ret = sfc_nand_read_feature(0xC0, &status); 647 648 if (ret != SFC_OK) 649 return SFC_NAND_ECC_ERROR; 650 651 if (!(status & (1 << 0))) 652 break; 653 654 sfc_delay(1); 655 } 656 657 ecc = (status >> 4) & 0xf; 658 659 if (ecc < 7) 660 ret = SFC_NAND_ECC_OK; 661 else if (ecc == 7 || ecc == 8) 662 ret = SFC_NAND_ECC_REFRESH; 663 else 664 ret = (u32)SFC_NAND_ECC_ERROR; 665 666 return ret; 667 } 668 669 /* 670 * ecc spectial type8: 671 * ecc bits: 0xC0[4,6] 672 * [0b000], No bit errors were detected; 673 * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not 674 * reach Flipping Bits; 675 * [0b100], Bit error count equals the bit flip 676 * detection threshold 677 * others, Reserved. 678 */ 679 static u32 sfc_nand_get_ecc_status8(void) 680 { 681 u32 ret; 682 u32 i; 683 u8 ecc; 684 u8 status; 685 u32 timeout = 1000 * 1000; 686 687 for (i = 0; i < timeout; i++) { 688 ret = sfc_nand_read_feature(0xC0, &status); 689 690 if (ret != SFC_OK) 691 return SFC_NAND_ECC_ERROR; 692 693 if (!(status & (1 << 0))) 694 break; 695 696 sfc_delay(1); 697 } 698 699 ecc = (status >> 4) & 0x07; 700 701 if (ecc < 4) 702 ret = SFC_NAND_ECC_OK; 703 else if (ecc == 4) 704 ret = SFC_NAND_ECC_REFRESH; 705 else 706 ret = (u32)SFC_NAND_ECC_ERROR; 707 708 return ret; 709 } 710 711 u32 sfc_nand_erase_block(u8 cs, u32 addr) 712 { 713 int ret; 714 struct rk_sfc_op op; 715 u8 status; 716 717 rkflash_print_dio("%s %x\n", __func__, addr); 718 op.sfcmd.d32 = 0; 719 op.sfcmd.b.cmd = 0xd8; 720 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 721 op.sfcmd.b.rw = SFC_WRITE; 722 723 op.sfctrl.d32 = 0; 724 725 sfc_nand_write_en(); 726 ret = sfc_request(&op, addr, NULL, 0); 727 728 if (ret != SFC_OK) 729 return ret; 730 731 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 732 733 if (status & (1 << 2)) 734 return SFC_NAND_PROG_ERASE_ERROR; 735 736 return ret; 737 } 738 739 static u32 sfc_nand_read_cache(u32 row, u32 *p_page_buf, u32 column, u32 len) 740 { 741 int ret; 742 u32 plane; 743 struct rk_sfc_op op; 744 745 op.sfcmd.d32 = 0; 746 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 747 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 748 op.sfcmd.b.dummybits = 8; 749 750 op.sfctrl.d32 = 0; 751 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 752 op.sfctrl.b.addrbits = 16; 753 754 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 755 756 ret = sfc_request(&op, plane | column, p_page_buf, len); 757 if (ret != SFC_OK) 758 return SFC_NAND_HW_ERROR; 759 760 return ret; 761 } 762 763 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 764 { 765 int ret; 766 u32 plane; 767 struct rk_sfc_op op; 768 u8 status; 769 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 770 u32 data_area_size = SFC_NAND_SECTOR_SIZE * p_nand_info->sec_per_page; 771 772 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 773 sfc_nand_write_en(); 774 775 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 776 p_nand_info->feature & FEA_SOFT_QOP_BIT && 777 sfc_get_version() < SFC_VER_3) 778 sfc_nand_rw_preset(); 779 780 op.sfcmd.d32 = 0; 781 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 782 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 783 op.sfcmd.b.rw = SFC_WRITE; 784 785 op.sfctrl.d32 = 0; 786 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 787 op.sfctrl.b.addrbits = 16; 788 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 789 sfc_request(&op, plane, p_page_buf, page_size); 790 791 /* 792 * At the moment of power lost or dev running in harsh environment, flash 793 * maybe work in a unkonw state and result in bit flip, when this situation 794 * is detected by cache recheck, it's better to wait a second for a reliable 795 * hardware environment to avoid abnormal data written to flash array. 796 */ 797 if (p_nand_info->id0 == MID_GIGADEV) { 798 sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size); 799 if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) { 800 rkflash_print_error("%s %x cache bitflip\n", __func__, addr); 801 mdelay(1000); 802 sfc_request(&op, plane, p_page_buf, page_size); 803 } 804 } 805 806 op.sfcmd.d32 = 0; 807 op.sfcmd.b.cmd = 0x10; 808 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 809 op.sfcmd.b.rw = SFC_WRITE; 810 811 op.sfctrl.d32 = 0; 812 ret = sfc_request(&op, addr, p_page_buf, 0); 813 814 if (ret != SFC_OK) 815 return ret; 816 817 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 818 if (status & (1 << 3)) 819 return SFC_NAND_PROG_ERASE_ERROR; 820 821 return ret; 822 } 823 824 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 825 { 826 int ret; 827 u32 sec_per_page = p_nand_info->sec_per_page; 828 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 829 struct nand_mega_area *meta = &p_nand_info->meta; 830 831 memcpy(gp_page_buf, p_data, data_size); 832 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 833 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 834 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 835 836 if (sec_per_page == 8) { 837 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 838 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 839 } 840 841 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 842 843 return ret; 844 } 845 846 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 847 { 848 int ret; 849 u32 plane; 850 struct rk_sfc_op op; 851 u32 ecc_result; 852 u8 status; 853 854 op.sfcmd.d32 = 0; 855 op.sfcmd.b.cmd = 0x13; 856 op.sfcmd.b.rw = SFC_WRITE; 857 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 858 859 op.sfctrl.d32 = 0; 860 861 sfc_request(&op, row, p_page_buf, 0); 862 863 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 864 p_nand_info->feature & FEA_SOFT_QOP_BIT && 865 sfc_get_version() < SFC_VER_3) 866 sfc_nand_rw_preset(); 867 868 sfc_nand_wait_busy(&status, 1000 * 1000); 869 ecc_result = p_nand_info->ecc_status(); 870 871 op.sfcmd.d32 = 0; 872 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 873 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 874 op.sfcmd.b.dummybits = 8; 875 876 op.sfctrl.d32 = 0; 877 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 878 op.sfctrl.b.addrbits = 16; 879 880 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 881 ret = sfc_request(&op, plane | column, p_page_buf, len); 882 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 883 884 if (ret != SFC_OK) 885 return SFC_NAND_HW_ERROR; 886 887 return ecc_result; 888 } 889 890 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 891 { 892 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 893 894 return sfc_nand_read(addr, p_page_buf, 0, page_size); 895 } 896 897 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 898 { 899 u32 ret; 900 u32 sec_per_page = p_nand_info->sec_per_page; 901 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 902 struct nand_mega_area *meta = &p_nand_info->meta; 903 904 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 905 memcpy(p_data, gp_page_buf, data_size); 906 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 907 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 908 909 if (p_nand_info->sec_per_page == 8) { 910 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 911 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 912 } 913 914 if (ret == SFC_NAND_HW_ERROR) 915 ret = SFC_NAND_ECC_ERROR; 916 917 if (ret != SFC_NAND_ECC_OK) { 918 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 919 920 if (p_data) 921 rkflash_print_hex("data:", p_data, 4, 8); 922 923 if (p_spare) 924 rkflash_print_hex("spare:", p_spare, 4, 2); 925 } 926 927 return ret; 928 } 929 930 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 931 { 932 u32 ret; 933 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 934 u32 marker = 0; 935 936 ret = sfc_nand_read(addr, &marker, data_size, 2); 937 938 /* unify with mtd framework */ 939 if (ret == SFC_NAND_ECC_ERROR || (u16)marker != 0xffff) 940 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 941 __func__, addr, ret, marker); 942 943 /* Original bad block */ 944 if ((u16)marker != 0xffff) 945 return true; 946 947 return false; 948 } 949 950 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 951 { 952 u32 ret; 953 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 954 955 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 956 957 if (ret) 958 return SFC_NAND_HW_ERROR; 959 960 gp_page_buf[data_size / 4] = 0x0; 961 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 962 963 if (ret) 964 return SFC_NAND_HW_ERROR; 965 966 return ret; 967 } 968 969 int sfc_nand_read_id(u8 *data) 970 { 971 int ret; 972 struct rk_sfc_op op; 973 974 op.sfcmd.d32 = 0; 975 op.sfcmd.b.cmd = CMD_READ_JEDECID; 976 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 977 978 op.sfctrl.d32 = 0; 979 op.sfctrl.b.addrbits = 8; 980 981 ret = sfc_request(&op, 0, data, 3); 982 983 return ret; 984 } 985 986 /* 987 * Read the 1st page's 1st byte of a phy_blk 988 * If not FF, it's bad blk 989 */ 990 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 991 { 992 u32 bad_cnt, page; 993 u32 blk_per_die; 994 u16 blk; 995 996 rkflash_print_info("%s\n", __func__); 997 998 bad_cnt = 0; 999 blk_per_die = p_nand_info->plane_per_die * 1000 p_nand_info->blk_per_plane; 1001 1002 for (blk = 0; blk < blk_per_die; blk++) { 1003 page = (blk + blk_per_die * die) * 1004 p_nand_info->page_per_blk; 1005 1006 if (sfc_nand_check_bad_block(die, page)) { 1007 table[bad_cnt++] = blk; 1008 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 1009 } 1010 } 1011 1012 return (int)bad_cnt; 1013 } 1014 1015 void sfc_nand_ftl_ops_init(void) 1016 { 1017 /* para init */ 1018 g_nand_phy_info.nand_type = 1; 1019 g_nand_phy_info.die_num = 1; 1020 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 1021 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 1022 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 1023 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 1024 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 1025 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 1026 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 1027 p_nand_info->page_per_blk; 1028 g_nand_phy_info.reserved_blk = 8; 1029 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 1030 p_nand_info->blk_per_plane; 1031 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 1032 1033 /* driver register */ 1034 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 1035 g_nand_ops.erase_blk = sfc_nand_erase_block; 1036 g_nand_ops.prog_page = sfc_nand_prog_page; 1037 g_nand_ops.read_page = sfc_nand_read_page; 1038 g_nand_ops.bch_sel = NULL; 1039 } 1040 1041 static int sfc_nand_enable_QE(void) 1042 { 1043 int ret = SFC_OK; 1044 u8 status; 1045 1046 ret = sfc_nand_read_feature(0xB0, &status); 1047 1048 if (ret != SFC_OK) 1049 return ret; 1050 1051 if (status & 1) /* is QE bit set */ 1052 return SFC_OK; 1053 1054 status |= 1; 1055 1056 return sfc_nand_write_feature(0xB0, status); 1057 } 1058 1059 u32 sfc_nand_init(void) 1060 { 1061 u8 status, id_byte[8]; 1062 1063 sfc_nand_read_id(id_byte); 1064 rkflash_print_error("sfc_nand id: %x %x %x\n", 1065 id_byte[0], id_byte[1], id_byte[2]); 1066 1067 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 1068 return (u32)FTL_NO_FLASH; 1069 1070 p_nand_info = sfc_nand_get_info(id_byte); 1071 1072 if (!p_nand_info) { 1073 pr_err("The device not support yet!\n"); 1074 1075 return (u32)FTL_UNSUPPORTED_FLASH; 1076 } 1077 1078 sfc_nand_dev.manufacturer = id_byte[0]; 1079 sfc_nand_dev.mem_type = id_byte[1]; 1080 sfc_nand_dev.capacity = p_nand_info->density; 1081 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 1082 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 1083 1084 /* disable block lock */ 1085 sfc_nand_write_feature(0xA0, 0); 1086 sfc_nand_dev.read_lines = DATA_LINES_X1; 1087 sfc_nand_dev.prog_lines = DATA_LINES_X1; 1088 sfc_nand_dev.page_read_cmd = 0x03; 1089 sfc_nand_dev.page_prog_cmd = 0x02; 1090 sfc_nand_dev.recheck_buffer = ftl_malloc(SFC_NAND_PAGE_MAX_SIZE); 1091 if (!sfc_nand_dev.recheck_buffer) { 1092 rkflash_print_error("%s recheck_buffer alloc failed\n", __func__); 1093 return -1; 1094 } 1095 1096 if (p_nand_info->feature & FEA_4BIT_READ) { 1097 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 1098 !p_nand_info->has_qe_bits) { 1099 sfc_nand_dev.read_lines = DATA_LINES_X4; 1100 sfc_nand_dev.page_read_cmd = 0x6b; 1101 } 1102 } 1103 1104 if (p_nand_info->feature & FEA_4BIT_PROG && 1105 sfc_nand_dev.read_lines == DATA_LINES_X4) { 1106 sfc_nand_dev.prog_lines = DATA_LINES_X4; 1107 sfc_nand_dev.page_prog_cmd = 0x32; 1108 } 1109 1110 sfc_nand_read_feature(0xA0, &status); 1111 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 1112 sfc_nand_read_feature(0xB0, &status); 1113 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 1114 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 1115 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 1116 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 1117 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 1118 1119 return SFC_OK; 1120 } 1121 1122 void sfc_nand_deinit(void) 1123 { 1124 /* to-do */ 1125 kfree(sfc_nand_dev.recheck_buffer); 1126 } 1127 1128 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 1129 { 1130 return &sfc_nand_dev; 1131 } 1132 1133