1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 25 static struct nand_info spi_nand_tbl[] = { 26 /* TC58CVG0S0HxAIx */ 27 { 0x98C2, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 28 /* TC58CVG1S0HxAIx */ 29 { 0x98CB, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 30 /* TC58CVG2S0HRAIJ */ 31 { 0x98ED, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 32 /* TC58CVG1S3HRAIJ */ 33 { 0x98EB, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 34 /* TC58CVG0S3HRAIJ */ 35 { 0x98E2, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 36 37 /* MX35LF1GE4AB */ 38 { 0xC212, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 39 /* MX35LF2GE4AB */ 40 { 0xC222, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 41 /* MX35LF2GE4AD */ 42 { 0xC226, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 43 /* MX35LF4GE4AD */ 44 { 0xC237, 8, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 45 /* MT29F1G01ZAC */ 46 { 0x2C12, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 47 48 /* GD5F1GQ4UAYIG */ 49 { 0xC8F1, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 50 /* GD5F1GQ4RB9IGR */ 51 { 0xC8D1, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 52 /* GD5F2GQ40BY2GR */ 53 { 0xC8D2, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 54 /* GD5F1GQ5UEYIG */ 55 { 0xC851, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 56 /* GD5F2GQ5UEYIG */ 57 { 0xC852, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 58 /* GD5F1GQ4R */ 59 { 0xC8C1, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 60 61 /* W25N01GV */ 62 { 0xEFAA, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 63 /* W25N01GW */ 64 { 0xEFBA, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 65 66 /* HYF2GQ4UAACAE */ 67 { 0xC952, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 68 /* HYF1GQ4UDACAE */ 69 { 0xC921, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 70 /* HYF1GQ4UPACAE */ 71 { 0xC9A1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 72 /* HYF2GQ4UDACAE */ 73 { 0xC922, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 74 /* HYF2GQ4UHCCAE */ 75 { 0xC95A, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 76 /* HYF4GQ4UAACBE */ 77 { 0xC9D4, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 78 79 /* FS35ND01G-S1 */ 80 { 0xCDB1, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 81 /* FS35ND02G-S2 */ 82 { 0xCDA2, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 83 /* FS35ND01G-S1Y2 */ 84 { 0xCDEA, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 85 /* FS35ND02G-S3Y2 */ 86 { 0xCDEB, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 87 /* FS35ND04G-S2Y2 1*4096 */ 88 { 0xCDEC, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 89 90 /* DS35Q1GA-IB */ 91 { 0xE571, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 92 /* DS35Q2GA-IB */ 93 { 0xE572, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 94 /* DS35M1GA-1B */ 95 { 0xE521, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 96 97 /* EM73C044VCC-H */ 98 { 0xD522, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 99 /* EM73D044VCE-H */ 100 { 0xD520, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 101 /* EM73E044SNA-G */ 102 { 0xD503, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 103 104 /* XT26G02A */ 105 { 0x0BE2, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 106 /* XT26G01A */ 107 { 0x0BE1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 108 /* XT26G04A */ 109 { 0x0BE3, 4, 0x80, 1, 2048, 0x4C, 20, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 110 /* XT26G01B */ 111 { 0x0BF1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 112 /* XT26G02B */ 113 { 0x0BF2, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 114 115 /* MT29F2G1ABA, XT26G02E, F50L2G41XA */ 116 { 0x2C24, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 117 118 /* FM25S01 */ 119 { 0xA1A1, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 120 /* FM25S01A */ 121 { 0xA1E4, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 122 /* FM25S02A */ 123 { 0xA1E5, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 124 125 /* IS37SML01G1 */ 126 { 0xC821, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 127 /* F50L1G41LB */ 128 { 0xC801, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 129 /* ATO25D1GA */ 130 { 0x9B12, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 131 }; 132 133 static struct nand_info *p_nand_info; 134 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 135 static struct SFNAND_DEV sfc_nand_dev; 136 137 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 138 { 139 u32 i; 140 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 141 142 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 143 if (spi_nand_tbl[i].id == id) 144 return &spi_nand_tbl[i]; 145 } 146 147 return NULL; 148 } 149 150 static int sfc_nand_write_en(void) 151 { 152 int ret; 153 struct rk_sfc_op op; 154 155 op.sfcmd.d32 = 0; 156 op.sfcmd.b.cmd = CMD_WRITE_EN; 157 158 op.sfctrl.d32 = 0; 159 160 ret = sfc_request(&op, 0, NULL, 0); 161 return ret; 162 } 163 164 static int sfc_nand_rw_preset(void) 165 { 166 int ret; 167 struct rk_sfc_op op; 168 169 op.sfcmd.d32 = 0; 170 op.sfcmd.b.cmd = 0xff; 171 op.sfcmd.b.cs = 2; 172 173 op.sfctrl.d32 = 0; 174 op.sfctrl.b.datalines = 2; 175 op.sfctrl.b.cmdlines = 2; 176 op.sfctrl.b.addrlines = 2; 177 178 ret = sfc_request(&op, 0, NULL, 0); 179 return ret; 180 } 181 182 static int sfc_nand_read_feature(u8 addr, u8 *data) 183 { 184 int ret; 185 struct rk_sfc_op op; 186 187 op.sfcmd.d32 = 0; 188 op.sfcmd.b.cmd = 0x0F; 189 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 190 191 op.sfctrl.d32 = 0; 192 op.sfctrl.b.addrbits = 8; 193 194 *data = 0; 195 196 ret = sfc_request(&op, addr, data, 1); 197 198 if (ret != SFC_OK) 199 return ret; 200 201 return SFC_OK; 202 } 203 204 static int sfc_nand_write_feature(u32 addr, u8 status) 205 { 206 int ret; 207 struct rk_sfc_op op; 208 209 sfc_nand_write_en(); 210 211 op.sfcmd.d32 = 0; 212 op.sfcmd.b.cmd = 0x1F; 213 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 214 op.sfcmd.b.rw = SFC_WRITE; 215 216 op.sfctrl.d32 = 0; 217 op.sfctrl.b.addrbits = 8; 218 219 ret = sfc_request(&op, addr, &status, 1); 220 221 if (ret != SFC_OK) 222 return ret; 223 224 return ret; 225 } 226 227 static int sfc_nand_wait_busy(u8 *data, int timeout) 228 { 229 int ret; 230 int i; 231 u8 status; 232 233 *data = 0; 234 235 for (i = 0; i < timeout; i++) { 236 ret = sfc_nand_read_feature(0xC0, &status); 237 238 if (ret != SFC_OK) 239 return ret; 240 241 *data = status; 242 243 if (!(status & (1 << 0))) 244 return SFC_OK; 245 246 sfc_delay(1); 247 } 248 249 return SFC_NAND_WAIT_TIME_OUT; 250 } 251 252 /* 253 * ecc default: 254 * ecc bits: 0xC0[4,5] 255 * 0b00, No bit errors were detected 256 * 0b01, Bit errors were detected and corrected. 257 * 0b10, Multiple bit errors were detected and not corrected. 258 * 0b11, Bits errors were detected and corrected, bit error count 259 * exceed the bit flip detection threshold 260 */ 261 static u32 sfc_nand_get_ecc_status0(void) 262 { 263 u32 ret; 264 u32 i; 265 u8 ecc; 266 u8 status; 267 u32 timeout = 1000 * 1000; 268 269 for (i = 0; i < timeout; i++) { 270 ret = sfc_nand_read_feature(0xC0, &status); 271 272 if (ret != SFC_OK) 273 return SFC_NAND_ECC_ERROR; 274 275 if (!(status & (1 << 0))) 276 break; 277 278 sfc_delay(1); 279 } 280 281 ecc = (status >> 4) & 0x03; 282 283 if (ecc <= 1) 284 ret = SFC_NAND_ECC_OK; 285 else if (ecc == 2) 286 ret = (u32)SFC_NAND_ECC_ERROR; 287 else 288 ret = SFC_NAND_ECC_REFRESH; 289 290 return ret; 291 } 292 293 /* 294 * ecc spectial type1: 295 * ecc bits: 0xC0[4,5] 296 * 0b00, No bit errors were detected; 297 * 0b01, Bits errors were detected and corrected, bit error count 298 * may reach the bit flip detection threshold; 299 * 0b10, Multiple bit errors were detected and not corrected; 300 * 0b11, Reserved. 301 */ 302 static u32 sfc_nand_get_ecc_status1(void) 303 { 304 u32 ret; 305 u32 i; 306 u8 ecc; 307 u8 status; 308 u32 timeout = 1000 * 1000; 309 310 for (i = 0; i < timeout; i++) { 311 ret = sfc_nand_read_feature(0xC0, &status); 312 313 if (ret != SFC_OK) 314 return SFC_NAND_ECC_ERROR; 315 316 if (!(status & (1 << 0))) 317 break; 318 319 sfc_delay(1); 320 } 321 322 ecc = (status >> 4) & 0x03; 323 324 if (ecc == 0) 325 ret = SFC_NAND_ECC_OK; 326 else if (ecc == 1) 327 ret = SFC_NAND_ECC_REFRESH; 328 else 329 ret = (u32)SFC_NAND_ECC_ERROR; 330 331 return ret; 332 } 333 334 /* 335 * ecc spectial type2: 336 * ecc bits: 0xC0[4,5] 0xF0[4,5] 337 * [0b0000, 0b0011], No bit errors were detected; 338 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 339 * reach Flipping Bits; 340 * [0b1000, 0b1011], Multiple bit errors were detected and 341 * not corrected. 342 * [0b1100, 0b1111], reserved. 343 */ 344 static u32 sfc_nand_get_ecc_status2(void) 345 { 346 u32 ret; 347 u32 i; 348 u8 ecc; 349 u8 status, status1; 350 u32 timeout = 1000 * 1000; 351 352 for (i = 0; i < timeout; i++) { 353 ret = sfc_nand_read_feature(0xC0, &status); 354 355 if (ret != SFC_OK) 356 return SFC_NAND_ECC_ERROR; 357 358 ret = sfc_nand_read_feature(0xF0, &status1); 359 360 if (ret != SFC_OK) 361 return SFC_NAND_ECC_ERROR; 362 363 if (!(status & (1 << 0))) 364 break; 365 366 sfc_delay(1); 367 } 368 369 ecc = (status >> 4) & 0x03; 370 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 371 372 if (ecc < 7) 373 ret = SFC_NAND_ECC_OK; 374 else if (ecc == 7) 375 ret = SFC_NAND_ECC_REFRESH; 376 else 377 ret = (u32)SFC_NAND_ECC_ERROR; 378 379 return ret; 380 } 381 382 /* 383 * ecc spectial type3: 384 * ecc bits: 0xC0[4,5] 0xF0[4,5] 385 * [0b0000, 0b0011], No bit errors were detected; 386 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 387 * reach Flipping Bits; 388 * [0b1000, 0b1011], Multiple bit errors were detected and 389 * not corrected. 390 * [0b1100, 0b1111], Bit error count equals the bit flip 391 * detectio nthreshold 392 */ 393 static u32 sfc_nand_get_ecc_status3(void) 394 { 395 u32 ret; 396 u32 i; 397 u8 ecc; 398 u8 status, status1; 399 u32 timeout = 1000 * 1000; 400 401 for (i = 0; i < timeout; i++) { 402 ret = sfc_nand_read_feature(0xC0, &status); 403 404 if (ret != SFC_OK) 405 return SFC_NAND_ECC_ERROR; 406 407 ret = sfc_nand_read_feature(0xF0, &status1); 408 409 if (ret != SFC_OK) 410 return SFC_NAND_ECC_ERROR; 411 412 if (!(status & (1 << 0))) 413 break; 414 415 sfc_delay(1); 416 } 417 418 ecc = (status >> 4) & 0x03; 419 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 420 421 if (ecc < 7) 422 ret = SFC_NAND_ECC_OK; 423 else if (ecc == 7 || ecc >= 12) 424 ret = SFC_NAND_ECC_REFRESH; 425 else 426 ret = (u32)SFC_NAND_ECC_ERROR; 427 428 return ret; 429 } 430 431 /* 432 * ecc spectial type4: 433 * ecc bits: 0xC0[2,5] 434 * [0b0000], No bit errors were detected; 435 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 436 * reach Flipping Bits; 437 * [0b1000], Multiple bit errors were detected and 438 * not corrected. 439 * [0b1100], Bit error count equals the bit flip 440 * detectionthreshold 441 * else, reserved 442 */ 443 static u32 sfc_nand_get_ecc_status4(void) 444 { 445 u32 ret; 446 u32 i; 447 u8 ecc; 448 u8 status; 449 u32 timeout = 1000 * 1000; 450 451 for (i = 0; i < timeout; i++) { 452 ret = sfc_nand_read_feature(0xC0, &status); 453 454 if (ret != SFC_OK) 455 return SFC_NAND_ECC_ERROR; 456 457 if (!(status & (1 << 0))) 458 break; 459 460 sfc_delay(1); 461 } 462 463 ecc = (status >> 2) & 0x0f; 464 465 if (ecc < 7) 466 ret = SFC_NAND_ECC_OK; 467 else if (ecc == 7 || ecc == 12) 468 ret = SFC_NAND_ECC_REFRESH; 469 else 470 ret = (u32)SFC_NAND_ECC_ERROR; 471 472 return ret; 473 } 474 475 /* 476 * ecc spectial type5: 477 * ecc bits: 0xC0[4,6] 478 * [0b000], No bit errors were detected; 479 * [0b001, 0b011], Bit errors were detected and corrected. Not 480 * reach Flipping Bits; 481 * [0b100], Bit error count equals the bit flip 482 * detectionthreshold 483 * [0b101, 0b110], Reserved; 484 * [0b111], Multiple bit errors were detected and 485 * not corrected. 486 */ 487 static u32 sfc_nand_get_ecc_status5(void) 488 { 489 u32 ret; 490 u32 i; 491 u8 ecc; 492 u8 status; 493 u32 timeout = 1000 * 1000; 494 495 for (i = 0; i < timeout; i++) { 496 ret = sfc_nand_read_feature(0xC0, &status); 497 498 if (ret != SFC_OK) 499 return SFC_NAND_ECC_ERROR; 500 501 if (!(status & (1 << 0))) 502 break; 503 504 sfc_delay(1); 505 } 506 507 ecc = (status >> 4) & 0x07; 508 509 if (ecc < 4) 510 ret = SFC_NAND_ECC_OK; 511 else if (ecc == 4) 512 ret = SFC_NAND_ECC_REFRESH; 513 else 514 ret = (u32)SFC_NAND_ECC_ERROR; 515 516 return ret; 517 } 518 519 /* 520 * ecc spectial type6: 521 * ecc bits: 0xC0[4,6] 522 * [0b000], No bit errors were detected; 523 * [0b001], 1-3 Bit errors were detected and corrected. Not 524 * reach Flipping Bits; 525 * [0b010], Multiple bit errors were detected and 526 * not corrected. 527 * [0b011], 4-6 Bit errors were detected and corrected. Not 528 * reach Flipping Bits; 529 * [0b101], Bit error count equals the bit flip 530 * detectionthreshold 531 * others, Reserved. 532 */ 533 static u32 sfc_nand_get_ecc_status6(void) 534 { 535 u32 ret; 536 u32 i; 537 u8 ecc; 538 u8 status; 539 u32 timeout = 1000 * 1000; 540 541 for (i = 0; i < timeout; i++) { 542 ret = sfc_nand_read_feature(0xC0, &status); 543 544 if (ret != SFC_OK) 545 return SFC_NAND_ECC_ERROR; 546 547 if (!(status & (1 << 0))) 548 break; 549 550 sfc_delay(1); 551 } 552 553 ecc = (status >> 4) & 0x07; 554 555 if (ecc == 0 || ecc == 1 || ecc == 3) 556 ret = SFC_NAND_ECC_OK; 557 else if (ecc == 5) 558 ret = SFC_NAND_ECC_REFRESH; 559 else 560 ret = (u32)SFC_NAND_ECC_ERROR; 561 562 return ret; 563 } 564 565 u32 sfc_nand_erase_block(u8 cs, u32 addr) 566 { 567 int ret; 568 struct rk_sfc_op op; 569 u8 status; 570 571 rkflash_print_dio("%s %x\n", __func__, addr); 572 op.sfcmd.d32 = 0; 573 op.sfcmd.b.cmd = 0xd8; 574 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 575 op.sfcmd.b.rw = SFC_WRITE; 576 577 op.sfctrl.d32 = 0; 578 579 sfc_nand_write_en(); 580 ret = sfc_request(&op, addr, NULL, 0); 581 582 if (ret != SFC_OK) 583 return ret; 584 585 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 586 587 if (status & (1 << 2)) 588 return SFC_NAND_PROG_ERASE_ERROR; 589 590 return ret; 591 } 592 593 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 594 { 595 int ret; 596 u32 plane; 597 struct rk_sfc_op op; 598 u8 status; 599 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 600 601 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 602 sfc_nand_write_en(); 603 604 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 605 p_nand_info->feature & FEA_SOFT_QOP_BIT && 606 sfc_get_version() < SFC_VER_3) 607 sfc_nand_rw_preset(); 608 609 op.sfcmd.d32 = 0; 610 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 611 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 612 op.sfcmd.b.rw = SFC_WRITE; 613 614 op.sfctrl.d32 = 0; 615 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 616 op.sfctrl.b.addrbits = 16; 617 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 618 sfc_request(&op, plane, p_page_buf, page_size); 619 620 op.sfcmd.d32 = 0; 621 op.sfcmd.b.cmd = 0x10; 622 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 623 op.sfcmd.b.rw = SFC_WRITE; 624 625 op.sfctrl.d32 = 0; 626 ret = sfc_request(&op, addr, p_page_buf, 0); 627 628 if (ret != SFC_OK) 629 return ret; 630 631 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 632 633 if (status & (1 << 3)) 634 return SFC_NAND_PROG_ERASE_ERROR; 635 636 return ret; 637 } 638 639 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 640 { 641 int ret; 642 u32 sec_per_page = p_nand_info->sec_per_page; 643 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 644 struct nand_mega_area *meta = &p_nand_info->meta; 645 646 memcpy(gp_page_buf, p_data, data_size); 647 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 648 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 649 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 650 651 if (sec_per_page == 8) { 652 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 653 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 654 } 655 656 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 657 658 return ret; 659 } 660 661 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 662 { 663 int ret; 664 u32 plane; 665 struct rk_sfc_op op; 666 u32 ecc_result; 667 u8 status; 668 669 op.sfcmd.d32 = 0; 670 op.sfcmd.b.cmd = 0x13; 671 op.sfcmd.b.rw = SFC_WRITE; 672 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 673 674 op.sfctrl.d32 = 0; 675 676 sfc_request(&op, row, p_page_buf, 0); 677 678 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 679 p_nand_info->feature & FEA_SOFT_QOP_BIT && 680 sfc_get_version() < SFC_VER_3) 681 sfc_nand_rw_preset(); 682 683 sfc_nand_wait_busy(&status, 1000 * 1000); 684 ecc_result = p_nand_info->ecc_status(); 685 686 op.sfcmd.d32 = 0; 687 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 688 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 689 op.sfcmd.b.dummybits = 8; 690 691 op.sfctrl.d32 = 0; 692 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 693 op.sfctrl.b.addrbits = 16; 694 695 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 696 ret = sfc_request(&op, plane | column, p_page_buf, len); 697 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 698 699 if (ret != SFC_OK) 700 return SFC_NAND_HW_ERROR; 701 702 return ecc_result; 703 } 704 705 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 706 { 707 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 708 709 return sfc_nand_read(addr, p_page_buf, 0, page_size); 710 } 711 712 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 713 { 714 u32 ret; 715 u32 sec_per_page = p_nand_info->sec_per_page; 716 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 717 struct nand_mega_area *meta = &p_nand_info->meta; 718 719 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 720 memcpy(p_data, gp_page_buf, data_size); 721 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 722 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 723 724 if (p_nand_info->sec_per_page == 8) { 725 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 726 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 727 } 728 729 if (ret == SFC_NAND_HW_ERROR) 730 ret = SFC_NAND_ECC_ERROR; 731 732 if (ret != SFC_NAND_ECC_OK) { 733 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 734 735 if (p_data) 736 rkflash_print_hex("data:", p_data, 4, 8); 737 738 if (p_spare) 739 rkflash_print_hex("spare:", p_spare, 4, 2); 740 } 741 742 return ret; 743 } 744 745 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 746 { 747 u32 ret; 748 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 749 u32 marker = 0; 750 751 ret = sfc_nand_read(addr, &marker, data_size, 2); 752 753 /* unify with mtd framework */ 754 if (ret == SFC_NAND_ECC_ERROR) 755 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 756 __func__, addr, ret, marker); 757 758 /* Original bad block */ 759 if ((u16)marker != 0xffff) 760 return true; 761 762 return false; 763 } 764 765 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 766 { 767 u32 ret; 768 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 769 770 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 771 772 if (ret) 773 return SFC_NAND_HW_ERROR; 774 775 gp_page_buf[data_size / 4] = 0x0; 776 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 777 778 if (ret) 779 return SFC_NAND_HW_ERROR; 780 781 return ret; 782 } 783 784 int sfc_nand_read_id(u8 *data) 785 { 786 int ret; 787 struct rk_sfc_op op; 788 789 op.sfcmd.d32 = 0; 790 op.sfcmd.b.cmd = CMD_READ_JEDECID; 791 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 792 793 op.sfctrl.d32 = 0; 794 op.sfctrl.b.addrbits = 8; 795 796 ret = sfc_request(&op, 0, data, 3); 797 798 return ret; 799 } 800 801 /* 802 * Read the 1st page's 1st byte of a phy_blk 803 * If not FF, it's bad blk 804 */ 805 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 806 { 807 u32 bad_cnt, page; 808 u32 blk_per_die; 809 u16 blk; 810 811 rkflash_print_info("%s\n", __func__); 812 813 bad_cnt = 0; 814 blk_per_die = p_nand_info->plane_per_die * 815 p_nand_info->blk_per_plane; 816 817 for (blk = 0; blk < blk_per_die; blk++) { 818 page = (blk + blk_per_die * die) * 819 p_nand_info->page_per_blk; 820 821 if (sfc_nand_check_bad_block(die, page)) { 822 table[bad_cnt++] = blk; 823 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 824 } 825 } 826 827 return (int)bad_cnt; 828 } 829 830 void sfc_nand_ftl_ops_init(void) 831 { 832 /* para init */ 833 g_nand_phy_info.nand_type = 1; 834 g_nand_phy_info.die_num = 1; 835 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 836 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 837 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 838 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 839 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 840 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 841 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 842 p_nand_info->page_per_blk; 843 g_nand_phy_info.reserved_blk = 8; 844 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 845 p_nand_info->blk_per_plane; 846 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 847 848 /* driver register */ 849 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 850 g_nand_ops.erase_blk = sfc_nand_erase_block; 851 g_nand_ops.prog_page = sfc_nand_prog_page; 852 g_nand_ops.read_page = sfc_nand_read_page; 853 g_nand_ops.bch_sel = NULL; 854 } 855 856 static int sfc_nand_enable_QE(void) 857 { 858 int ret = SFC_OK; 859 u8 status; 860 861 ret = sfc_nand_read_feature(0xB0, &status); 862 863 if (ret != SFC_OK) 864 return ret; 865 866 if (status & 1) /* is QE bit set */ 867 return SFC_OK; 868 869 status |= 1; 870 871 return sfc_nand_write_feature(0xB0, status); 872 } 873 874 u32 sfc_nand_init(void) 875 { 876 u8 status, id_byte[8]; 877 878 sfc_nand_read_id(id_byte); 879 rkflash_print_error("sfc_nand id: %x %x %x\n", 880 id_byte[0], id_byte[1], id_byte[2]); 881 882 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 883 return (u32)FTL_NO_FLASH; 884 885 p_nand_info = sfc_nand_get_info(id_byte); 886 887 if (!p_nand_info) 888 return (u32)FTL_UNSUPPORTED_FLASH; 889 890 sfc_nand_dev.manufacturer = id_byte[0]; 891 sfc_nand_dev.mem_type = id_byte[1]; 892 sfc_nand_dev.capacity = p_nand_info->density; 893 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 894 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 895 896 /* disable block lock */ 897 sfc_nand_write_feature(0xA0, 0); 898 sfc_nand_dev.read_lines = DATA_LINES_X1; 899 sfc_nand_dev.prog_lines = DATA_LINES_X1; 900 sfc_nand_dev.page_read_cmd = 0x03; 901 sfc_nand_dev.page_prog_cmd = 0x02; 902 903 if (p_nand_info->feature & FEA_4BIT_READ) { 904 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 905 !p_nand_info->has_qe_bits) { 906 sfc_nand_dev.read_lines = DATA_LINES_X4; 907 sfc_nand_dev.page_read_cmd = 0x6b; 908 } 909 } 910 911 if (p_nand_info->feature & FEA_4BIT_PROG && 912 sfc_nand_dev.read_lines == DATA_LINES_X4) { 913 sfc_nand_dev.prog_lines = DATA_LINES_X4; 914 sfc_nand_dev.page_prog_cmd = 0x32; 915 } 916 917 sfc_nand_read_feature(0xA0, &status); 918 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 919 sfc_nand_read_feature(0xB0, &status); 920 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 921 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 922 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 923 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 924 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 925 926 return SFC_OK; 927 } 928 929 void sfc_nand_deinit(void) 930 { 931 /* to-do */ 932 } 933 934 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 935 { 936 return &sfc_nand_dev; 937 } 938 939