1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static struct nand_info spi_nand_tbl[] = { 18 /* TC58CVG0S0HxAIx */ 19 {0x98C2, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 18, 8, 0xFF, 0xFF, 4, 8, NULL}, 20 /* TC58CVG1S0HxAIx */ 21 {0x98CB, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x02, 0xD8, 0x00, 19, 8, 0xFF, 0xFF, 4, 8, NULL}, 22 /* MX35LF1GE4AB */ 23 {0xC212, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 24 /* MX35LF2GE4AB */ 25 {0xC222, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 26 /* GD5F1GQ4UAYIG */ 27 {0xC8F1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, NULL}, 28 /* MT29F1G01ZAC */ 29 {0x2C12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp1}, 30 /* GD5F2GQ40BY2GR */ 31 {0xC8D2, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 32 /* GD5F1GQ4U */ 33 {0xC8D1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0, 4, 8, &sfc_nand_ecc_status_sp3}, 34 /* IS37SML01G1 */ 35 {0xC821, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x00, 18, 1, 0xFF, 0xFF, 8, 12, &sfc_nand_ecc_status_sp1}, 36 /* W25N01GV */ 37 {0xEFAA, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 4, 20, &sfc_nand_ecc_status_sp1}, 38 /* HYF2GQ4UAACAE */ 39 {0xC952, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 40 /* HYF2GQ4UDACAE */ 41 {0xC922, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 4, 0xB0, 0, 4, 20, NULL}, 42 /* HYF2GQ4UHCCAE */ 43 {0xC95A, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 14, 0xB0, 0, 4, 36, NULL}, 44 /* HYF1GQ4UDACAE */ 45 {0xC921, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 4, 0xB0, 0, 4, 20, NULL}, 46 /* F50L1G41LB */ 47 {0xC801, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xFF, 0xFF, 20, 36, &sfc_nand_ecc_status_sp1}, 48 /* XT26G02A */ 49 {0x0BE2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 50 /* XT26G01A */ 51 {0x0BE1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 52 /* FS35ND01G-S1 */ 53 {0xCDB1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 16, 20, &sfc_nand_ecc_status_sp5}, 54 /* FS35ND02G-S2 */ 55 {0xCDA2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x03, 0x02, 0xD8, 0x00, 19, 4, 0xFF, 0xFF, 16, 20, &sfc_nand_ecc_status_sp5}, 56 /* DS35Q1GA-1B */ 57 {0xE571, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 58 /* DS35Q2GA-1B */ 59 {0xE572, 4, 64, 2, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 4, 0xB0, 0x0, 4, 20, &sfc_nand_ecc_status_sp1}, 60 /* EM73C044SNC-G */ 61 {0xD522, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 18, 8, 0xB0, 0x0, 4, 20, NULL}, 62 /* EM73D044SNB-G */ 63 {0xD520, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x0C, 19, 8, 0xB0, 0x0, 4, 20, NULL}, 64 /* ATO25D1GA */ 65 {0x9B12, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x40, 18, 1, 0xB0, 0x0, 20, 36, &sfc_nand_ecc_status_sp1}, 66 /* XT26G02B */ 67 {0x0BF2, 4, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 19, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 68 /* XT26G01B */ 69 {0x0BF1, 4, 64, 1, 1024, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 18, 1, 0xB0, 0x0, 8, 12, &sfc_nand_ecc_status_sp4}, 70 /* HYF4GQ4UAACBE */ 71 {0xC9D4, 8, 64, 1, 2048, 0x13, 0x10, 0x03, 0x02, 0x6B, 0x32, 0xD8, 0x4C, 20, 4, 0xB0, 0, 32, 64, NULL}, 72 }; 73 74 static u8 id_byte[8]; 75 static struct nand_info *p_nand_info; 76 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 77 static struct SFNAND_DEV sfc_nand_dev; 78 79 static struct nand_info *spi_nand_get_info(u8 *nand_id) 80 { 81 u32 i; 82 u32 id = (nand_id[0] << 8) | (nand_id[1] << 0); 83 84 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 85 if (spi_nand_tbl[i].id == id) 86 return &spi_nand_tbl[i]; 87 } 88 return NULL; 89 } 90 91 static int sfc_nand_write_en(void) 92 { 93 int ret; 94 union SFCCMD_DATA sfcmd; 95 96 sfcmd.d32 = 0; 97 sfcmd.b.cmd = CMD_WRITE_EN; 98 ret = sfc_request(sfcmd.d32, 0, 0, NULL); 99 return ret; 100 } 101 102 static int sfc_nand_rw_preset(void) 103 { 104 int ret; 105 union SFCCTRL_DATA sfctrl; 106 union SFCCMD_DATA sfcmd; 107 u8 status = 0xFF; 108 109 sfcmd.d32 = 0; 110 sfcmd.b.cmd = 0; 111 sfcmd.b.datasize = 1; 112 sfcmd.b.rw = SFC_WRITE; 113 114 sfctrl.b.datalines = 2; 115 ret = sfc_request(sfcmd.d32, sfctrl.d32, 0, &status); 116 return ret; 117 } 118 119 static int sfc_nand_read_feature(u8 addr, u8 *data) 120 { 121 int ret; 122 union SFCCMD_DATA sfcmd; 123 124 sfcmd.d32 = 0; 125 sfcmd.b.cmd = 0x0F; 126 sfcmd.b.datasize = 1; 127 sfcmd.b.addrbits = SFC_ADDR_XBITS; 128 *data = 0; 129 130 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, data); 131 if (ret != SFC_OK) 132 return ret; 133 return SFC_OK; 134 } 135 136 static int sfc_nand_write_feature(u32 addr, u8 status) 137 { 138 int ret; 139 union SFCCMD_DATA sfcmd; 140 141 sfc_nand_write_en(); 142 143 sfcmd.d32 = 0; 144 sfcmd.b.cmd = 0x1F; 145 sfcmd.b.datasize = 1; 146 sfcmd.b.addrbits = SFC_ADDR_XBITS; 147 sfcmd.b.rw = SFC_WRITE; 148 149 ret = sfc_request(sfcmd.d32, 0x8 << 16, addr, &status); 150 if (ret != SFC_OK) 151 return ret; 152 return ret; 153 } 154 155 static int sfc_nand_wait_busy(u8 *data, int timeout) 156 { 157 int ret; 158 int i; 159 u8 status; 160 161 *data = 0; 162 for (i = 0; i < timeout; i++) { 163 ret = sfc_nand_read_feature(0xC0, &status); 164 if (ret != SFC_OK) 165 return ret; 166 *data = status; 167 if (!(status & (1 << 0))) 168 return SFC_OK; 169 sfc_delay(1); 170 } 171 return -1; 172 } 173 174 /* 175 * ecc default: 176 * 0, No bit errors were detected 177 * 1, Bit errors were detected and corrected. 178 * 2, Multiple bit errors were detected and not corrected. 179 * 3, Bits errors were detected and corrected, bit error count 180 * exceed the bit flip detection threshold 181 */ 182 static u32 sfc_nand_ecc_status(void) 183 { 184 int ret; 185 u32 i; 186 u8 ecc; 187 u8 status; 188 u32 timeout = 1000 * 1000; 189 190 for (i = 0; i < timeout; i++) { 191 ret = sfc_nand_read_feature(0xC0, &status); 192 if (ret != SFC_OK) 193 return SFC_NAND_ECC_ERROR; 194 if (!(status & (1 << 0))) 195 break; 196 sfc_delay(1); 197 } 198 199 ecc = (status >> 4) & 0x03; 200 201 if (ecc <= 1) 202 ret = SFC_NAND_ECC_OK; 203 else if (ecc == 2) 204 ret = SFC_NAND_ECC_ERROR; 205 else 206 ret = SFC_NAND_ECC_REFRESH; 207 208 return ret; 209 } 210 211 /* 212 * ecc spectial type1: 213 * 0x00, No bit errors were detected; 214 * 0x01, Bits errors were detected and corrected, bit error count 215 * may reach the bit flip detection threshold; 216 * 0x10, Multiple bit errors were detected and not corrected; 217 * 0x11, Reserved. 218 */ 219 u32 sfc_nand_ecc_status_sp1(void) 220 { 221 int ret; 222 u32 i; 223 u8 ecc; 224 u8 status; 225 u32 timeout = 1000 * 1000; 226 227 for (i = 0; i < timeout; i++) { 228 ret = sfc_nand_read_feature(0xC0, &status); 229 if (ret != SFC_OK) 230 return SFC_NAND_ECC_ERROR; 231 if (!(status & (1 << 0))) 232 break; 233 sfc_delay(1); 234 } 235 236 ecc = (status >> 4) & 0x03; 237 238 if (ecc == 0) 239 ret = SFC_NAND_ECC_OK; 240 else if (ecc == 1) 241 ret = SFC_NAND_ECC_REFRESH; 242 else 243 ret = SFC_NAND_ECC_ERROR; 244 245 return ret; 246 } 247 248 /* 249 * ecc spectial type3: 250 * [0x0000, 0x0011], No bit errors were detected; 251 * [0x0100, 0x0111], Bit errors were detected and corrected. Not 252 * reach Flipping Bits; 253 * [0x1000, 0x1011], Multiple bit errors were detected and 254 * not corrected. 255 * [0x1100, 0x1111], Bit error count equals the bit flip 256 * detectionthreshold 257 */ 258 u32 sfc_nand_ecc_status_sp3(void) 259 { 260 int ret; 261 u32 i; 262 u8 ecc; 263 u8 status, status1; 264 u32 timeout = 1000 * 1000; 265 266 for (i = 0; i < timeout; i++) { 267 ret = sfc_nand_read_feature(0xC0, &status); 268 if (ret != SFC_OK) 269 return SFC_NAND_ECC_ERROR; 270 ret = sfc_nand_read_feature(0xF0, &status1); 271 if (ret != SFC_OK) 272 return SFC_NAND_ECC_ERROR; 273 if (!(status & (1 << 0))) 274 break; 275 sfc_delay(1); 276 } 277 278 ecc = (status >> 4) & 0x03; 279 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 280 if (ecc < 7) 281 ret = SFC_NAND_ECC_OK; 282 else if (ecc == 7 || ecc >= 12) 283 ret = SFC_NAND_ECC_REFRESH; 284 else 285 ret = SFC_NAND_ECC_ERROR; 286 287 return ret; 288 } 289 290 /* 291 * ecc spectial type4: 292 * [0x0000], No bit errors were detected; 293 * [0x0001, 0x0111], Bit errors were detected and corrected. Not 294 * reach Flipping Bits; 295 * [0x1000], Multiple bit errors were detected and 296 * not corrected. 297 * [0x1100], Bit error count equals the bit flip 298 * detectionthreshold 299 * else, reserved 300 */ 301 u32 sfc_nand_ecc_status_sp4(void) 302 { 303 int ret; 304 u32 i; 305 u8 ecc; 306 u8 status; 307 u32 timeout = 1000 * 1000; 308 309 for (i = 0; i < timeout; i++) { 310 ret = sfc_nand_read_feature(0xC0, &status); 311 if (ret != SFC_OK) 312 return SFC_NAND_ECC_ERROR; 313 if (!(status & (1 << 0))) 314 break; 315 sfc_delay(1); 316 } 317 318 ecc = (status >> 2) & 0x0f; 319 if (ecc < 7) 320 ret = SFC_NAND_ECC_OK; 321 else if (ecc == 7 || ecc == 12) 322 ret = SFC_NAND_ECC_REFRESH; 323 else 324 ret = SFC_NAND_ECC_ERROR; 325 326 return ret; 327 } 328 329 /* 330 * ecc spectial type5: 331 * [0x0], No bit errors were detected; 332 * [0x001, 0x011], Bit errors were detected and corrected. Not 333 * reach Flipping Bits; 334 * [0x100], Bit error count equals the bit flip 335 * detectionthreshold 336 * [0x101, 0x110], Reserved; 337 * [0x111], Multiple bit errors were detected and 338 * not corrected. 339 */ 340 u32 sfc_nand_ecc_status_sp5(void) 341 { 342 int ret; 343 u32 i; 344 u8 ecc; 345 u8 status; 346 u32 timeout = 1000 * 1000; 347 348 for (i = 0; i < timeout; i++) { 349 ret = sfc_nand_read_feature(0xC0, &status); 350 if (ret != SFC_OK) 351 return SFC_NAND_ECC_ERROR; 352 if (!(status & (1 << 0))) 353 break; 354 sfc_delay(1); 355 } 356 357 ecc = (status >> 4) & 0x07; 358 if (ecc < 4) 359 ret = SFC_NAND_ECC_OK; 360 else if (ecc == 4) 361 ret = SFC_NAND_ECC_REFRESH; 362 else 363 ret = SFC_NAND_ECC_ERROR; 364 365 return ret; 366 } 367 368 static u32 sfc_nand_erase_block(u8 cs, u32 addr) 369 { 370 int ret; 371 union SFCCMD_DATA sfcmd; 372 u8 status; 373 374 sfcmd.d32 = 0; 375 sfcmd.b.cmd = p_nand_info->block_erase_cmd; 376 sfcmd.b.addrbits = SFC_ADDR_24BITS; 377 sfc_nand_write_en(); 378 ret = sfc_request(sfcmd.d32, 0, addr, NULL); 379 if (ret != SFC_OK) 380 return ret; 381 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 382 if (status & (1 << 2)) 383 return SFC_NAND_PROG_ERASE_ERROR; 384 return ret; 385 } 386 387 static u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 388 { 389 int ret; 390 u32 plane; 391 union SFCCMD_DATA sfcmd; 392 union SFCCTRL_DATA sfctrl; 393 u8 status; 394 u32 sec_per_page = p_nand_info->sec_per_page; 395 u32 spare_offs_1 = p_nand_info->spare_offs_1; 396 u32 spare_offs_2 = p_nand_info->spare_offs_2; 397 u32 data_size = sec_per_page * 512; 398 399 PRINT_SFC_I("%s %x %x %x\n", __func__, addr, p_data[0], p_spare[0]); 400 memcpy(gp_page_buf, p_data, data_size); 401 ftl_memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 402 gp_page_buf[(data_size + spare_offs_1) / 4] = p_spare[0]; 403 gp_page_buf[(data_size + spare_offs_2) / 4] = p_spare[1]; 404 if (sec_per_page == 8) { 405 gp_page_buf[(data_size + spare_offs_1) / 4 + 1] = p_spare[2]; 406 gp_page_buf[(data_size + spare_offs_2) / 4 + 1] = p_spare[3]; 407 } 408 sfc_nand_write_en(); 409 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 410 p_nand_info->feature & FEA_SOFT_QOP_BIT && 411 sfc_get_version() < SFC_VER_3) 412 sfc_nand_rw_preset(); 413 414 sfcmd.d32 = 0; 415 sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 416 sfcmd.b.addrbits = SFC_ADDR_XBITS; 417 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 418 sfcmd.b.rw = SFC_WRITE; 419 420 sfctrl.d32 = 0; 421 sfctrl.b.datalines = sfc_nand_dev.prog_lines; 422 sfctrl.b.addrbits = 16; 423 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 424 sfc_request(sfcmd.d32, sfctrl.d32, plane, gp_page_buf); 425 426 sfcmd.d32 = 0; 427 sfcmd.b.cmd = p_nand_info->page_prog_cmd; 428 sfcmd.b.addrbits = SFC_ADDR_24BITS; 429 sfcmd.b.datasize = 0; 430 sfcmd.b.rw = SFC_WRITE; 431 ret = sfc_request(sfcmd.d32, 0, addr, p_data); 432 if (ret != SFC_OK) 433 return ret; 434 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 435 if (status & (1 << 3)) 436 return SFC_NAND_PROG_ERASE_ERROR; 437 return ret; 438 } 439 440 static u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 441 { 442 int ret; 443 u32 plane; 444 union SFCCMD_DATA sfcmd; 445 union SFCCTRL_DATA sfctrl; 446 u32 ecc_result; 447 u32 spare_offs_1 = p_nand_info->spare_offs_1; 448 u32 spare_offs_2 = p_nand_info->spare_offs_2; 449 u32 sec_per_page = p_nand_info->sec_per_page; 450 u32 data_size = sec_per_page * 512; 451 452 PRINT_SFC_I("%s %x %x %x\n", __func__, addr, p_data[0], p_spare[0]); 453 sfcmd.d32 = 0; 454 sfcmd.b.cmd = p_nand_info->page_read_cmd; 455 sfcmd.b.datasize = 0; 456 sfcmd.b.addrbits = SFC_ADDR_24BITS; 457 sfc_request(sfcmd.d32, 0, addr, p_data); 458 459 if (p_nand_info->ecc_status) 460 ecc_result = p_nand_info->ecc_status(); 461 else 462 ecc_result = sfc_nand_ecc_status(); 463 464 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 465 p_nand_info->feature & FEA_SOFT_QOP_BIT && 466 sfc_get_version() < SFC_VER_3) 467 sfc_nand_rw_preset(); 468 469 sfcmd.d32 = 0; 470 sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 471 sfcmd.b.datasize = SFC_NAND_SECTOR_FULL_SIZE * sec_per_page; 472 sfcmd.b.addrbits = SFC_ADDR_24BITS; 473 sfctrl.d32 = 0; 474 sfctrl.b.datalines = sfc_nand_dev.read_lines; 475 476 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 477 ret = sfc_request(sfcmd.d32, sfctrl.d32, plane << 8, gp_page_buf); 478 memcpy(p_data, gp_page_buf, data_size); 479 p_spare[0] = gp_page_buf[(data_size + spare_offs_1) / 4]; 480 p_spare[1] = gp_page_buf[(data_size + spare_offs_2) / 4]; 481 if (p_nand_info->sec_per_page == 8) { 482 p_spare[2] = gp_page_buf[(data_size + spare_offs_1) / 4 + 1]; 483 p_spare[3] = gp_page_buf[(data_size + spare_offs_2) / 4 + 1]; 484 } 485 if (ret != SFC_OK) 486 return SFC_NAND_ECC_ERROR; 487 488 if (ecc_result != SFC_NAND_ECC_OK) { 489 PRINT_SFC_E("%s[0x%x], ret=0x%x\n", __func__, addr, ecc_result); 490 if (p_data) 491 PRINT_SFC_HEX("data:", p_data, 4, 8); 492 if (p_spare) 493 PRINT_SFC_HEX("spare:", p_spare, 4, 2); 494 } 495 496 return ecc_result; 497 } 498 499 static int sfc_nand_read_id_raw(u8 *data) 500 { 501 int ret; 502 union SFCCMD_DATA sfcmd; 503 504 sfcmd.d32 = 0; 505 sfcmd.b.cmd = CMD_READ_JEDECID; 506 sfcmd.b.datasize = 3; 507 sfcmd.b.addrbits = SFC_ADDR_XBITS; 508 509 ret = sfc_request(sfcmd.d32, 0x8 << 16, 0, data); 510 511 return ret; 512 } 513 514 /* 515 * Read the 1st page's 1st byte of a phy_blk 516 * If not FF, it's bad blk 517 */ 518 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 519 { 520 u16 blk; 521 u32 bad_cnt, page; 522 u32 blk_per_die; 523 u32 *pread; 524 u32 *pspare_read; 525 526 PRINT_SFC_E("%s\n", __func__); 527 pread = ftl_malloc(2048); 528 pspare_read = ftl_malloc(8); 529 bad_cnt = 0; 530 blk_per_die = p_nand_info->plane_per_die * 531 p_nand_info->blk_per_plane; 532 for (blk = 0; blk < blk_per_die; blk++) { 533 page = (blk + blk_per_die * die) * 534 p_nand_info->page_per_blk; 535 sfc_nand_read_page(0, page, pread, pspare_read); 536 537 if (pread[0] != 0xFFFFFFFF || 538 pspare_read[0] != 0xFFFFFFFF) { 539 table[bad_cnt++] = blk; 540 PRINT_SFC_E("die[%d], bad_blk[%d]\n", die, blk); 541 } 542 } 543 ftl_free(pread); 544 ftl_free(pspare_read); 545 return (int)bad_cnt; 546 } 547 548 #if SFC_NAND_STRESS_TEST_EN 549 550 #define SFC_NAND_PAGE_SIZE 2048 551 #define SFC_NAND_SPARE_SIZE 8 552 553 static u16 bad_blk_list[1024]; 554 static u32 pwrite[SFC_NAND_PAGE_SIZE / 4]; 555 static u32 pread[SFC_NAND_PAGE_SIZE / 4]; 556 static u32 pspare_write[SFC_NAND_SPARE_SIZE / 4]; 557 static u32 pspare_read[SFC_NAND_SPARE_SIZE / 4]; 558 static u32 bad_blk_num; 559 static u32 bad_page_num; 560 561 static void sfc_nand_test(void) 562 { 563 u32 i, blk, page, bad_cnt, page_addr; 564 int ret; 565 u32 pages_num = 64; 566 u32 blk_addr = 64; 567 u32 is_bad_blk = 0; 568 569 PRINT_SFC_E("%s\n", __func__); 570 571 bad_blk_num = 0; 572 bad_page_num = 0; 573 bad_cnt = sfc_nand_get_bad_block_list(bad_blk_list, 0); 574 575 for (blk = 0; blk < 1024; blk++) { 576 for (i = 0; i < bad_cnt; i++) { 577 if (bad_blk_list[i] == blk) 578 break; 579 } 580 if (i < bad_cnt) 581 continue; 582 is_bad_blk = 0; 583 PRINT_SFC_E("Flash prog block: %x\n", blk); 584 sfc_nand_erase_block(0, blk * blk_addr); 585 for (page = 0; page < pages_num; page++) { 586 page_addr = blk * blk_addr + page; 587 for (i = 0; i < 512; i++) 588 pwrite[i] = (page_addr << 16) + i; 589 pspare_write[0] = pwrite[0] + 0x5AF0; 590 pspare_write[1] = pspare_write[0] + 1; 591 sfc_nand_prog_page(0, page_addr, pwrite, pspare_write); 592 memset(pread, 0, 2048); 593 memset(pspare_read, 0, 8); 594 ret = sfc_nand_read_page(0, page_addr, pread, 595 pspare_read); 596 if (ret != SFC_NAND_ECC_OK) 597 is_bad_blk = 1; 598 for (i = 0; i < 512; i++) { 599 if (pwrite[i] != pread[i]) { 600 is_bad_blk = 1; 601 break; 602 } 603 } 604 for (i = 0; i < 2; i++) { 605 if (pspare_write[i] != pspare_read[i]) { 606 is_bad_blk = 1; 607 break; 608 } 609 } 610 if (is_bad_blk) { 611 bad_page_num++; 612 PRINT_SFC_E("ERR:page%x, ret=%x\n", 613 page_addr, ret); 614 PRINT_SFC_HEX("data:", pread, 4, 8); 615 PRINT_SFC_HEX("spare:", pspare_read, 4, 2); 616 } 617 } 618 sfc_nand_erase_block(0, blk * blk_addr); 619 if (is_bad_blk) 620 bad_blk_num++; 621 } 622 PRINT_SFC_E("bad_blk_num = %d, bad_page_num = %d\n", 623 bad_blk_num, bad_page_num); 624 625 PRINT_SFC_E("Flash Test Finish!!!\n"); 626 while (1) 627 ; 628 } 629 #endif 630 631 static void ftl_flash_init(void) 632 { 633 /* para init */ 634 g_nand_phy_info.nand_type = 1; 635 g_nand_phy_info.die_num = 1; 636 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 637 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 638 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 639 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 640 g_nand_phy_info.byte_per_sec = 512; 641 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 642 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 643 p_nand_info->page_per_blk; 644 g_nand_phy_info.reserved_blk = 8; 645 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 646 p_nand_info->blk_per_plane; 647 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 648 649 /* driver register */ 650 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 651 g_nand_ops.erase_blk = sfc_nand_erase_block; 652 g_nand_ops.prog_page = sfc_nand_prog_page; 653 g_nand_ops.read_page = sfc_nand_read_page; 654 g_nand_ops.bch_sel = NULL; 655 } 656 657 static int spi_nand_enable_QE(void) 658 { 659 int ret = SFC_OK; 660 u8 status; 661 int bit_offset = p_nand_info->QE_bits; 662 663 if (bit_offset == 0xFF) 664 return SFC_OK; 665 666 ret = sfc_nand_read_feature(p_nand_info->QE_address, &status); 667 if (ret != SFC_OK) 668 return ret; 669 670 if (status & (1 << bit_offset)) /* is QE bit set */ 671 return SFC_OK; 672 673 status |= (1 << bit_offset); 674 return sfc_nand_write_feature(p_nand_info->QE_address, status); 675 676 return ret; 677 } 678 679 u32 sfc_nand_init(void) 680 { 681 PRINT_SFC_I("...%s enter...\n", __func__); 682 683 sfc_nand_read_id_raw(id_byte); 684 PRINT_SFC_E("sfc_nand id: %x %x %x\n", 685 id_byte[0], id_byte[1], id_byte[2]); 686 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 687 return FTL_NO_FLASH; 688 689 p_nand_info = spi_nand_get_info(id_byte); 690 if (!p_nand_info) 691 return FTL_UNSUPPORTED_FLASH; 692 693 sfc_nand_dev.manufacturer = id_byte[0]; 694 sfc_nand_dev.mem_type = id_byte[1]; 695 696 /* disable block lock */ 697 sfc_nand_write_feature(0xA0, 0); 698 sfc_nand_dev.read_lines = DATA_LINES_X1; 699 sfc_nand_dev.prog_lines = DATA_LINES_X1; 700 sfc_nand_dev.page_read_cmd = p_nand_info->read_cache_cmd_1; 701 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_1; 702 if (p_nand_info->feature & FEA_4BIT_READ) { 703 if (spi_nand_enable_QE() == SFC_OK) { 704 sfc_nand_dev.read_lines = DATA_LINES_X4; 705 sfc_nand_dev.page_read_cmd = 706 p_nand_info->read_cache_cmd_4; 707 } 708 } 709 710 if (p_nand_info->feature & FEA_4BIT_PROG && 711 sfc_nand_dev.read_lines == DATA_LINES_X4) { 712 sfc_nand_dev.prog_lines = DATA_LINES_X4; 713 sfc_nand_dev.page_prog_cmd = p_nand_info->prog_cache_cmd_4; 714 } 715 716 if (1) { 717 u8 status; 718 719 sfc_nand_read_feature(0xA0, &status); 720 PRINT_SFC_I("sfc_nand A0 = 0x%x\n", status); 721 sfc_nand_read_feature(0xB0, &status); 722 PRINT_SFC_I("sfc_nand B0 = 0x%x\n", status); 723 sfc_nand_read_feature(0xC0, &status); 724 PRINT_SFC_I("sfc_nand C0 = 0x%x\n", status); 725 PRINT_SFC_I("read_lines = %x\n", sfc_nand_dev.read_lines); 726 PRINT_SFC_I("prog_lines = %x\n", sfc_nand_dev.prog_lines); 727 PRINT_SFC_I("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 728 PRINT_SFC_I("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 729 } 730 ftl_flash_init(); 731 732 #if SFC_NAND_STRESS_TEST_EN 733 sfc_nand_test(); 734 #endif 735 736 return SFC_OK; 737 } 738 739 int sfc_nand_read_id(u8 *data) 740 { 741 memcpy(data, id_byte, 3); 742 return 0; 743 } 744