1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 static u32 sfc_nand_get_ecc_status7(void); 25 static u32 sfc_nand_get_ecc_status8(void); 26 27 static struct nand_info spi_nand_tbl[] = { 28 /* TC58CVG0S0HxAIx */ 29 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 30 /* TC58CVG1S0HxAIx */ 31 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 32 /* TC58CVG2S0HRAIJ */ 33 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 34 /* TC58CVG1S3HRAIJ */ 35 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 36 /* TC58CVG0S3HRAIJ */ 37 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 38 39 /* MX35LF1GE4AB */ 40 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 41 /* MX35LF2GE4AB */ 42 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 43 /* MX35LF2GE4AD */ 44 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 45 /* MX35LF4GE4AD */ 46 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 47 /* MX35UF1GE4AC */ 48 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 49 /* MX35UF2GE4AC */ 50 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 51 52 /* GD5F1GQ4UAYIG */ 53 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 54 /* GD5F1GQ4RB9IGR */ 55 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 56 /* GD5F2GQ40BY2GR */ 57 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 58 /* GD5F1GQ5UEYIG */ 59 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 60 /* GD5F2GQ5UEYIG */ 61 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 62 /* GD5F1GQ4R */ 63 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 64 /* GD5F4GQ6RExxG 1*4096 */ 65 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 66 /* GD5F4GQ6UExxG 1*4096 */ 67 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0X14, 0x18 }, &sfc_nand_get_ecc_status2 }, 68 /* GD5F1GQ4UExxH */ 69 { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 70 /* GD5F1GQ5REYIG */ 71 { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 72 /* GD5F2GQ5REYIG */ 73 { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 74 /* GD5F2GM7RxG */ 75 { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 76 /* GD5F2GM7UxG */ 77 { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 78 79 /* W25N01GV */ 80 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 81 /* W25N02KVZEIR */ 82 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 83 /* W25N04KVZEIR */ 84 { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 }, 85 /* W25N01GW */ 86 { 0xEF, 0xBA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 87 /* W25N512GVEIG */ 88 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 89 90 /* HYF2GQ4UAACAE */ 91 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 92 /* HYF1GQ4UDACAE */ 93 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 94 /* HYF1GQ4UPACAE */ 95 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 96 /* HYF2GQ4UDACAE */ 97 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 98 /* HYF2GQ4UHCCAE */ 99 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 100 /* HYF4GQ4UAACBE */ 101 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 102 103 /* FS35ND01G-S1 */ 104 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 105 /* FS35ND02G-S2 */ 106 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 107 /* FS35ND01G-S1Y2 */ 108 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 109 /* FS35ND02G-S3Y2 */ 110 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 111 /* FS35ND04G-S2Y2 1*4096 */ 112 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 113 /* F35SQA001G */ 114 { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 115 116 /* DS35Q1GA-IB */ 117 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 118 /* DS35Q2GA-IB */ 119 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 120 /* DS35M1GA-1B */ 121 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 122 /* DS35M2GA-IB */ 123 { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 124 /* DS35Q2GB-IB */ 125 { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 126 /* DS35M1GB-IB */ 127 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 128 129 /* EM73C044VCC-H */ 130 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 131 /* EM73D044VCE-H */ 132 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 133 /* EM73E044SNA-G */ 134 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 135 /* EM73C044VCF-H */ 136 { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 137 138 /* XT26G02A */ 139 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 140 /* XT26G01A */ 141 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 142 /* XT26G04A */ 143 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 144 /* XT26G01B */ 145 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 146 /* XT26G02B */ 147 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 148 /* XT26G01C */ 149 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 150 /* XT26G02C */ 151 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 152 /* XT26G04C */ 153 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, 154 /* XT26G11C */ 155 { 0x0B, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 156 157 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ 158 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 159 /* MT29F1G01ABA, F50L1G41XA */ 160 { 0x2C, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 161 162 /* FM25S01 */ 163 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 164 /* FM25S01A */ 165 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 166 /* FM25S02A */ 167 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 168 169 /* IS37SML01G1 */ 170 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 171 /* F50L1G41LB */ 172 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 173 /* ATO25D1GA */ 174 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 175 /* BWJX08K-2Gb */ 176 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 177 /* JS28U1GQSCAHG-83 */ 178 { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 179 /* SGM7000I-S24W1GH */ 180 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 181 /* TX25G01 */ 182 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 183 }; 184 185 static struct nand_info *p_nand_info; 186 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 187 static struct SFNAND_DEV sfc_nand_dev; 188 189 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 190 { 191 u32 i; 192 193 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 194 if (spi_nand_tbl[i].id0 == nand_id[0] && 195 spi_nand_tbl[i].id1 == nand_id[1]) { 196 if (spi_nand_tbl[i].id2 && 197 spi_nand_tbl[i].id2 != nand_id[2]) 198 continue; 199 200 return &spi_nand_tbl[i]; 201 } 202 } 203 204 return NULL; 205 } 206 207 static int sfc_nand_write_en(void) 208 { 209 int ret; 210 struct rk_sfc_op op; 211 212 op.sfcmd.d32 = 0; 213 op.sfcmd.b.cmd = CMD_WRITE_EN; 214 215 op.sfctrl.d32 = 0; 216 217 ret = sfc_request(&op, 0, NULL, 0); 218 return ret; 219 } 220 221 static int sfc_nand_rw_preset(void) 222 { 223 int ret; 224 struct rk_sfc_op op; 225 226 op.sfcmd.d32 = 0; 227 op.sfcmd.b.cmd = 0xff; 228 op.sfcmd.b.cs = 2; 229 230 op.sfctrl.d32 = 0; 231 op.sfctrl.b.datalines = 2; 232 op.sfctrl.b.cmdlines = 2; 233 op.sfctrl.b.addrlines = 2; 234 235 ret = sfc_request(&op, 0, NULL, 0); 236 return ret; 237 } 238 239 static int sfc_nand_read_feature(u8 addr, u8 *data) 240 { 241 int ret; 242 struct rk_sfc_op op; 243 244 op.sfcmd.d32 = 0; 245 op.sfcmd.b.cmd = 0x0F; 246 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 247 248 op.sfctrl.d32 = 0; 249 op.sfctrl.b.addrbits = 8; 250 251 *data = 0; 252 253 ret = sfc_request(&op, addr, data, 1); 254 255 if (ret != SFC_OK) 256 return ret; 257 258 return SFC_OK; 259 } 260 261 static int sfc_nand_write_feature(u32 addr, u8 status) 262 { 263 int ret; 264 struct rk_sfc_op op; 265 266 sfc_nand_write_en(); 267 268 op.sfcmd.d32 = 0; 269 op.sfcmd.b.cmd = 0x1F; 270 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 271 op.sfcmd.b.rw = SFC_WRITE; 272 273 op.sfctrl.d32 = 0; 274 op.sfctrl.b.addrbits = 8; 275 276 ret = sfc_request(&op, addr, &status, 1); 277 278 if (ret != SFC_OK) 279 return ret; 280 281 return ret; 282 } 283 284 static int sfc_nand_wait_busy(u8 *data, int timeout) 285 { 286 int ret; 287 int i; 288 u8 status; 289 290 *data = 0; 291 292 for (i = 0; i < timeout; i++) { 293 ret = sfc_nand_read_feature(0xC0, &status); 294 295 if (ret != SFC_OK) 296 return ret; 297 298 *data = status; 299 300 if (!(status & (1 << 0))) 301 return SFC_OK; 302 303 sfc_delay(1); 304 } 305 306 return SFC_NAND_WAIT_TIME_OUT; 307 } 308 309 /* 310 * ecc default: 311 * ecc bits: 0xC0[4,5] 312 * 0b00, No bit errors were detected 313 * 0b01, Bit errors were detected and corrected. 314 * 0b10, Multiple bit errors were detected and not corrected. 315 * 0b11, Bits errors were detected and corrected, bit error count 316 * reach the bit flip detection threshold 317 */ 318 static u32 sfc_nand_get_ecc_status0(void) 319 { 320 u32 ret; 321 u32 i; 322 u8 ecc; 323 u8 status; 324 u32 timeout = 1000 * 1000; 325 326 for (i = 0; i < timeout; i++) { 327 ret = sfc_nand_read_feature(0xC0, &status); 328 329 if (ret != SFC_OK) 330 return SFC_NAND_ECC_ERROR; 331 332 if (!(status & (1 << 0))) 333 break; 334 335 sfc_delay(1); 336 } 337 338 ecc = (status >> 4) & 0x03; 339 340 if (ecc <= 1) 341 ret = SFC_NAND_ECC_OK; 342 else if (ecc == 2) 343 ret = (u32)SFC_NAND_ECC_ERROR; 344 else 345 ret = SFC_NAND_ECC_REFRESH; 346 347 return ret; 348 } 349 350 /* 351 * ecc spectial type1: 352 * ecc bits: 0xC0[4,5] 353 * 0b00, No bit errors were detected; 354 * 0b01, Bits errors were detected and corrected, bit error count 355 * may reach the bit flip detection threshold; 356 * 0b10, Multiple bit errors were detected and not corrected; 357 * 0b11, Reserved. 358 */ 359 static u32 sfc_nand_get_ecc_status1(void) 360 { 361 u32 ret; 362 u32 i; 363 u8 ecc; 364 u8 status; 365 u32 timeout = 1000 * 1000; 366 367 for (i = 0; i < timeout; i++) { 368 ret = sfc_nand_read_feature(0xC0, &status); 369 370 if (ret != SFC_OK) 371 return SFC_NAND_ECC_ERROR; 372 373 if (!(status & (1 << 0))) 374 break; 375 376 sfc_delay(1); 377 } 378 379 ecc = (status >> 4) & 0x03; 380 381 if (ecc == 0) 382 ret = SFC_NAND_ECC_OK; 383 else if (ecc == 1) 384 ret = SFC_NAND_ECC_REFRESH; 385 else 386 ret = (u32)SFC_NAND_ECC_ERROR; 387 388 return ret; 389 } 390 391 /* 392 * ecc spectial type2: 393 * ecc bits: 0xC0[4,5] 0xF0[4,5] 394 * [0b0000, 0b0011], No bit errors were detected; 395 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 396 * reach Flipping Bits; 397 * [0b1000, 0b1011], Multiple bit errors were detected and 398 * not corrected. 399 * [0b1100, 0b1111], reserved. 400 */ 401 static u32 sfc_nand_get_ecc_status2(void) 402 { 403 u32 ret; 404 u32 i; 405 u8 ecc; 406 u8 status, status1; 407 u32 timeout = 1000 * 1000; 408 409 for (i = 0; i < timeout; i++) { 410 ret = sfc_nand_read_feature(0xC0, &status); 411 412 if (ret != SFC_OK) 413 return SFC_NAND_ECC_ERROR; 414 415 ret = sfc_nand_read_feature(0xF0, &status1); 416 417 if (ret != SFC_OK) 418 return SFC_NAND_ECC_ERROR; 419 420 if (!(status & (1 << 0))) 421 break; 422 423 sfc_delay(1); 424 } 425 426 ecc = (status >> 4) & 0x03; 427 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 428 429 if (ecc < 7) 430 ret = SFC_NAND_ECC_OK; 431 else if (ecc == 7) 432 ret = SFC_NAND_ECC_REFRESH; 433 else 434 ret = (u32)SFC_NAND_ECC_ERROR; 435 436 return ret; 437 } 438 439 /* 440 * ecc spectial type3: 441 * ecc bits: 0xC0[4,5] 0xF0[4,5] 442 * [0b0000, 0b0011], No bit errors were detected; 443 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 444 * reach Flipping Bits; 445 * [0b1000, 0b1011], Multiple bit errors were detected and 446 * not corrected. 447 * [0b1100, 0b1111], Bit error count equals the bit flip 448 * detectio nthreshold 449 */ 450 static u32 sfc_nand_get_ecc_status3(void) 451 { 452 u32 ret; 453 u32 i; 454 u8 ecc; 455 u8 status, status1; 456 u32 timeout = 1000 * 1000; 457 458 for (i = 0; i < timeout; i++) { 459 ret = sfc_nand_read_feature(0xC0, &status); 460 461 if (ret != SFC_OK) 462 return SFC_NAND_ECC_ERROR; 463 464 ret = sfc_nand_read_feature(0xF0, &status1); 465 466 if (ret != SFC_OK) 467 return SFC_NAND_ECC_ERROR; 468 469 if (!(status & (1 << 0))) 470 break; 471 472 sfc_delay(1); 473 } 474 475 ecc = (status >> 4) & 0x03; 476 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 477 478 if (ecc < 7) 479 ret = SFC_NAND_ECC_OK; 480 else if (ecc == 7 || ecc >= 12) 481 ret = SFC_NAND_ECC_REFRESH; 482 else 483 ret = (u32)SFC_NAND_ECC_ERROR; 484 485 return ret; 486 } 487 488 /* 489 * ecc spectial type4: 490 * ecc bits: 0xC0[2,5] 491 * [0b0000], No bit errors were detected; 492 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 493 * reach Flipping Bits; 494 * [0b1000], Multiple bit errors were detected and 495 * not corrected. 496 * [0b1100], Bit error count equals the bit flip 497 * detection threshold 498 * else, reserved 499 */ 500 static u32 sfc_nand_get_ecc_status4(void) 501 { 502 u32 ret; 503 u32 i; 504 u8 ecc; 505 u8 status; 506 u32 timeout = 1000 * 1000; 507 508 for (i = 0; i < timeout; i++) { 509 ret = sfc_nand_read_feature(0xC0, &status); 510 511 if (ret != SFC_OK) 512 return SFC_NAND_ECC_ERROR; 513 514 if (!(status & (1 << 0))) 515 break; 516 517 sfc_delay(1); 518 } 519 520 ecc = (status >> 2) & 0x0f; 521 522 if (ecc < 7) 523 ret = SFC_NAND_ECC_OK; 524 else if (ecc == 7 || ecc == 12) 525 ret = SFC_NAND_ECC_REFRESH; 526 else 527 ret = (u32)SFC_NAND_ECC_ERROR; 528 529 return ret; 530 } 531 532 /* 533 * ecc spectial type5: 534 * ecc bits: 0xC0[4,6] 535 * [0b000], No bit errors were detected; 536 * [0b001, 0b011], Bit errors were detected and corrected. Not 537 * reach Flipping Bits; 538 * [0b100], Bit error count equals the bit flip 539 * detection threshold 540 * [0b101, 0b110], Reserved; 541 * [0b111], Multiple bit errors were detected and 542 * not corrected. 543 */ 544 static u32 sfc_nand_get_ecc_status5(void) 545 { 546 u32 ret; 547 u32 i; 548 u8 ecc; 549 u8 status; 550 u32 timeout = 1000 * 1000; 551 552 for (i = 0; i < timeout; i++) { 553 ret = sfc_nand_read_feature(0xC0, &status); 554 555 if (ret != SFC_OK) 556 return SFC_NAND_ECC_ERROR; 557 558 if (!(status & (1 << 0))) 559 break; 560 561 sfc_delay(1); 562 } 563 564 ecc = (status >> 4) & 0x07; 565 566 if (ecc < 4) 567 ret = SFC_NAND_ECC_OK; 568 else if (ecc == 4) 569 ret = SFC_NAND_ECC_REFRESH; 570 else 571 ret = (u32)SFC_NAND_ECC_ERROR; 572 573 return ret; 574 } 575 576 /* 577 * ecc spectial type6: 578 * ecc bits: 0xC0[4,6] 579 * [0b000], No bit errors were detected; 580 * [0b001], 1-3 Bit errors were detected and corrected. Not 581 * reach Flipping Bits; 582 * [0b010], Multiple bit errors were detected and 583 * not corrected. 584 * [0b011], 4-6 Bit errors were detected and corrected. Not 585 * reach Flipping Bits; 586 * [0b101], Bit error count equals the bit flip 587 * detectionthreshold 588 * others, Reserved. 589 */ 590 static u32 sfc_nand_get_ecc_status6(void) 591 { 592 u32 ret; 593 u32 i; 594 u8 ecc; 595 u8 status; 596 u32 timeout = 1000 * 1000; 597 598 for (i = 0; i < timeout; i++) { 599 ret = sfc_nand_read_feature(0xC0, &status); 600 601 if (ret != SFC_OK) 602 return SFC_NAND_ECC_ERROR; 603 604 if (!(status & (1 << 0))) 605 break; 606 607 sfc_delay(1); 608 } 609 610 ecc = (status >> 4) & 0x07; 611 612 if (ecc == 0 || ecc == 1 || ecc == 3) 613 ret = SFC_NAND_ECC_OK; 614 else if (ecc == 5) 615 ret = SFC_NAND_ECC_REFRESH; 616 else 617 ret = (u32)SFC_NAND_ECC_ERROR; 618 619 return ret; 620 } 621 622 /* 623 * ecc spectial type7: 624 * ecc bits: 0xC0[4,7] 625 * [0b0000], No bit errors were detected; 626 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not 627 * reach Flipping Bits; 628 * [0b1000], 8 Bit errors were detected and corrected. Bit error count 629 * equals the bit flip detectionthreshold; 630 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; 631 * others, Reserved. 632 */ 633 static u32 sfc_nand_get_ecc_status7(void) 634 { 635 u32 ret; 636 u32 i; 637 u8 ecc; 638 u8 status; 639 u32 timeout = 1000 * 1000; 640 641 for (i = 0; i < timeout; i++) { 642 ret = sfc_nand_read_feature(0xC0, &status); 643 644 if (ret != SFC_OK) 645 return SFC_NAND_ECC_ERROR; 646 647 if (!(status & (1 << 0))) 648 break; 649 650 sfc_delay(1); 651 } 652 653 ecc = (status >> 4) & 0xf; 654 655 if (ecc < 7) 656 ret = SFC_NAND_ECC_OK; 657 else if (ecc == 7 || ecc == 8) 658 ret = SFC_NAND_ECC_REFRESH; 659 else 660 ret = (u32)SFC_NAND_ECC_ERROR; 661 662 return ret; 663 } 664 665 /* 666 * ecc spectial type8: 667 * ecc bits: 0xC0[4,6] 668 * [0b000], No bit errors were detected; 669 * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not 670 * reach Flipping Bits; 671 * [0b100], Bit error count equals the bit flip 672 * detection threshold 673 * others, Reserved. 674 */ 675 static u32 sfc_nand_get_ecc_status8(void) 676 { 677 u32 ret; 678 u32 i; 679 u8 ecc; 680 u8 status; 681 u32 timeout = 1000 * 1000; 682 683 for (i = 0; i < timeout; i++) { 684 ret = sfc_nand_read_feature(0xC0, &status); 685 686 if (ret != SFC_OK) 687 return SFC_NAND_ECC_ERROR; 688 689 if (!(status & (1 << 0))) 690 break; 691 692 sfc_delay(1); 693 } 694 695 ecc = (status >> 4) & 0x07; 696 697 if (ecc < 4) 698 ret = SFC_NAND_ECC_OK; 699 else if (ecc == 4) 700 ret = SFC_NAND_ECC_REFRESH; 701 else 702 ret = (u32)SFC_NAND_ECC_ERROR; 703 704 return ret; 705 } 706 707 u32 sfc_nand_erase_block(u8 cs, u32 addr) 708 { 709 int ret; 710 struct rk_sfc_op op; 711 u8 status; 712 713 rkflash_print_dio("%s %x\n", __func__, addr); 714 op.sfcmd.d32 = 0; 715 op.sfcmd.b.cmd = 0xd8; 716 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 717 op.sfcmd.b.rw = SFC_WRITE; 718 719 op.sfctrl.d32 = 0; 720 721 sfc_nand_write_en(); 722 ret = sfc_request(&op, addr, NULL, 0); 723 724 if (ret != SFC_OK) 725 return ret; 726 727 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 728 729 if (status & (1 << 2)) 730 return SFC_NAND_PROG_ERASE_ERROR; 731 732 return ret; 733 } 734 735 static u32 sfc_nand_read_cache(u32 row, u32 *p_page_buf, u32 column, u32 len) 736 { 737 int ret; 738 u32 plane; 739 struct rk_sfc_op op; 740 741 op.sfcmd.d32 = 0; 742 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 743 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 744 op.sfcmd.b.dummybits = 8; 745 746 op.sfctrl.d32 = 0; 747 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 748 op.sfctrl.b.addrbits = 16; 749 750 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 751 752 ret = sfc_request(&op, plane | column, p_page_buf, len); 753 if (ret != SFC_OK) 754 return SFC_NAND_HW_ERROR; 755 756 return ret; 757 } 758 759 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 760 { 761 int ret; 762 u32 plane; 763 struct rk_sfc_op op; 764 u8 status; 765 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 766 u32 data_area_size = SFC_NAND_SECTOR_SIZE * p_nand_info->sec_per_page; 767 768 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 769 sfc_nand_write_en(); 770 771 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 772 p_nand_info->feature & FEA_SOFT_QOP_BIT && 773 sfc_get_version() < SFC_VER_3) 774 sfc_nand_rw_preset(); 775 776 op.sfcmd.d32 = 0; 777 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 778 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 779 op.sfcmd.b.rw = SFC_WRITE; 780 781 op.sfctrl.d32 = 0; 782 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 783 op.sfctrl.b.addrbits = 16; 784 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 785 sfc_request(&op, plane, p_page_buf, page_size); 786 787 /* 788 * At the moment of power lost or dev running in harsh environment, flash 789 * maybe work in a unkonw state and result in bit flip, when this situation 790 * is detected by cache recheck, it's better to wait a second for a reliable 791 * hardware environment to avoid abnormal data written to flash array. 792 */ 793 if (p_nand_info->id0 == MID_GIGADEV) { 794 sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size); 795 if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) { 796 rkflash_print_error("%s %x cache bitflip\n", __func__, addr); 797 mdelay(1000); 798 sfc_request(&op, plane, p_page_buf, page_size); 799 } 800 } 801 802 op.sfcmd.d32 = 0; 803 op.sfcmd.b.cmd = 0x10; 804 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 805 op.sfcmd.b.rw = SFC_WRITE; 806 807 op.sfctrl.d32 = 0; 808 ret = sfc_request(&op, addr, p_page_buf, 0); 809 810 if (ret != SFC_OK) 811 return ret; 812 813 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 814 if (status & (1 << 3)) 815 return SFC_NAND_PROG_ERASE_ERROR; 816 817 return ret; 818 } 819 820 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 821 { 822 int ret; 823 u32 sec_per_page = p_nand_info->sec_per_page; 824 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 825 struct nand_mega_area *meta = &p_nand_info->meta; 826 827 memcpy(gp_page_buf, p_data, data_size); 828 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 829 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 830 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 831 832 if (sec_per_page == 8) { 833 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 834 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 835 } 836 837 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 838 839 return ret; 840 } 841 842 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 843 { 844 int ret; 845 u32 plane; 846 struct rk_sfc_op op; 847 u32 ecc_result; 848 u8 status; 849 850 op.sfcmd.d32 = 0; 851 op.sfcmd.b.cmd = 0x13; 852 op.sfcmd.b.rw = SFC_WRITE; 853 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 854 855 op.sfctrl.d32 = 0; 856 857 sfc_request(&op, row, p_page_buf, 0); 858 859 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 860 p_nand_info->feature & FEA_SOFT_QOP_BIT && 861 sfc_get_version() < SFC_VER_3) 862 sfc_nand_rw_preset(); 863 864 sfc_nand_wait_busy(&status, 1000 * 1000); 865 ecc_result = p_nand_info->ecc_status(); 866 867 op.sfcmd.d32 = 0; 868 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 869 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 870 op.sfcmd.b.dummybits = 8; 871 872 op.sfctrl.d32 = 0; 873 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 874 op.sfctrl.b.addrbits = 16; 875 876 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 877 ret = sfc_request(&op, plane | column, p_page_buf, len); 878 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 879 880 if (ret != SFC_OK) 881 return SFC_NAND_HW_ERROR; 882 883 return ecc_result; 884 } 885 886 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 887 { 888 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 889 890 return sfc_nand_read(addr, p_page_buf, 0, page_size); 891 } 892 893 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 894 { 895 u32 ret; 896 u32 sec_per_page = p_nand_info->sec_per_page; 897 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 898 struct nand_mega_area *meta = &p_nand_info->meta; 899 900 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 901 memcpy(p_data, gp_page_buf, data_size); 902 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 903 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 904 905 if (p_nand_info->sec_per_page == 8) { 906 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 907 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 908 } 909 910 if (ret == SFC_NAND_HW_ERROR) 911 ret = SFC_NAND_ECC_ERROR; 912 913 if (ret != SFC_NAND_ECC_OK) { 914 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 915 916 if (p_data) 917 rkflash_print_hex("data:", p_data, 4, 8); 918 919 if (p_spare) 920 rkflash_print_hex("spare:", p_spare, 4, 2); 921 } 922 923 return ret; 924 } 925 926 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 927 { 928 u32 ret; 929 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 930 u32 marker = 0; 931 932 ret = sfc_nand_read(addr, &marker, data_size, 2); 933 934 /* unify with mtd framework */ 935 if (ret == SFC_NAND_ECC_ERROR || (u16)marker != 0xffff) 936 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 937 __func__, addr, ret, marker); 938 939 /* Original bad block */ 940 if ((u16)marker != 0xffff) 941 return true; 942 943 return false; 944 } 945 946 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 947 { 948 u32 ret; 949 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 950 951 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 952 953 if (ret) 954 return SFC_NAND_HW_ERROR; 955 956 gp_page_buf[data_size / 4] = 0x0; 957 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 958 959 if (ret) 960 return SFC_NAND_HW_ERROR; 961 962 return ret; 963 } 964 965 int sfc_nand_read_id(u8 *data) 966 { 967 int ret; 968 struct rk_sfc_op op; 969 970 op.sfcmd.d32 = 0; 971 op.sfcmd.b.cmd = CMD_READ_JEDECID; 972 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 973 974 op.sfctrl.d32 = 0; 975 op.sfctrl.b.addrbits = 8; 976 977 ret = sfc_request(&op, 0, data, 3); 978 979 return ret; 980 } 981 982 /* 983 * Read the 1st page's 1st byte of a phy_blk 984 * If not FF, it's bad blk 985 */ 986 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 987 { 988 u32 bad_cnt, page; 989 u32 blk_per_die; 990 u16 blk; 991 992 rkflash_print_info("%s\n", __func__); 993 994 bad_cnt = 0; 995 blk_per_die = p_nand_info->plane_per_die * 996 p_nand_info->blk_per_plane; 997 998 for (blk = 0; blk < blk_per_die; blk++) { 999 page = (blk + blk_per_die * die) * 1000 p_nand_info->page_per_blk; 1001 1002 if (sfc_nand_check_bad_block(die, page)) { 1003 table[bad_cnt++] = blk; 1004 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 1005 } 1006 } 1007 1008 return (int)bad_cnt; 1009 } 1010 1011 void sfc_nand_ftl_ops_init(void) 1012 { 1013 /* para init */ 1014 g_nand_phy_info.nand_type = 1; 1015 g_nand_phy_info.die_num = 1; 1016 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 1017 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 1018 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 1019 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 1020 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 1021 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 1022 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 1023 p_nand_info->page_per_blk; 1024 g_nand_phy_info.reserved_blk = 8; 1025 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 1026 p_nand_info->blk_per_plane; 1027 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 1028 1029 /* driver register */ 1030 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 1031 g_nand_ops.erase_blk = sfc_nand_erase_block; 1032 g_nand_ops.prog_page = sfc_nand_prog_page; 1033 g_nand_ops.read_page = sfc_nand_read_page; 1034 g_nand_ops.bch_sel = NULL; 1035 } 1036 1037 static int sfc_nand_enable_QE(void) 1038 { 1039 int ret = SFC_OK; 1040 u8 status; 1041 1042 ret = sfc_nand_read_feature(0xB0, &status); 1043 1044 if (ret != SFC_OK) 1045 return ret; 1046 1047 if (status & 1) /* is QE bit set */ 1048 return SFC_OK; 1049 1050 status |= 1; 1051 1052 return sfc_nand_write_feature(0xB0, status); 1053 } 1054 1055 u32 sfc_nand_init(void) 1056 { 1057 u8 status, id_byte[8]; 1058 1059 sfc_nand_read_id(id_byte); 1060 rkflash_print_error("sfc_nand id: %x %x %x\n", 1061 id_byte[0], id_byte[1], id_byte[2]); 1062 1063 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 1064 return (u32)FTL_NO_FLASH; 1065 1066 p_nand_info = sfc_nand_get_info(id_byte); 1067 1068 if (!p_nand_info) 1069 return (u32)FTL_UNSUPPORTED_FLASH; 1070 1071 sfc_nand_dev.manufacturer = id_byte[0]; 1072 sfc_nand_dev.mem_type = id_byte[1]; 1073 sfc_nand_dev.capacity = p_nand_info->density; 1074 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 1075 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 1076 1077 /* disable block lock */ 1078 sfc_nand_write_feature(0xA0, 0); 1079 sfc_nand_dev.read_lines = DATA_LINES_X1; 1080 sfc_nand_dev.prog_lines = DATA_LINES_X1; 1081 sfc_nand_dev.page_read_cmd = 0x03; 1082 sfc_nand_dev.page_prog_cmd = 0x02; 1083 sfc_nand_dev.recheck_buffer = ftl_malloc(SFC_NAND_PAGE_MAX_SIZE); 1084 if (!sfc_nand_dev.recheck_buffer) { 1085 rkflash_print_error("%s recheck_buffer alloc failed\n", __func__); 1086 return -1; 1087 } 1088 1089 if (p_nand_info->feature & FEA_4BIT_READ) { 1090 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 1091 !p_nand_info->has_qe_bits) { 1092 sfc_nand_dev.read_lines = DATA_LINES_X4; 1093 sfc_nand_dev.page_read_cmd = 0x6b; 1094 } 1095 } 1096 1097 if (p_nand_info->feature & FEA_4BIT_PROG && 1098 sfc_nand_dev.read_lines == DATA_LINES_X4) { 1099 sfc_nand_dev.prog_lines = DATA_LINES_X4; 1100 sfc_nand_dev.page_prog_cmd = 0x32; 1101 } 1102 1103 sfc_nand_read_feature(0xA0, &status); 1104 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 1105 sfc_nand_read_feature(0xB0, &status); 1106 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 1107 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 1108 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 1109 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 1110 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 1111 1112 return SFC_OK; 1113 } 1114 1115 void sfc_nand_deinit(void) 1116 { 1117 /* to-do */ 1118 kfree(sfc_nand_dev.recheck_buffer); 1119 } 1120 1121 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 1122 { 1123 return &sfc_nand_dev; 1124 } 1125 1126