1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/bug.h> 9 #include <linux/delay.h> 10 11 #include "flash_com.h" 12 #include "rkflash_debug.h" 13 #include "rk_sftl.h" 14 #include "sfc.h" 15 #include "sfc_nand.h" 16 17 static u32 sfc_nand_get_ecc_status0(void); 18 static u32 sfc_nand_get_ecc_status1(void); 19 static u32 sfc_nand_get_ecc_status2(void); 20 static u32 sfc_nand_get_ecc_status3(void); 21 static u32 sfc_nand_get_ecc_status4(void); 22 static u32 sfc_nand_get_ecc_status5(void); 23 static u32 sfc_nand_get_ecc_status6(void); 24 static u32 sfc_nand_get_ecc_status7(void); 25 static u32 sfc_nand_get_ecc_status8(void); 26 static u32 sfc_nand_get_ecc_status9(void); 27 28 static struct nand_info spi_nand_tbl[] = { 29 /* TC58CVG0S0HxAIx */ 30 { 0x98, 0xC2, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 31 /* TC58CVG1S0HxAIx */ 32 { 0x98, 0xCB, 0x00, 4, 0x40, 2, 1024, 0x00, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 33 /* TC58CVG2S0HRAIJ */ 34 { 0x98, 0xED, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 0, { 0x04, 0x0C, 0x08, 0x10 }, &sfc_nand_get_ecc_status0 }, 35 /* TC58CVG1S3HRAIJ */ 36 { 0x98, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 37 /* TC58CVG0S3HRAIJ */ 38 { 0x98, 0xE2, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 39 40 /* MX35LF1GE4AB */ 41 { 0xC2, 0x12, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 42 /* MX35LF2GE4AB */ 43 { 0xC2, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 44 /* MX35LF2GE4AD */ 45 { 0xC2, 0x26, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 46 /* MX35LF4GE4AD */ 47 { 0xC2, 0x37, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 48 /* MX35UF1GE4AC */ 49 { 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 50 /* MX35UF2GE4AC */ 51 { 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 52 53 /* GD5F1GQ4UAYIG */ 54 { 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 55 /* GD5F1GQ4RB9IGR */ 56 { 0xC8, 0xD1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 57 /* GD5F2GQ40BY2GR */ 58 { 0xC8, 0xD2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 59 /* GD5F1GQ5UEYIG */ 60 { 0xC8, 0x51, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 61 /* GD5F2GQ5UEYIG */ 62 { 0xC8, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 63 /* GD5F1GQ4R */ 64 { 0xC8, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 65 /* GD5F4GQ6RExxG 1*4096 */ 66 { 0xC8, 0x45, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, 67 /* GD5F4GQ6UExxG 1*4096 */ 68 { 0xC8, 0x55, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status2 }, 69 /* GD5F1GQ4UExxH */ 70 { 0xC8, 0xD9, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status3 }, 71 /* GD5F1GQ5REYIG */ 72 { 0xC8, 0x41, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 73 /* GD5F2GQ5REYIG */ 74 { 0xC8, 0x42, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 75 /* GD5F2GM7RxG */ 76 { 0xC8, 0x82, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 77 /* GD5F2GM7UxG */ 78 { 0xC8, 0x92, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 79 /* GD5F1GM7UxG */ 80 { 0xC8, 0x91, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status2 }, 81 /* GD5F4GQ4UAYIG 1*4096 */ 82 { 0xC8, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 }, 83 84 /* W25N01GV */ 85 { 0xEF, 0xAA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 86 /* W25N02KVZEIR */ 87 { 0xEF, 0xAA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 88 /* W25N04KVZEIR */ 89 { 0xEF, 0xAA, 0x23, 4, 0x40, 1, 4096, 0x4C, 20, 0x8, 0, { 0x04, 0x14, 0x24, 0x34 }, &sfc_nand_get_ecc_status0 }, 90 /* W25N01GW */ 91 { 0xEF, 0xBA, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 92 /* W25N02KW */ 93 { 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 }, 94 /* W25N512GVEIG */ 95 { 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 }, 96 97 /* HYF2GQ4UAACAE */ 98 { 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 99 /* HYF1GQ4UDACAE */ 100 { 0xC9, 0x21, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 101 /* HYF1GQ4UPACAE */ 102 { 0xC9, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 103 /* HYF2GQ4UDACAE */ 104 { 0xC9, 0x22, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 105 /* HYF2GQ4UHCCAE */ 106 { 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 107 /* HYF4GQ4UAACBE */ 108 { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 }, 109 110 /* FS35ND01G-S1 */ 111 { 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 112 /* FS35ND02G-S2 */ 113 { 0xCD, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x00, 19, 0x4, 0, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 114 /* FS35ND01G-S1Y2 */ 115 { 0xCD, 0xEA, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 116 /* FS35ND02G-S3Y2 */ 117 { 0xCD, 0xEB, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 118 /* FS35ND04G-S2Y2 1*4096 */ 119 { 0xCD, 0xEC, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 120 /* F35SQA001G */ 121 { 0xCD, 0x71, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 122 /* F35SQA002G */ 123 { 0xCD, 0x72, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 124 /* F35SQA512M */ 125 { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 126 /* F35UQA512M */ 127 { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 128 129 /* DS35Q1GA-IB */ 130 { 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 131 /* DS35Q2GA-IB */ 132 { 0xE5, 0x72, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 133 /* DS35M1GA-1B */ 134 { 0xE5, 0x21, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 135 /* DS35M2GA-IB */ 136 { 0xE5, 0x22, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 137 /* DS35Q1GB-IB */ 138 { 0xE5, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 139 /* DS35Q2GB-IB */ 140 { 0xE5, 0xF2, 0x00, 4, 0x40, 2, 1024, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 141 /* DS35Q4GM */ 142 { 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 143 /* DS35M1GB-IB */ 144 { 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 145 146 /* EM73C044VCC-H */ 147 { 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 148 /* EM73D044VCE-H */ 149 { 0xD5, 0x20, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 150 /* EM73E044SNA-G */ 151 { 0xD5, 0x03, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x28, 0x08, 0x2C }, &sfc_nand_get_ecc_status0 }, 152 /* EM73C044VCF-H */ 153 { 0xD5, 0x25, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 154 155 /* XT26G02A */ 156 { 0x0B, 0xE2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 157 /* XT26G01A */ 158 { 0x0B, 0xE1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 159 /* XT26G04A */ 160 { 0x0B, 0xE3, 0x00, 4, 0x80, 1, 2048, 0x4C, 20, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 161 /* XT26G01B */ 162 { 0x0B, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status4 }, 163 /* XT26G02B */ 164 { 0x0B, 0xF2, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 }, 165 /* XT26G01C */ 166 { 0x0B, 0x11, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 167 /* XT26G02C */ 168 { 0x0B, 0x12, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status7 }, 169 /* XT26G04C */ 170 { 0x0B, 0x13, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x8, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status7 }, 171 /* XT26G11C */ 172 { 0x0B, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 173 174 /* MT29F2G01ABA, XT26G02E, F50L2G41XA */ 175 { 0x2C, 0x24, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 176 /* MT29F1G01ABA, F50L1G41XA */ 177 { 0x2C, 0x14, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x8, 0, { 0x20, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 }, 178 179 /* FM25S01 */ 180 { 0xA1, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x00, 0x04, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 181 /* FM25S01A */ 182 { 0xA1, 0xE4, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 183 /* FM25S02A */ 184 { 0xA1, 0xE5, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 185 /* FM25LS01 */ 186 { 0xA1, 0xA5, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 187 188 /* IS37SML01G1 */ 189 { 0xC8, 0x21, 0x00, 4, 0x40, 1, 1024, 0x00, 18, 0x1, 0, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 190 /* F50L1G41LB */ 191 { 0xC8, 0x01, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x1, 0, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 192 /* ATO25D1GA */ 193 { 0x9B, 0x12, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x1, 1, { 0x14, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 194 /* BWJX08K-2Gb */ 195 { 0xBC, 0xB3, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 1, { 0x04, 0x10, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 }, 196 /* JS28U1GQSCAHG-83 */ 197 { 0xBF, 0x21, 0x00, 4, 0x40, 1, 1024, 0x40, 18, 0x4, 1, { 0x08, 0x0C, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 198 /* SGM7000I-S24W1GH */ 199 { 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 }, 200 /* TX25G01 */ 201 { 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 }, 202 /* S35ML04G3 */ 203 { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 }, 204 }; 205 206 static struct nand_info *p_nand_info; 207 static u32 gp_page_buf[SFC_NAND_PAGE_MAX_SIZE / 4]; 208 static struct SFNAND_DEV sfc_nand_dev; 209 210 static struct nand_info *sfc_nand_get_info(u8 *nand_id) 211 { 212 u32 i; 213 214 for (i = 0; i < ARRAY_SIZE(spi_nand_tbl); i++) { 215 if (spi_nand_tbl[i].id0 == nand_id[0] && 216 spi_nand_tbl[i].id1 == nand_id[1]) { 217 if (spi_nand_tbl[i].id2 && 218 spi_nand_tbl[i].id2 != nand_id[2]) 219 continue; 220 221 return &spi_nand_tbl[i]; 222 } 223 } 224 225 return NULL; 226 } 227 228 static int sfc_nand_write_en(void) 229 { 230 int ret; 231 struct rk_sfc_op op; 232 233 op.sfcmd.d32 = 0; 234 op.sfcmd.b.cmd = CMD_WRITE_EN; 235 236 op.sfctrl.d32 = 0; 237 238 ret = sfc_request(&op, 0, NULL, 0); 239 return ret; 240 } 241 242 static int sfc_nand_rw_preset(void) 243 { 244 int ret; 245 struct rk_sfc_op op; 246 247 op.sfcmd.d32 = 0; 248 op.sfcmd.b.cmd = 0xff; 249 op.sfcmd.b.cs = 2; 250 251 op.sfctrl.d32 = 0; 252 op.sfctrl.b.datalines = 2; 253 op.sfctrl.b.cmdlines = 2; 254 op.sfctrl.b.addrlines = 2; 255 256 ret = sfc_request(&op, 0, NULL, 0); 257 return ret; 258 } 259 260 static int sfc_nand_read_feature(u8 addr, u8 *data) 261 { 262 int ret; 263 struct rk_sfc_op op; 264 265 op.sfcmd.d32 = 0; 266 op.sfcmd.b.cmd = 0x0F; 267 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 268 269 op.sfctrl.d32 = 0; 270 op.sfctrl.b.addrbits = 8; 271 272 *data = 0; 273 274 ret = sfc_request(&op, addr, data, 1); 275 276 if (ret != SFC_OK) 277 return ret; 278 279 return SFC_OK; 280 } 281 282 static int sfc_nand_write_feature(u32 addr, u8 status) 283 { 284 int ret; 285 struct rk_sfc_op op; 286 287 sfc_nand_write_en(); 288 289 op.sfcmd.d32 = 0; 290 op.sfcmd.b.cmd = 0x1F; 291 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 292 op.sfcmd.b.rw = SFC_WRITE; 293 294 op.sfctrl.d32 = 0; 295 op.sfctrl.b.addrbits = 8; 296 297 ret = sfc_request(&op, addr, &status, 1); 298 299 if (ret != SFC_OK) 300 return ret; 301 302 return ret; 303 } 304 305 static int sfc_nand_wait_busy(u8 *data, int timeout) 306 { 307 int ret; 308 int i; 309 u8 status; 310 311 *data = 0; 312 313 for (i = 0; i < timeout; i++) { 314 ret = sfc_nand_read_feature(0xC0, &status); 315 316 if (ret != SFC_OK) 317 return ret; 318 319 *data = status; 320 321 if (!(status & (1 << 0))) 322 return SFC_OK; 323 324 sfc_delay(1); 325 } 326 327 return SFC_NAND_WAIT_TIME_OUT; 328 } 329 330 /* 331 * ecc default: 332 * ecc bits: 0xC0[4,5] 333 * 0b00, No bit errors were detected 334 * 0b01, Bit errors were detected and corrected. 335 * 0b10, Multiple bit errors were detected and not corrected. 336 * 0b11, Bits errors were detected and corrected, bit error count 337 * reach the bit flip detection threshold 338 */ 339 static u32 sfc_nand_get_ecc_status0(void) 340 { 341 u32 ret; 342 u32 i; 343 u8 ecc; 344 u8 status; 345 u32 timeout = 1000 * 1000; 346 347 for (i = 0; i < timeout; i++) { 348 ret = sfc_nand_read_feature(0xC0, &status); 349 350 if (ret != SFC_OK) 351 return SFC_NAND_ECC_ERROR; 352 353 if (!(status & (1 << 0))) 354 break; 355 356 sfc_delay(1); 357 } 358 359 ecc = (status >> 4) & 0x03; 360 361 if (ecc <= 1) 362 ret = SFC_NAND_ECC_OK; 363 else if (ecc == 2) 364 ret = (u32)SFC_NAND_ECC_ERROR; 365 else 366 ret = SFC_NAND_ECC_REFRESH; 367 368 return ret; 369 } 370 371 /* 372 * ecc spectial type1: 373 * ecc bits: 0xC0[4,5] 374 * 0b00, No bit errors were detected; 375 * 0b01, Bits errors were detected and corrected, bit error count 376 * may reach the bit flip detection threshold; 377 * 0b10, Multiple bit errors were detected and not corrected; 378 * 0b11, Reserved. 379 */ 380 static u32 sfc_nand_get_ecc_status1(void) 381 { 382 u32 ret; 383 u32 i; 384 u8 ecc; 385 u8 status; 386 u32 timeout = 1000 * 1000; 387 388 for (i = 0; i < timeout; i++) { 389 ret = sfc_nand_read_feature(0xC0, &status); 390 391 if (ret != SFC_OK) 392 return SFC_NAND_ECC_ERROR; 393 394 if (!(status & (1 << 0))) 395 break; 396 397 sfc_delay(1); 398 } 399 400 ecc = (status >> 4) & 0x03; 401 402 if (ecc == 0) 403 ret = SFC_NAND_ECC_OK; 404 else if (ecc == 1) 405 ret = SFC_NAND_ECC_REFRESH; 406 else 407 ret = (u32)SFC_NAND_ECC_ERROR; 408 409 return ret; 410 } 411 412 /* 413 * ecc spectial type2: 414 * ecc bits: 0xC0[4,5] 0xF0[4,5] 415 * [0b0000, 0b0011], No bit errors were detected; 416 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 417 * reach Flipping Bits; 418 * [0b1000, 0b1011], Multiple bit errors were detected and 419 * not corrected. 420 * [0b1100, 0b1111], reserved. 421 */ 422 static u32 sfc_nand_get_ecc_status2(void) 423 { 424 u32 ret; 425 u32 i; 426 u8 ecc; 427 u8 status, status1; 428 u32 timeout = 1000 * 1000; 429 430 for (i = 0; i < timeout; i++) { 431 ret = sfc_nand_read_feature(0xC0, &status); 432 433 if (ret != SFC_OK) 434 return SFC_NAND_ECC_ERROR; 435 436 ret = sfc_nand_read_feature(0xF0, &status1); 437 438 if (ret != SFC_OK) 439 return SFC_NAND_ECC_ERROR; 440 441 if (!(status & (1 << 0))) 442 break; 443 444 sfc_delay(1); 445 } 446 447 ecc = (status >> 4) & 0x03; 448 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 449 450 if (ecc < 7) 451 ret = SFC_NAND_ECC_OK; 452 else if (ecc == 7) 453 ret = SFC_NAND_ECC_REFRESH; 454 else 455 ret = (u32)SFC_NAND_ECC_ERROR; 456 457 return ret; 458 } 459 460 /* 461 * ecc spectial type3: 462 * ecc bits: 0xC0[4,5] 0xF0[4,5] 463 * [0b0000, 0b0011], No bit errors were detected; 464 * [0b0100, 0b0111], Bit errors were detected and corrected. Not 465 * reach Flipping Bits; 466 * [0b1000, 0b1011], Multiple bit errors were detected and 467 * not corrected. 468 * [0b1100, 0b1111], Bit error count equals the bit flip 469 * detectio nthreshold 470 */ 471 static u32 sfc_nand_get_ecc_status3(void) 472 { 473 u32 ret; 474 u32 i; 475 u8 ecc; 476 u8 status, status1; 477 u32 timeout = 1000 * 1000; 478 479 for (i = 0; i < timeout; i++) { 480 ret = sfc_nand_read_feature(0xC0, &status); 481 482 if (ret != SFC_OK) 483 return SFC_NAND_ECC_ERROR; 484 485 ret = sfc_nand_read_feature(0xF0, &status1); 486 487 if (ret != SFC_OK) 488 return SFC_NAND_ECC_ERROR; 489 490 if (!(status & (1 << 0))) 491 break; 492 493 sfc_delay(1); 494 } 495 496 ecc = (status >> 4) & 0x03; 497 ecc = (ecc << 2) | ((status1 >> 4) & 0x03); 498 499 if (ecc < 7) 500 ret = SFC_NAND_ECC_OK; 501 else if (ecc == 7 || ecc >= 12) 502 ret = SFC_NAND_ECC_REFRESH; 503 else 504 ret = (u32)SFC_NAND_ECC_ERROR; 505 506 return ret; 507 } 508 509 /* 510 * ecc spectial type4: 511 * ecc bits: 0xC0[2,5] 512 * [0b0000], No bit errors were detected; 513 * [0b0001, 0b0111], Bit errors were detected and corrected. Not 514 * reach Flipping Bits; 515 * [0b1000], Multiple bit errors were detected and 516 * not corrected. 517 * [0b1100], Bit error count equals the bit flip 518 * detection threshold 519 * else, reserved 520 */ 521 static u32 sfc_nand_get_ecc_status4(void) 522 { 523 u32 ret; 524 u32 i; 525 u8 ecc; 526 u8 status; 527 u32 timeout = 1000 * 1000; 528 529 for (i = 0; i < timeout; i++) { 530 ret = sfc_nand_read_feature(0xC0, &status); 531 532 if (ret != SFC_OK) 533 return SFC_NAND_ECC_ERROR; 534 535 if (!(status & (1 << 0))) 536 break; 537 538 sfc_delay(1); 539 } 540 541 ecc = (status >> 2) & 0x0f; 542 543 if (ecc < 7) 544 ret = SFC_NAND_ECC_OK; 545 else if (ecc == 7 || ecc == 12) 546 ret = SFC_NAND_ECC_REFRESH; 547 else 548 ret = (u32)SFC_NAND_ECC_ERROR; 549 550 return ret; 551 } 552 553 /* 554 * ecc spectial type5: 555 * ecc bits: 0xC0[4,6] 556 * [0b000], No bit errors were detected; 557 * [0b001, 0b011], Bit errors were detected and corrected. Not 558 * reach Flipping Bits; 559 * [0b100], Bit error count equals the bit flip 560 * detection threshold 561 * [0b101, 0b110], Reserved; 562 * [0b111], Multiple bit errors were detected and 563 * not corrected. 564 */ 565 static u32 sfc_nand_get_ecc_status5(void) 566 { 567 u32 ret; 568 u32 i; 569 u8 ecc; 570 u8 status; 571 u32 timeout = 1000 * 1000; 572 573 for (i = 0; i < timeout; i++) { 574 ret = sfc_nand_read_feature(0xC0, &status); 575 576 if (ret != SFC_OK) 577 return SFC_NAND_ECC_ERROR; 578 579 if (!(status & (1 << 0))) 580 break; 581 582 sfc_delay(1); 583 } 584 585 ecc = (status >> 4) & 0x07; 586 587 if (ecc < 4) 588 ret = SFC_NAND_ECC_OK; 589 else if (ecc == 4) 590 ret = SFC_NAND_ECC_REFRESH; 591 else 592 ret = (u32)SFC_NAND_ECC_ERROR; 593 594 return ret; 595 } 596 597 /* 598 * ecc spectial type6: 599 * ecc bits: 0xC0[4,6] 600 * [0b000], No bit errors were detected; 601 * [0b001], 1-3 Bit errors were detected and corrected. Not 602 * reach Flipping Bits; 603 * [0b010], Multiple bit errors were detected and 604 * not corrected. 605 * [0b011], 4-6 Bit errors were detected and corrected. Not 606 * reach Flipping Bits; 607 * [0b101], Bit error count equals the bit flip 608 * detectionthreshold 609 * others, Reserved. 610 */ 611 static u32 sfc_nand_get_ecc_status6(void) 612 { 613 u32 ret; 614 u32 i; 615 u8 ecc; 616 u8 status; 617 u32 timeout = 1000 * 1000; 618 619 for (i = 0; i < timeout; i++) { 620 ret = sfc_nand_read_feature(0xC0, &status); 621 622 if (ret != SFC_OK) 623 return SFC_NAND_ECC_ERROR; 624 625 if (!(status & (1 << 0))) 626 break; 627 628 sfc_delay(1); 629 } 630 631 ecc = (status >> 4) & 0x07; 632 633 if (ecc == 0 || ecc == 1 || ecc == 3) 634 ret = SFC_NAND_ECC_OK; 635 else if (ecc == 5) 636 ret = SFC_NAND_ECC_REFRESH; 637 else 638 ret = (u32)SFC_NAND_ECC_ERROR; 639 640 return ret; 641 } 642 643 /* 644 * ecc spectial type7: 645 * ecc bits: 0xC0[4,7] 646 * [0b0000], No bit errors were detected; 647 * [0b0001, 0b0111], 1-7 Bit errors were detected and corrected. Not 648 * reach Flipping Bits; 649 * [0b1000], 8 Bit errors were detected and corrected. Bit error count 650 * equals the bit flip detectionthreshold; 651 * [0b1111], Bit errors greater than ECC capability(8 bits) and not corrected; 652 * others, Reserved. 653 */ 654 static u32 sfc_nand_get_ecc_status7(void) 655 { 656 u32 ret; 657 u32 i; 658 u8 ecc; 659 u8 status; 660 u32 timeout = 1000 * 1000; 661 662 for (i = 0; i < timeout; i++) { 663 ret = sfc_nand_read_feature(0xC0, &status); 664 665 if (ret != SFC_OK) 666 return SFC_NAND_ECC_ERROR; 667 668 if (!(status & (1 << 0))) 669 break; 670 671 sfc_delay(1); 672 } 673 674 ecc = (status >> 4) & 0xf; 675 676 if (ecc < 7) 677 ret = SFC_NAND_ECC_OK; 678 else if (ecc == 7 || ecc == 8) 679 ret = SFC_NAND_ECC_REFRESH; 680 else 681 ret = (u32)SFC_NAND_ECC_ERROR; 682 683 return ret; 684 } 685 686 /* 687 * ecc spectial type8: 688 * ecc bits: 0xC0[4,6] 689 * [0b000], No bit errors were detected; 690 * [0b001, 0b011], 1~3 Bit errors were detected and corrected. Not 691 * reach Flipping Bits; 692 * [0b100], Bit error count equals the bit flip 693 * detection threshold 694 * others, Reserved. 695 */ 696 static u32 sfc_nand_get_ecc_status8(void) 697 { 698 u32 ret; 699 u32 i; 700 u8 ecc; 701 u8 status; 702 u32 timeout = 1000 * 1000; 703 704 for (i = 0; i < timeout; i++) { 705 ret = sfc_nand_read_feature(0xC0, &status); 706 707 if (ret != SFC_OK) 708 return SFC_NAND_ECC_ERROR; 709 710 if (!(status & (1 << 0))) 711 break; 712 713 sfc_delay(1); 714 } 715 716 ecc = (status >> 4) & 0x07; 717 718 if (ecc < 4) 719 ret = SFC_NAND_ECC_OK; 720 else if (ecc == 4) 721 ret = SFC_NAND_ECC_REFRESH; 722 else 723 ret = (u32)SFC_NAND_ECC_ERROR; 724 725 return ret; 726 } 727 728 /* 729 * ecc spectial type9: 730 * ecc bits: 0xC0[4,5] 731 * 0b00, No bit errors were detected 732 * 0b01, 1-2Bit errors were detected and corrected. 733 * 0b10, 3-4Bit errors were detected and corrected. 734 * 0b11, 11 can be used as uncorrectable 735 */ 736 static u32 sfc_nand_get_ecc_status9(void) 737 { 738 u32 ret; 739 u32 i; 740 u8 ecc; 741 u8 status; 742 u32 timeout = 1000 * 1000; 743 744 for (i = 0; i < timeout; i++) { 745 ret = sfc_nand_read_feature(0xC0, &status); 746 747 if (ret != SFC_OK) 748 return SFC_NAND_ECC_ERROR; 749 750 if (!(status & (1 << 0))) 751 break; 752 753 sfc_delay(1); 754 } 755 756 ecc = (status >> 4) & 0x03; 757 758 if (ecc <= 1) 759 ret = SFC_NAND_ECC_OK; 760 else if (ecc == 2) 761 ret = SFC_NAND_ECC_REFRESH; 762 else 763 ret = (u32)SFC_NAND_ECC_ERROR; 764 765 return ret; 766 } 767 768 u32 sfc_nand_erase_block(u8 cs, u32 addr) 769 { 770 int ret; 771 struct rk_sfc_op op; 772 u8 status; 773 774 rkflash_print_dio("%s %x\n", __func__, addr); 775 op.sfcmd.d32 = 0; 776 op.sfcmd.b.cmd = 0xd8; 777 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 778 op.sfcmd.b.rw = SFC_WRITE; 779 780 op.sfctrl.d32 = 0; 781 782 sfc_nand_write_en(); 783 ret = sfc_request(&op, addr, NULL, 0); 784 785 if (ret != SFC_OK) 786 return ret; 787 788 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 789 790 if (status & (1 << 2)) 791 return SFC_NAND_PROG_ERASE_ERROR; 792 793 return ret; 794 } 795 796 static u32 sfc_nand_read_cache(u32 row, u32 *p_page_buf, u32 column, u32 len) 797 { 798 int ret; 799 u32 plane; 800 struct rk_sfc_op op; 801 802 op.sfcmd.d32 = 0; 803 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 804 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 805 op.sfcmd.b.dummybits = 8; 806 807 op.sfctrl.d32 = 0; 808 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 809 op.sfctrl.b.addrbits = 16; 810 811 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 812 813 ret = sfc_request(&op, plane | column, p_page_buf, len); 814 if (ret != SFC_OK) 815 return SFC_NAND_HW_ERROR; 816 817 return ret; 818 } 819 820 u32 sfc_nand_prog_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 821 { 822 int ret; 823 u32 plane; 824 struct rk_sfc_op op; 825 u8 status; 826 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 827 u32 data_area_size = SFC_NAND_SECTOR_SIZE * p_nand_info->sec_per_page; 828 829 rkflash_print_dio("%s %x %x\n", __func__, addr, p_page_buf[0]); 830 sfc_nand_write_en(); 831 832 if (sfc_nand_dev.prog_lines == DATA_LINES_X4 && 833 p_nand_info->feature & FEA_SOFT_QOP_BIT && 834 sfc_get_version() < SFC_VER_3) 835 sfc_nand_rw_preset(); 836 837 op.sfcmd.d32 = 0; 838 op.sfcmd.b.cmd = sfc_nand_dev.page_prog_cmd; 839 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 840 op.sfcmd.b.rw = SFC_WRITE; 841 842 op.sfctrl.d32 = 0; 843 op.sfctrl.b.datalines = sfc_nand_dev.prog_lines; 844 op.sfctrl.b.addrbits = 16; 845 plane = p_nand_info->plane_per_die == 2 ? ((addr >> 6) & 0x1) << 12 : 0; 846 sfc_request(&op, plane, p_page_buf, page_size); 847 848 /* 849 * At the moment of power lost or dev running in harsh environment, flash 850 * maybe work in a unkonw state and result in bit flip, when this situation 851 * is detected by cache recheck, it's better to wait a second for a reliable 852 * hardware environment to avoid abnormal data written to flash array. 853 */ 854 if (p_nand_info->id0 == MID_GIGADEV) { 855 sfc_nand_read_cache(addr, (u32 *)sfc_nand_dev.recheck_buffer, 0, data_area_size); 856 if (memcmp(sfc_nand_dev.recheck_buffer, p_page_buf, data_area_size)) { 857 rkflash_print_error("%s %x cache bitflip\n", __func__, addr); 858 mdelay(1000); 859 sfc_request(&op, plane, p_page_buf, page_size); 860 } 861 } 862 863 op.sfcmd.d32 = 0; 864 op.sfcmd.b.cmd = 0x10; 865 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 866 op.sfcmd.b.rw = SFC_WRITE; 867 868 op.sfctrl.d32 = 0; 869 ret = sfc_request(&op, addr, p_page_buf, 0); 870 871 if (ret != SFC_OK) 872 return ret; 873 874 ret = sfc_nand_wait_busy(&status, 1000 * 1000); 875 if (status & (1 << 3)) 876 return SFC_NAND_PROG_ERASE_ERROR; 877 878 return ret; 879 } 880 881 u32 sfc_nand_prog_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 882 { 883 int ret; 884 u32 sec_per_page = p_nand_info->sec_per_page; 885 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 886 struct nand_mega_area *meta = &p_nand_info->meta; 887 888 memcpy(gp_page_buf, p_data, data_size); 889 memset(&gp_page_buf[data_size / 4], 0xff, sec_per_page * 16); 890 gp_page_buf[(data_size + meta->off0) / 4] = p_spare[0]; 891 gp_page_buf[(data_size + meta->off1) / 4] = p_spare[1]; 892 893 if (sec_per_page == 8) { 894 gp_page_buf[(data_size + meta->off2) / 4] = p_spare[2]; 895 gp_page_buf[(data_size + meta->off3) / 4] = p_spare[3]; 896 } 897 898 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 899 900 return ret; 901 } 902 903 u32 sfc_nand_read(u32 row, u32 *p_page_buf, u32 column, u32 len) 904 { 905 int ret; 906 u32 plane; 907 struct rk_sfc_op op; 908 u32 ecc_result; 909 u8 status; 910 911 op.sfcmd.d32 = 0; 912 op.sfcmd.b.cmd = 0x13; 913 op.sfcmd.b.rw = SFC_WRITE; 914 op.sfcmd.b.addrbits = SFC_ADDR_24BITS; 915 916 op.sfctrl.d32 = 0; 917 918 sfc_request(&op, row, p_page_buf, 0); 919 920 if (sfc_nand_dev.read_lines == DATA_LINES_X4 && 921 p_nand_info->feature & FEA_SOFT_QOP_BIT && 922 sfc_get_version() < SFC_VER_3) 923 sfc_nand_rw_preset(); 924 925 sfc_nand_wait_busy(&status, 1000 * 1000); 926 ecc_result = p_nand_info->ecc_status(); 927 928 op.sfcmd.d32 = 0; 929 op.sfcmd.b.cmd = sfc_nand_dev.page_read_cmd; 930 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 931 op.sfcmd.b.dummybits = 8; 932 933 op.sfctrl.d32 = 0; 934 op.sfctrl.b.datalines = sfc_nand_dev.read_lines; 935 op.sfctrl.b.addrbits = 16; 936 937 plane = p_nand_info->plane_per_die == 2 ? ((row >> 6) & 0x1) << 12 : 0; 938 ret = sfc_request(&op, plane | column, p_page_buf, len); 939 rkflash_print_dio("%s %x %x\n", __func__, row, p_page_buf[0]); 940 941 if (ret != SFC_OK) 942 return SFC_NAND_HW_ERROR; 943 944 return ecc_result; 945 } 946 947 u32 sfc_nand_read_page_raw(u8 cs, u32 addr, u32 *p_page_buf) 948 { 949 u32 page_size = SFC_NAND_SECTOR_FULL_SIZE * p_nand_info->sec_per_page; 950 951 return sfc_nand_read(addr, p_page_buf, 0, page_size); 952 } 953 954 u32 sfc_nand_read_page(u8 cs, u32 addr, u32 *p_data, u32 *p_spare) 955 { 956 u32 ret; 957 u32 sec_per_page = p_nand_info->sec_per_page; 958 u32 data_size = sec_per_page * SFC_NAND_SECTOR_SIZE; 959 struct nand_mega_area *meta = &p_nand_info->meta; 960 961 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 962 memcpy(p_data, gp_page_buf, data_size); 963 p_spare[0] = gp_page_buf[(data_size + meta->off0) / 4]; 964 p_spare[1] = gp_page_buf[(data_size + meta->off1) / 4]; 965 966 if (p_nand_info->sec_per_page == 8) { 967 p_spare[2] = gp_page_buf[(data_size + meta->off2) / 4]; 968 p_spare[3] = gp_page_buf[(data_size + meta->off3) / 4]; 969 } 970 971 if (ret == SFC_NAND_HW_ERROR) 972 ret = SFC_NAND_ECC_ERROR; 973 974 if (ret != SFC_NAND_ECC_OK) { 975 rkflash_print_error("%s[0x%x], ret=0x%x\n", __func__, addr, ret); 976 977 if (p_data) 978 rkflash_print_hex("data:", p_data, 4, 8); 979 980 if (p_spare) 981 rkflash_print_hex("spare:", p_spare, 4, 2); 982 } 983 984 return ret; 985 } 986 987 u32 sfc_nand_check_bad_block(u8 cs, u32 addr) 988 { 989 u32 ret; 990 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 991 u32 marker = 0; 992 993 ret = sfc_nand_read(addr, &marker, data_size, 2); 994 995 /* unify with mtd framework */ 996 if (ret == SFC_NAND_ECC_ERROR || (u16)marker != 0xffff) 997 rkflash_print_error("%s page= %x ret= %x spare= %x\n", 998 __func__, addr, ret, marker); 999 1000 /* Original bad block */ 1001 if ((u16)marker != 0xffff) 1002 return true; 1003 1004 return false; 1005 } 1006 1007 u32 sfc_nand_mark_bad_block(u8 cs, u32 addr) 1008 { 1009 u32 ret; 1010 u32 data_size = p_nand_info->sec_per_page * SFC_NAND_SECTOR_SIZE; 1011 1012 ret = sfc_nand_read_page_raw(cs, addr, gp_page_buf); 1013 1014 if (ret) 1015 return SFC_NAND_HW_ERROR; 1016 1017 gp_page_buf[data_size / 4] = 0x0; 1018 ret = sfc_nand_prog_page_raw(cs, addr, gp_page_buf); 1019 1020 if (ret) 1021 return SFC_NAND_HW_ERROR; 1022 1023 return ret; 1024 } 1025 1026 int sfc_nand_read_id(u8 *data) 1027 { 1028 int ret; 1029 struct rk_sfc_op op; 1030 1031 op.sfcmd.d32 = 0; 1032 op.sfcmd.b.cmd = CMD_READ_JEDECID; 1033 op.sfcmd.b.addrbits = SFC_ADDR_XBITS; 1034 1035 op.sfctrl.d32 = 0; 1036 op.sfctrl.b.addrbits = 8; 1037 1038 ret = sfc_request(&op, 0, data, 3); 1039 1040 return ret; 1041 } 1042 1043 /* 1044 * Read the 1st page's 1st byte of a phy_blk 1045 * If not FF, it's bad blk 1046 */ 1047 static int sfc_nand_get_bad_block_list(u16 *table, u32 die) 1048 { 1049 u32 bad_cnt, page; 1050 u32 blk_per_die; 1051 u16 blk; 1052 1053 rkflash_print_info("%s\n", __func__); 1054 1055 bad_cnt = 0; 1056 blk_per_die = p_nand_info->plane_per_die * 1057 p_nand_info->blk_per_plane; 1058 1059 for (blk = 0; blk < blk_per_die; blk++) { 1060 page = (blk + blk_per_die * die) * 1061 p_nand_info->page_per_blk; 1062 1063 if (sfc_nand_check_bad_block(die, page)) { 1064 table[bad_cnt++] = blk; 1065 rkflash_print_error("die[%d], bad_blk[%d]\n", die, blk); 1066 } 1067 } 1068 1069 return (int)bad_cnt; 1070 } 1071 1072 void sfc_nand_ftl_ops_init(void) 1073 { 1074 /* para init */ 1075 g_nand_phy_info.nand_type = 1; 1076 g_nand_phy_info.die_num = 1; 1077 g_nand_phy_info.plane_per_die = p_nand_info->plane_per_die; 1078 g_nand_phy_info.blk_per_plane = p_nand_info->blk_per_plane; 1079 g_nand_phy_info.page_per_blk = p_nand_info->page_per_blk; 1080 g_nand_phy_info.page_per_slc_blk = p_nand_info->page_per_blk; 1081 g_nand_phy_info.byte_per_sec = SFC_NAND_SECTOR_SIZE; 1082 g_nand_phy_info.sec_per_page = p_nand_info->sec_per_page; 1083 g_nand_phy_info.sec_per_blk = p_nand_info->sec_per_page * 1084 p_nand_info->page_per_blk; 1085 g_nand_phy_info.reserved_blk = 8; 1086 g_nand_phy_info.blk_per_die = p_nand_info->plane_per_die * 1087 p_nand_info->blk_per_plane; 1088 g_nand_phy_info.ecc_bits = p_nand_info->max_ecc_bits; 1089 1090 /* driver register */ 1091 g_nand_ops.get_bad_blk_list = sfc_nand_get_bad_block_list; 1092 g_nand_ops.erase_blk = sfc_nand_erase_block; 1093 g_nand_ops.prog_page = sfc_nand_prog_page; 1094 g_nand_ops.read_page = sfc_nand_read_page; 1095 g_nand_ops.bch_sel = NULL; 1096 } 1097 1098 static int sfc_nand_enable_QE(void) 1099 { 1100 int ret = SFC_OK; 1101 u8 status; 1102 1103 ret = sfc_nand_read_feature(0xB0, &status); 1104 1105 if (ret != SFC_OK) 1106 return ret; 1107 1108 if (status & 1) /* is QE bit set */ 1109 return SFC_OK; 1110 1111 status |= 1; 1112 1113 return sfc_nand_write_feature(0xB0, status); 1114 } 1115 1116 u32 sfc_nand_init(void) 1117 { 1118 u8 status, id_byte[8]; 1119 1120 sfc_nand_read_id(id_byte); 1121 rkflash_print_error("sfc_nand id: %x %x %x\n", 1122 id_byte[0], id_byte[1], id_byte[2]); 1123 1124 if (id_byte[0] == 0xFF || id_byte[0] == 0x00) 1125 return (u32)FTL_NO_FLASH; 1126 1127 p_nand_info = sfc_nand_get_info(id_byte); 1128 1129 if (!p_nand_info) { 1130 pr_err("The device not support yet!\n"); 1131 1132 return (u32)FTL_UNSUPPORTED_FLASH; 1133 } 1134 1135 sfc_nand_dev.manufacturer = id_byte[0]; 1136 sfc_nand_dev.mem_type = id_byte[1]; 1137 sfc_nand_dev.capacity = p_nand_info->density; 1138 sfc_nand_dev.block_size = p_nand_info->page_per_blk * p_nand_info->sec_per_page; 1139 sfc_nand_dev.page_size = p_nand_info->sec_per_page; 1140 1141 /* disable block lock */ 1142 sfc_nand_write_feature(0xA0, 0); 1143 sfc_nand_dev.read_lines = DATA_LINES_X1; 1144 sfc_nand_dev.prog_lines = DATA_LINES_X1; 1145 sfc_nand_dev.page_read_cmd = 0x03; 1146 sfc_nand_dev.page_prog_cmd = 0x02; 1147 sfc_nand_dev.recheck_buffer = ftl_malloc(SFC_NAND_PAGE_MAX_SIZE); 1148 if (!sfc_nand_dev.recheck_buffer) { 1149 rkflash_print_error("%s recheck_buffer alloc failed\n", __func__); 1150 return -1; 1151 } 1152 1153 if (p_nand_info->feature & FEA_4BIT_READ) { 1154 if ((p_nand_info->has_qe_bits && sfc_nand_enable_QE() == SFC_OK) || 1155 !p_nand_info->has_qe_bits) { 1156 sfc_nand_dev.read_lines = DATA_LINES_X4; 1157 sfc_nand_dev.page_read_cmd = 0x6b; 1158 } 1159 } 1160 1161 if (p_nand_info->feature & FEA_4BIT_PROG && 1162 sfc_nand_dev.read_lines == DATA_LINES_X4) { 1163 sfc_nand_dev.prog_lines = DATA_LINES_X4; 1164 sfc_nand_dev.page_prog_cmd = 0x32; 1165 } 1166 1167 sfc_nand_read_feature(0xA0, &status); 1168 rkflash_print_info("sfc_nand A0 = 0x%x\n", status); 1169 sfc_nand_read_feature(0xB0, &status); 1170 rkflash_print_info("sfc_nand B0 = 0x%x\n", status); 1171 rkflash_print_info("read_lines = %x\n", sfc_nand_dev.read_lines); 1172 rkflash_print_info("prog_lines = %x\n", sfc_nand_dev.prog_lines); 1173 rkflash_print_info("page_read_cmd = %x\n", sfc_nand_dev.page_read_cmd); 1174 rkflash_print_info("page_prog_cmd = %x\n", sfc_nand_dev.page_prog_cmd); 1175 1176 return SFC_OK; 1177 } 1178 1179 void sfc_nand_deinit(void) 1180 { 1181 /* to-do */ 1182 kfree(sfc_nand_dev.recheck_buffer); 1183 } 1184 1185 struct SFNAND_DEV *sfc_nand_get_private_dev(void) 1186 { 1187 return &sfc_nand_dev; 1188 } 1189 1190