1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _SFC_H 8 #define _SFC_H 9 10 #define SFC_VER_3 0x3 /* ver 3, else ver 1 */ 11 12 #define SFC_MAX_IOSIZE (1024 * 8) /* 8K byte */ 13 #define SFC_EN_INT (0) /* enable interrupt */ 14 #define SFC_EN_DMA (1) /* enable dma */ 15 #define SFC_FIFO_DEPTH (0x10) /* 16 words */ 16 17 /* FIFO watermark */ 18 #define SFC_RX_WMARK (SFC_FIFO_DEPTH) /* RX watermark level */ 19 #define SFC_TX_WMARK (SFC_FIFO_DEPTH) /* TX watermark level */ 20 #define SFC_RX_WMARK_SHIFT (8) 21 #define SFC_TX_WMARK_SHIFT (0) 22 23 /*return value*/ 24 #define SFC_OK (0) 25 #define SFC_ERROR (-1) 26 #define SFC_PARAM_ERR (-2) 27 #define SFC_TX_TIMEOUT (-3) 28 #define SFC_RX_TIMEOUT (-4) 29 #define SFC_WAIT_TIMEOUT (-5) 30 #define SFC_BUSY_TIMEOUT (-6) 31 #define SFC_ECC_FAIL (-7) 32 #define SFC_PROG_FAIL (-8) 33 #define SFC_ERASE_FAIL (-9) 34 35 /* SFC_CMD Register */ 36 #define SFC_ADDR_0BITS (0) 37 #define SFC_ADDR_24BITS (1) 38 #define SFC_ADDR_32BITS (2) 39 #define SFC_ADDR_XBITS (3) 40 41 #define SFC_WRITE (1) 42 #define SFC_READ (0) 43 44 /* SFC_CTRL Register */ 45 #define SFC_1BITS_LINE (0) 46 #define SFC_2BITS_LINE (1) 47 #define SFC_4BITS_LINE (2) 48 49 #define SFC_ENABLE_DMA BIT(14) 50 #define sfc_delay(us) udelay(us) 51 52 #define DMA_INT BIT(7) /* dma interrupt */ 53 #define NSPIERR_INT BIT(6) /* Nspi error interrupt */ 54 #define AHBERR_INT BIT(5) /* Ahb bus error interrupt */ 55 #define FINISH_INT BIT(4) /* Transfer finish interrupt */ 56 #define TXEMPTY_INT BIT(3) /* Tx fifo empty interrupt */ 57 #define TXOF_INT BIT(2) /* Tx fifo overflow interrupt */ 58 #define RXUF_INT BIT(1) /* Rx fifo underflow interrupt */ 59 #define RXFULL_INT BIT(0) /* Rx fifo full interrupt */ 60 61 /* SFC_FSR Register*/ 62 #define SFC_RXFULL BIT(3) /* rx fifo full */ 63 #define SFC_RXEMPTY BIT(2) /* rx fifo empty */ 64 #define SFC_TXEMPTY BIT(1) /* tx fifo empty */ 65 #define SFC_TXFULL BIT(0) /* tx fifo full */ 66 67 /* SFC_RCVR Register */ 68 #define SFC_RESET BIT(0) /* controller reset */ 69 70 /* SFC_SR Register */ 71 /* sfc busy flag. When busy, don't try to set the control register */ 72 #define SFC_BUSY BIT(0) 73 74 /* SFC_DMA_TRIGGER Register */ 75 /* Dma start trigger signal. Auto cleared after write */ 76 #define SFC_DMA_START BIT(0) 77 78 #define SFC_CTRL 0x00 79 #define SFC_IMR 0x04 80 #define SFC_ICLR 0x08 81 #define SFC_FTLR 0x0C 82 #define SFC_RCVR 0x10 83 #define SFC_AX 0x14 84 #define SFC_ABIT 0x18 85 #define SFC_MASKISR 0x1C 86 #define SFC_FSR 0x20 87 #define SFC_SR 0x24 88 #define SFC_RAWISR 0x28 89 #define SFC_VER 0x2C 90 #define SFC_QOP 0x30 91 #define SFC_DMA_TRIGGER 0x80 92 #define SFC_DMA_ADDR 0x84 93 #define SFC_CMD 0x100 94 #define SFC_ADDR 0x104 95 #define SFC_DATA 0x108 96 97 union SFCFSR_DATA { 98 u32 d32; 99 struct { 100 unsigned txempty : 1; 101 unsigned txfull : 1; 102 unsigned rxempty : 1; 103 unsigned rxfull : 1; 104 unsigned reserved7_4 : 4; 105 unsigned txlevel : 5; 106 unsigned reserved15_13 : 3; 107 unsigned rxlevel : 5; 108 unsigned reserved31_21 : 11; 109 } b; 110 }; 111 112 /*------------------------------ Global Typedefs -----------------------------*/ 113 enum SFC_DATA_LINES { 114 DATA_LINES_X1 = 0, 115 DATA_LINES_X2, 116 DATA_LINES_X4 117 }; 118 119 union SFCCTRL_DATA { 120 /* raw register data */ 121 u32 d32; 122 /* register bits */ 123 struct { 124 /* spi mode select */ 125 unsigned mode : 1; 126 /* 127 * Shift in phase selection 128 * 0: shift in the flash data at posedge sclk_out 129 * 1: shift in the flash data at negedge sclk_out 130 */ 131 unsigned sps : 1; 132 unsigned reserved3_2 : 2; 133 /* sclk_idle_level_cycles */ 134 unsigned scic : 4; 135 /* Cmd bits number */ 136 unsigned cmdlines : 2; 137 /* Address bits number */ 138 unsigned addrlines : 2; 139 /* Data bits number */ 140 unsigned datalines : 2; 141 /* this bit is not exit in regiseter, just use for code param */ 142 unsigned enbledma : 1; 143 unsigned reserved15 : 1; 144 unsigned addrbits : 5; 145 unsigned reserved31_21 : 11; 146 } b; 147 }; 148 149 union SFCCMD_DATA { 150 /* raw register data */ 151 u32 d32; 152 /* register bits */ 153 struct { 154 /* Command that will send to Serial Flash */ 155 unsigned cmd : 8; 156 /* Dummy bits number */ 157 unsigned dummybits : 4; 158 /* 0: read, 1: write */ 159 unsigned rw : 1; 160 /* Continuous read mode */ 161 unsigned readmode : 1; 162 /* Address bits number */ 163 unsigned addrbits : 2; 164 /* Transferred bytes number */ 165 unsigned datasize : 14; 166 /* Chip select */ 167 unsigned cs : 2; 168 } b; 169 }; 170 171 int sfc_init(void __iomem *reg_addr); 172 int sfc_request(u32 sfcmd, u32 sfctrl, u32 addr, void *data); 173 u16 sfc_get_version(void); 174 void sfc_clean_irq(void); 175 int rksfc_get_reg_addr(unsigned long *p_sfc_addr); 176 177 #endif 178