1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __NAND_H 8 #define __NAND_H 9 10 #include <asm/io.h> 11 12 #define nandc_writel(v, offs) writel((v), (offs) + nandc_base) 13 #define nandc_readl(offs) readl((offs) + nandc_base) 14 15 #define NANDC_READ 0 16 #define NANDC_WRITE 1 17 18 /* INT ID */ 19 enum NANDC_IRQ_NUM_T { 20 NC_IRQ_DMA = 0, 21 NC_IRQ_FRDY, 22 NC_IRQ_BCHERR, 23 NC_IRQ_BCHFAIL, 24 NC_IRQ_LLP 25 }; 26 27 union FM_CTL_T { 28 u32 d32; 29 struct { 30 unsigned cs : 8; /* bits[0:7] */ 31 unsigned wp : 1; /* bits[8] */ 32 unsigned rdy : 1; /* bits[9] */ 33 unsigned fifo_empty : 1; /* bits[10] */ 34 unsigned reserved11 : 1; /* bits[11] */ 35 unsigned dwidth : 1; /* bits[12] */ 36 unsigned tm : 1; /* bits[13] */ 37 unsigned onficlk_en : 1; /* bits[14] */ 38 unsigned toggle_en : 1; /* bits[15] */ 39 unsigned flash_abort_en : 1; /* bits[16] */ 40 unsigned flash_abort_clear : 1; /* bits[17] */ 41 unsigned reserved18_23 : 6; /* bits[18:23] */ 42 unsigned read_delay : 3; /* bits[24:26] */ 43 unsigned reserved27_31 : 5; /* bits[27:31] */ 44 } V6; 45 }; 46 47 union FM_WAIT_T { 48 u32 d32; 49 struct { 50 unsigned csrw : 5; 51 unsigned rwpw : 6; 52 unsigned rdy : 1; 53 unsigned rwcs : 6; 54 unsigned reserved18_23 : 6; 55 unsigned fmw_dly : 6; 56 unsigned fmw_dly_en : 1; 57 unsigned reserved31_31 : 1; 58 } V6; 59 }; 60 61 union FL_CTL_T { 62 u32 d32; 63 struct { 64 unsigned rst : 1; 65 unsigned rdn : 1; 66 unsigned start : 1; 67 unsigned dma : 1; 68 unsigned st_addr : 1; 69 unsigned tr_count : 2; 70 unsigned rdy_ignore : 1; 71 /* unsigned int_clr : 1; */ 72 /* unsigned int_en : 1; */ 73 unsigned reserved8_9 : 2; 74 unsigned cor_en : 1; 75 unsigned lba_en : 1; 76 unsigned spare_size : 7; 77 unsigned reserved19 : 1; 78 unsigned tr_rdy : 1; 79 unsigned page_size : 1; 80 unsigned page_num : 6; 81 unsigned low_power : 1; 82 unsigned async_tog_mix : 1; 83 unsigned reserved30_31 : 2; 84 } V6; 85 }; 86 87 union BCH_CTL_T { 88 u32 d32; 89 struct { 90 unsigned rst : 1; 91 unsigned reserved : 1; 92 unsigned addr_not_care : 1; 93 unsigned power_down : 1; 94 unsigned bch_mode : 1; /* 0-16bit/1KB, 1-24bit/1KB */ 95 unsigned region : 3; 96 unsigned addr : 8; 97 unsigned bchpage : 1; 98 unsigned reserved17 : 1; 99 unsigned bch_mode1 : 1; 100 unsigned thres : 8; 101 unsigned reserved27_31 : 5; 102 } V6; 103 }; 104 105 union BCH_ST_T { 106 u32 d32; 107 struct { 108 unsigned errf0 : 1; 109 unsigned done0 : 1; 110 unsigned fail0 : 1; 111 unsigned err_bits0 : 5; 112 unsigned err_bits_low0 : 5; 113 unsigned errf1 : 1; 114 unsigned done1 : 1; 115 unsigned fail1 : 1; 116 unsigned err_bits1 : 5; 117 unsigned err_bits_low1 : 5; 118 unsigned rdy : 1; 119 /* unsigned cnt : 1; */ 120 unsigned err_bits0_5 : 1; 121 unsigned err_bits_low0_5 : 1; 122 unsigned err_bits1_5 : 1; 123 unsigned err_bits_low1_5 : 1; 124 unsigned reserved31_31 : 1; 125 } V6; 126 }; 127 128 union MTRANS_CFG_T { 129 u32 d32; 130 struct { 131 unsigned ahb_wr_st : 1; 132 unsigned ahb_wr : 1; 133 unsigned bus_mode : 1; 134 unsigned hsize : 3; 135 unsigned burst : 3; 136 unsigned incr_num : 5; 137 unsigned fl_pwd : 1; 138 unsigned ahb_rst : 1; 139 unsigned reserved16_31 : 16; 140 } V6; 141 }; 142 143 union MTRANS_STAT_T { 144 u32 d32; 145 struct { 146 unsigned bus_err : 16; 147 unsigned mtrans_cnt : 5; 148 unsigned reserved21_31 : 11; 149 } V6; 150 }; 151 152 /* NANDC Registers */ 153 #define NANDC_FMCTL 0x0 154 #define NANDC_FMWAIT 0x4 155 #define NANDC_FLCTL 0x8 156 #define NANDC_BCHCTL 0xc 157 #define NANDC_MTRANS_CFG 0x10 158 #define NANDC_MTRANS_SADDR0 0x14 159 #define NANDC_MTRANS_SADDR1 0x18 160 #define NANDC_MTRANS_STAT 0x1c 161 #define NANDC_DLL_CTL_REG0 0x130 162 #define NANDC_DLL_CTL_REG1 0x134 163 #define NANDC_DLL_OBS_REG0 0x138 164 #define NANDC_RANDMZ_CFG 0x150 165 #define NANDC_EBI_EN 0x154 166 #define NANDC_FMWAIT_SYN 0x158 167 #define NANDC_MTRANS_STAT2 0x15c 168 #define NANDC_NANDC_VER 0x160 169 #define NANDC_LLP_CTL 0x164 170 #define NANDC_LLP_STAT 0x168 171 #define NANDC_INTEN 0x16c 172 #define NANDC_INTCLR 0x170 173 #define NANDC_INTST 0x174 174 #define NANDC_SPARE0 0x200 175 #define NANDC_SPARE1 0x230 176 177 #define NANDC_BCHST(i) ({ \ 178 u32 x = (i); \ 179 4 * x + x < 8 ? 0x20 : 0x520; }) 180 181 #define NANDC_CHIP_DATA(id) (0x800 + (id) * 0x100) 182 #define NANDC_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4) 183 #define NANDC_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8) 184 185 struct MASTER_INFO_T { 186 u32 *page_buf; /* [DATA_LEN]; */ 187 u32 *spare_buf; /* [DATA_LEN / (1024/128)]; */ 188 u32 *page_vir; /* page_buf_vir_addr */ 189 u32 *spare_vir; /* spare_buf_vir_addr */ 190 u32 page_phy; /* page_buf_phy_addr */ 191 u32 spare_phy; /* spare_buf_phy_addr*/ 192 u32 mapped; 193 u32 cnt; 194 }; 195 196 struct CHIP_MAP_INFO_T { 197 u32 *nandc_addr; 198 u32 chip_num; 199 }; 200 201 unsigned long rknandc_dma_map_single(unsigned long ptr, 202 int size, 203 int dir); 204 void rknandc_dma_unmap_single(unsigned long ptr, 205 int size, 206 int dir); 207 208 void nandc_init(void __iomem *nandc_addr); 209 void nandc_flash_cs(u8 chip_sel); 210 void nandc_flash_de_cs(u8 chip_sel); 211 u32 nandc_wait_flash_ready(u8 chip_sel); 212 u32 nandc_delayns(u32 count); 213 u32 nandc_xfer_data(u8 chip_sel, 214 u8 dir, 215 u8 sector_count, 216 u32 *p_data, 217 u32 *p_spare); 218 void nandc_randmz_sel(u8 chip_sel, u32 randmz_seed); 219 void nandc_bch_sel(u8 bits); 220 void nandc_read_not_case_busy_en(u8 en); 221 void nandc_time_cfg(u32 ns); 222 void nandc_clean_irq(void); 223 224 #endif 225