1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef __NAND_H 8 #define __NAND_H 9 10 #include <asm/io.h> 11 12 #define nandc_writel(v, offs) writel((v), (offs) + nandc_base) 13 #define nandc_readl(offs) readl((offs) + nandc_base) 14 15 #define NANDC_READ 0 16 #define NANDC_WRITE 1 17 #define RK3326_NANDC_VER 0x56393030 18 19 /* INT ID */ 20 enum NANDC_IRQ_NUM_T { 21 NC_IRQ_DMA = 0, 22 NC_IRQ_FRDY, 23 NC_IRQ_BCHERR, 24 NC_IRQ_BCHFAIL, 25 NC_IRQ_LLP 26 }; 27 28 enum ENUM_NANDC_BCH_CFG { 29 NC_BCH_70 = 0, 30 NC_BCH_24, 31 NC_BCH_40, 32 NC_BCH_60, 33 }; 34 35 union FM_CTL_T { 36 u32 d32; 37 struct { 38 unsigned cs : 8; /* bits[0:7] */ 39 unsigned wp : 1; /* bits[8] */ 40 unsigned rdy : 1; /* bits[9] */ 41 unsigned fifo_empty : 1; /* bits[10] */ 42 unsigned reserved11 : 1; /* bits[11] */ 43 unsigned dwidth : 1; /* bits[12] */ 44 unsigned tm : 1; /* bits[13] */ 45 unsigned onficlk_en : 1; /* bits[14] */ 46 unsigned toggle_en : 1; /* bits[15] */ 47 unsigned flash_abort_en : 1; /* bits[16] */ 48 unsigned flash_abort_clear : 1; /* bits[17] */ 49 unsigned reserved18_23 : 6; /* bits[18:23] */ 50 unsigned read_delay : 3; /* bits[24:26] */ 51 unsigned reserved27_31 : 5; /* bits[27:31] */ 52 } V6; 53 struct { 54 unsigned cs : 8; 55 unsigned wp : 1; 56 unsigned frdy : 1; 57 unsigned fifo_empth_flash : 1; 58 unsigned reserved11_12 : 2; 59 unsigned tm : 1; 60 unsigned syn_clken : 1; 61 unsigned syn_mode : 1; 62 unsigned flash_abort_en : 1; 63 /*share with flash_abort_stat*/ 64 unsigned flash_abort_clear : 1; 65 unsigned sif_read_delay : 3; 66 unsigned io_mux : 3; 67 unsigned reserved24_31 : 8; 68 } V9; 69 }; 70 71 union FM_WAIT_T { 72 u32 d32; 73 struct { 74 unsigned csrw : 5; 75 unsigned rwpw : 6; 76 unsigned rdy : 1; 77 unsigned rwcs : 6; 78 unsigned reserved18_23 : 6; 79 unsigned fmw_dly : 6; 80 unsigned fmw_dly_en : 1; 81 unsigned reserved31_31 : 1; 82 } V6; 83 struct { 84 unsigned rwcs : 5; 85 unsigned rwpw : 6; 86 unsigned hard_rdy : 1; 87 unsigned csrw : 6; 88 unsigned wait_frdy_dly : 5; 89 unsigned reserved23_23 : 1; 90 unsigned fmw_dly : 6; 91 unsigned fmw_dly_en : 1; 92 unsigned reserved31_31 : 1; 93 } V9; 94 }; 95 96 union FL_CTL_T { 97 u32 d32; 98 struct { 99 unsigned rst : 1; 100 unsigned rdn : 1; 101 unsigned start : 1; 102 unsigned dma : 1; 103 unsigned st_addr : 1; 104 unsigned tr_count : 2; 105 unsigned rdy_ignore : 1; 106 /* unsigned int_clr : 1; */ 107 /* unsigned int_en : 1; */ 108 unsigned reserved8_9 : 2; 109 unsigned cor_en : 1; 110 unsigned lba_en : 1; 111 unsigned spare_size : 7; 112 unsigned reserved19 : 1; 113 unsigned tr_rdy : 1; 114 unsigned page_size : 1; 115 unsigned page_num : 6; 116 unsigned low_power : 1; 117 unsigned async_tog_mix : 1; 118 unsigned reserved30_31 : 2; 119 } V6; 120 struct { 121 unsigned flash_rst : 1; 122 unsigned flash_rdn : 1; 123 unsigned flash_st : 1; 124 unsigned bypass : 1; 125 unsigned st_addr : 1; 126 unsigned tr_count : 2; 127 unsigned flash_st_mod : 1; 128 unsigned not_tran_data : 1; 129 unsigned tran_seed : 1; 130 unsigned cor_able : 1; 131 unsigned lba_en : 1; 132 unsigned lba_spare_sel : 1; 133 unsigned reserved13_18 : 6; 134 unsigned bchst_trans : 1; 135 unsigned tr_rdy : 1; 136 unsigned page_size : 1; 137 unsigned page_num : 6; 138 unsigned low_power : 1; 139 unsigned async_tog_mix : 1; 140 unsigned bypass_fifo_mode : 1; 141 unsigned reserved31_31 : 1; 142 } V9; 143 }; 144 145 union BCH_CTL_T { 146 u32 d32; 147 struct { 148 unsigned rst : 1; 149 unsigned reserved : 1; 150 unsigned addr_not_care : 1; 151 unsigned power_down : 1; 152 unsigned bch_mode : 1; /* 0-16bit/1KB, 1-24bit/1KB */ 153 unsigned region : 3; 154 unsigned addr : 8; 155 unsigned bchpage : 1; 156 unsigned reserved17 : 1; 157 unsigned bch_mode1 : 1; 158 unsigned thres : 8; 159 unsigned reserved27_31 : 5; 160 } V6; 161 struct { 162 unsigned bchrst : 1; 163 unsigned wcnt_clear : 1; 164 unsigned reserved2 : 1; 165 unsigned bchepd : 1; 166 unsigned reserved4_15 : 12; 167 unsigned bchpage : 1; 168 unsigned bchthre : 8; 169 unsigned bchmode : 3; 170 unsigned reserved28_31 : 4; 171 } V9; 172 }; 173 174 union BCH_ST_T { 175 u32 d32; 176 struct { 177 unsigned errf0 : 1; 178 unsigned done0 : 1; 179 unsigned fail0 : 1; 180 unsigned err_bits0 : 5; 181 unsigned err_bits_low0 : 5; 182 unsigned errf1 : 1; 183 unsigned done1 : 1; 184 unsigned fail1 : 1; 185 unsigned err_bits1 : 5; 186 unsigned err_bits_low1 : 5; 187 unsigned rdy : 1; 188 /* unsigned cnt : 1; */ 189 unsigned err_bits0_5 : 1; 190 unsigned err_bits_low0_5 : 1; 191 unsigned err_bits1_5 : 1; 192 unsigned err_bits_low1_5 : 1; 193 unsigned reserved31_31 : 1; 194 } V6; 195 struct { 196 unsigned errf0 : 1; 197 unsigned done0 : 1; 198 unsigned fail0 : 1; 199 unsigned err_bits0 : 7; 200 unsigned all_f_flag0 : 1; 201 unsigned reserved11_15 : 5; 202 unsigned errf1 : 1; 203 unsigned done1 : 1; 204 unsigned fail1 : 1; 205 unsigned err_bits1 : 7; 206 unsigned all_f_flag1 : 1; 207 unsigned reserved27_30 : 4; 208 unsigned bch_ready_flag: 1; 209 } V9; 210 }; 211 212 union MTRANS_CFG_T { 213 u32 d32; 214 struct { 215 unsigned ahb_wr_st : 1; 216 unsigned ahb_wr : 1; 217 unsigned bus_mode : 1; 218 unsigned hsize : 3; 219 unsigned burst : 3; 220 unsigned incr_num : 5; 221 unsigned fl_pwd : 1; 222 unsigned ahb_rst : 1; 223 unsigned reserved16_31 : 16; 224 } V6; 225 struct { 226 unsigned ahb_wr_st : 1; 227 unsigned ahb_wr : 1; 228 unsigned bus_mode : 1; 229 unsigned hsize : 3; 230 unsigned burst : 3; 231 unsigned incr_num : 5; 232 unsigned fl_pwd : 1; 233 unsigned ahb_rst : 1; 234 unsigned redundance_size : 11; 235 unsigned reserved27_31 : 5; 236 } V9; 237 }; 238 239 union MTRANS_STAT_T { 240 u32 d32; 241 struct { 242 unsigned bus_err : 16; 243 unsigned mtrans_cnt : 5; 244 unsigned reserved21_31 : 11; 245 } V6; 246 struct { 247 unsigned bus_err : 16; 248 unsigned mtrans_cnt : 6; 249 unsigned reserved22_31 : 10; 250 } V9; 251 }; 252 253 /* NANDC Registers */ 254 #define NANDC_FMCTL 0x0 255 #define NANDC_FMWAIT 0x4 256 #define NANDC_FLCTL 0x8 257 #define NANDC_BCHCTL 0xc 258 #define NANDC_MTRANS_CFG 0x10 259 #define NANDC_MTRANS_SADDR0 0x14 260 #define NANDC_MTRANS_SADDR1 0x18 261 #define NANDC_MTRANS_STAT 0x1c 262 #define NANDC_DLL_CTL_REG0 0x130 263 #define NANDC_DLL_CTL_REG1 0x134 264 #define NANDC_DLL_OBS_REG0 0x138 265 #define NANDC_RANDMZ_CFG 0x150 266 #define NANDC_EBI_EN 0x154 267 #define NANDC_FMWAIT_SYN 0x158 268 #define NANDC_MTRANS_STAT2 0x15c 269 #define NANDC_NANDC_VER 0x160 270 #define NANDC_LLP_CTL 0x164 271 #define NANDC_LLP_STAT 0x168 272 #define NANDC_INTEN 0x16c 273 #define NANDC_INTCLR 0x170 274 #define NANDC_INTST 0x174 275 #define NANDC_SPARE0 0x200 276 #define NANDC_SPARE1 0x230 277 278 #define NANDC_BCHST(i) ({ \ 279 u32 x = (i); \ 280 4 * x + x < 8 ? 0x20 : 0x520; }) 281 282 #define NANDC_CHIP_DATA(id) (0x800 + (id) * 0x100) 283 #define NANDC_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4) 284 #define NANDC_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8) 285 286 #define NANDC_V9_FMCTL 0x0 287 #define NANDC_V9_FMWAIT 0x4 288 #define NANDC_V9_FLCTL 0x10 289 #define NANDC_V9_BCHCTL 0x20 290 #define NANDC_V9_MTRANS_CFG 0x30 291 #define NANDC_V9_MTRANS_SADDR0 0x34 292 #define NANDC_V9_MTRANS_SADDR1 0x38 293 #define NANDC_V9_MTRANS_STAT 0x40 294 #define NANDC_V9_MTRANS_STAT2 0x44 295 #define NANDC_V9_NANDC_VER 0x80 296 297 #define NANDC_V9_INTEN 0x120 298 #define NANDC_V9_INTCLR 0x124 299 #define NANDC_V9_INTST 0x128 300 #define NANDC_V9_SPARE0 0x200 301 #define NANDC_V9_SPARE1 0x204 302 #define NANDC_V9_RANDMZ_CFG 0x208 303 #define NANDC_V9_BCHST(i) (0x150 + (i) * 4) 304 305 #define NANDC_V9_CHIP_DATA(id) (0x800 + (id) * 0x100) 306 #define NANDC_V9_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4) 307 #define NANDC_V9_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8) 308 309 struct MASTER_INFO_T { 310 u32 *page_buf; /* [DATA_LEN]; */ 311 u32 *spare_buf; /* [DATA_LEN / (1024/128)]; */ 312 u32 *page_vir; /* page_buf_vir_addr */ 313 u32 *spare_vir; /* spare_buf_vir_addr */ 314 u32 page_phy; /* page_buf_phy_addr */ 315 u32 spare_phy; /* spare_buf_phy_addr*/ 316 u32 mapped; 317 u32 cnt; 318 }; 319 320 struct CHIP_MAP_INFO_T { 321 u32 *nandc_addr; 322 u32 chip_num; 323 }; 324 325 unsigned long rknandc_dma_map_single(unsigned long ptr, 326 int size, 327 int dir); 328 void rknandc_dma_unmap_single(unsigned long ptr, 329 int size, 330 int dir); 331 332 void nandc_init(void __iomem *nandc_addr); 333 void nandc_flash_cs(u8 chip_sel); 334 void nandc_flash_de_cs(u8 chip_sel); 335 u32 nandc_wait_flash_ready(u8 chip_sel); 336 u32 nandc_delayns(u32 count); 337 u32 nandc_xfer_data(u8 chip_sel, 338 u8 dir, 339 u8 sector_count, 340 u32 *p_data, 341 u32 *p_spare); 342 void nandc_randmz_sel(u8 chip_sel, u32 randmz_seed); 343 void nandc_bch_sel(u8 bits); 344 void nandc_read_not_case_busy_en(u8 en); 345 void nandc_time_cfg(u32 ns); 346 void nandc_clean_irq(void); 347 u8 nandc_get_version(void); 348 349 #endif 350