1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/delay.h> 9 10 #include "flash.h" 11 #include "flash_com.h" 12 #include "nandc.h" 13 #include "typedef.h" 14 #include "rkflash_debug.h" 15 16 #define FLASH_STRESS_TEST_EN 0 17 18 static u8 id_byte[MAX_FLASH_NUM][8]; 19 static u8 die_cs_index[MAX_FLASH_NUM]; 20 static u8 g_nand_max_die; 21 static u16 g_totle_block; 22 static u8 g_nand_flash_ecc_bits; 23 static u8 g_nand_idb_res_blk_num; 24 25 static struct NAND_PARA_INFO_T nand_para = { 26 2, 27 {0x98, 0xF1, 0, 0, 0, 0}, 28 TOSHIBA, 29 1, 30 4, 31 64, 32 1, 33 1, 34 1024, 35 0x100, 36 LSB_0, 37 RR_NONE, 38 16, 39 40, 40 1, 41 0, 42 BBF_1, 43 MPM_0, 44 {0} 45 }; /* TC58NVG0S3HTA00 */ 46 47 void nandc_flash_reset(u8 cs) 48 { 49 nandc_flash_cs(cs); 50 nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs)); 51 nandc_wait_flash_ready(cs); 52 nandc_flash_de_cs(cs); 53 } 54 55 static void flash_read_id_raw(u8 cs, u8 *buf) 56 { 57 u8 *ptr = (u8 *)buf; 58 59 nandc_flash_reset(cs); 60 nandc_flash_cs(cs); 61 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); 62 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 63 nandc_delayns(200); 64 65 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); 66 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); 67 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); 68 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); 69 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); 70 ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs)); 71 ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs)); 72 ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs)); 73 74 nandc_flash_de_cs(cs); 75 if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF) 76 PRINT_NANDC_E("No.%d FLASH ID:%x %x %x %x %x %x\n", 77 cs + 1, ptr[0], ptr[1], ptr[2], 78 ptr[3], ptr[4], ptr[5]); 79 } 80 81 static void flash_bch_sel(u8 bits) 82 { 83 g_nand_flash_ecc_bits = bits; 84 nandc_bch_sel(bits); 85 } 86 87 static __maybe_unused void flash_timing_cfg(u32 ahb_khz) 88 { 89 nandc_time_cfg(nand_para.access_freq); 90 } 91 92 static void flash_read_cmd(u8 cs, u32 page_addr) 93 { 94 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 95 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 96 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 97 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 98 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 99 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 100 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 101 } 102 103 static void flash_prog_first_cmd(u8 cs, u32 page_addr) 104 { 105 nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs)); 106 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 107 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 108 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 109 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 110 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 111 } 112 113 static void flash_erase_cmd(u8 cs, u32 page_addr) 114 { 115 nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs)); 116 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 117 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 118 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 119 nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 120 } 121 122 static void flash_prog_second_cmd(u8 cs, u32 page_addr) 123 { 124 nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 125 } 126 127 static u32 flash_read_status(u8 cs, u32 page_addr) 128 { 129 nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs)); 130 nandc_delayns(80); 131 132 return nandc_readl(NANDC_CHIP_DATA(cs)); 133 } 134 135 static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr) 136 { 137 nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs)); 138 nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 139 nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs)); 140 nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 141 } 142 143 static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 144 { 145 u32 ret = 0; 146 u32 error_ecc_bits; 147 u32 sec_per_page = nand_para.sec_per_page; 148 149 nandc_wait_flash_ready(cs); 150 nandc_flash_cs(cs); 151 flash_read_cmd(cs, page_addr); 152 nandc_wait_flash_ready(cs); 153 flash_read_random_dataout_cmd(cs, 0); 154 nandc_wait_flash_ready(cs); 155 156 error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page, 157 p_data, p_spare); 158 if (error_ecc_bits > 2) { 159 PRINT_NANDC_E("FlashReadRawPage %x %x error_ecc_bits %d\n", 160 cs, page_addr, error_ecc_bits); 161 if (p_data) 162 PRINT_NANDC_HEX("data:", p_data, 4, 8); 163 if (p_spare) 164 PRINT_NANDC_HEX("spare:", p_spare, 4, 2); 165 } 166 nandc_flash_de_cs(cs); 167 168 if (error_ecc_bits != NAND_STS_ECC_ERR) { 169 if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) 170 ret = NAND_STS_REFRESH; 171 else 172 ret = NAND_STS_OK; 173 } 174 175 return ret; 176 } 177 178 static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 179 { 180 u32 ret; 181 182 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 183 if (ret == NAND_STS_ECC_ERR) 184 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 185 186 return ret; 187 } 188 189 static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 190 { 191 u32 status; 192 u32 sec_per_page = nand_para.sec_per_page; 193 194 nandc_wait_flash_ready(cs); 195 nandc_flash_cs(cs); 196 flash_prog_first_cmd(cs, page_addr); 197 nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare); 198 flash_prog_second_cmd(cs, page_addr); 199 nandc_wait_flash_ready(cs); 200 status = flash_read_status(cs, page_addr); 201 nandc_flash_de_cs(cs); 202 status &= 0x01; 203 if (status) { 204 PRINT_NANDC_I("%s addr=%x status=%x\n", 205 __func__, page_addr, status); 206 } 207 return status; 208 } 209 210 static u32 flash_erase_block(u8 cs, u32 page_addr) 211 { 212 u32 status; 213 214 nandc_wait_flash_ready(cs); 215 nandc_flash_cs(cs); 216 flash_erase_cmd(cs, page_addr); 217 nandc_wait_flash_ready(cs); 218 status = flash_read_status(cs, page_addr); 219 nandc_flash_de_cs(cs); 220 status &= 0x01; 221 if (status) { 222 PRINT_NANDC_I("%s pageadd=%x status=%x\n", 223 __func__, page_addr, status); 224 } 225 return status; 226 } 227 228 static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare) 229 { 230 u32 col = nand_para.sec_per_page << 9; 231 232 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 233 nandc_writel(col, NANDC_CHIP_ADDR(cs)); 234 nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs)); 235 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 236 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 237 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 238 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 239 240 nandc_wait_flash_ready(cs); 241 242 *spare = nandc_readl(NANDC_CHIP_DATA(cs)); 243 } 244 245 /* 246 * Read the 1st page's 1st spare byte of a phy_blk 247 * If not FF, it's bad blk 248 */ 249 static s32 get_bad_blk_list(u16 *table, u32 die) 250 { 251 u16 blk; 252 u32 bad_cnt, page_addr0, page_addr1, page_addr2; 253 u32 blk_per_die; 254 u8 bad_flag0, bad_flag1, bad_flag2; 255 256 bad_cnt = 0; 257 blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane; 258 for (blk = 0; blk < blk_per_die; blk++) { 259 bad_flag0 = 0xFF; 260 bad_flag1 = 0xFF; 261 bad_flag2 = 0xFF; 262 page_addr0 = (blk + blk_per_die * die) * 263 nand_para.page_per_blk + 0; 264 page_addr1 = page_addr0 + 1; 265 page_addr2 = page_addr0 + nand_para.page_per_blk - 1; 266 flash_read_spare(die, page_addr0, &bad_flag0); 267 flash_read_spare(die, page_addr1, &bad_flag1); 268 flash_read_spare(die, page_addr2, &bad_flag2); 269 if (bad_flag0 != 0xFF || 270 bad_flag1 != 0xFF || 271 bad_flag2 != 0xFF) { 272 table[bad_cnt++] = blk; 273 PRINT_NANDC_E("die[%d], bad_blk[%d]\n", die, blk); 274 } 275 } 276 return bad_cnt; 277 } 278 279 #if FLASH_STRESS_TEST_EN 280 281 #define FLASH_PAGE_SIZE 2048 282 #define FLASH_SPARE_SIZE 8 283 284 static u16 bad_blk_list[1024]; 285 static u32 pwrite[FLASH_PAGE_SIZE / 4]; 286 static u32 pread[FLASH_PAGE_SIZE / 4]; 287 static u32 pspare_write[FLASH_SPARE_SIZE / 4]; 288 static u32 pspare_read[FLASH_SPARE_SIZE / 4]; 289 static u32 bad_blk_num; 290 static u32 bad_page_num; 291 292 static void flash_test(void) 293 { 294 u32 i, blk, page, bad_cnt, page_addr; 295 int ret; 296 u32 pages_num = 64; 297 u32 blk_addr = 64; 298 u32 is_bad_blk = 0; 299 300 PRINT_NANDC_E("%s\n", __func__); 301 bad_blk_num = 0; 302 bad_page_num = 0; 303 bad_cnt = get_bad_blk_list(bad_blk_list, 0); 304 305 for (blk = 0; blk < 1024; blk++) { 306 for (i = 0; i < bad_cnt; i++) { 307 if (bad_blk_list[i] == blk) 308 break; 309 } 310 if (i < bad_cnt) 311 continue; 312 is_bad_blk = 0; 313 PRINT_NANDC_E("Flash prog block: %x\n", blk); 314 flash_erase_block(0, blk * blk_addr); 315 for (page = 0; page < pages_num; page++) { 316 page_addr = blk * blk_addr + page; 317 for (i = 0; i < 512; i++) 318 pwrite[i] = (page_addr << 16) + i; 319 pspare_write[0] = pwrite[0] + 0x5AF0; 320 pspare_write[1] = pspare_write[0] + 1; 321 flash_prog_page(0, page_addr, pwrite, pspare_write); 322 memset(pread, 0, 2048); 323 memset(pspare_read, 0, 8); 324 ret = flash_read_page(0, page_addr, pread, 325 pspare_read); 326 if (ret != NAND_STS_OK) 327 is_bad_blk = 1; 328 for (i = 0; i < 512; i++) { 329 if (pwrite[i] != pread[i]) { 330 is_bad_blk = 1; 331 break; 332 } 333 } 334 for (i = 0; i < 2; i++) { 335 if (pspare_write[i] != pspare_read[i]) { 336 is_bad_blk = 1; 337 break; 338 } 339 } 340 if (is_bad_blk) { 341 bad_page_num++; 342 PRINT_NANDC_E("ERR:page %x, ret= %x\n", 343 page_addr, 344 ret); 345 PRINT_NANDC_HEX("data:", pread, 4, 8); 346 PRINT_NANDC_HEX("spare:", pspare_read, 4, 2); 347 } 348 } 349 flash_erase_block(0, blk * blk_addr); 350 if (is_bad_blk) 351 bad_blk_num++; 352 } 353 PRINT_NANDC_E("bad_blk_num = %d, bad_page_num = %d\n", 354 bad_blk_num, bad_page_num); 355 356 PRINT_NANDC_E("Flash Test Finish!!!\n"); 357 while (1) 358 ; 359 } 360 #endif 361 362 static void flash_die_info_init(void) 363 { 364 u32 cs; 365 366 g_nand_max_die = 0; 367 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 368 if (nand_para.nand_id[1] == id_byte[cs][1]) { 369 die_cs_index[g_nand_max_die] = cs; 370 g_nand_max_die++; 371 } 372 } 373 g_totle_block = g_nand_max_die * nand_para.plane_per_die * 374 nand_para.blk_per_plane; 375 } 376 377 static void nandc_flash_print_info(void) 378 { 379 PRINT_NANDC_I("No.0 FLASH ID: %x %x %x %x %x %x\n", 380 nand_para.nand_id[0], 381 nand_para.nand_id[1], 382 nand_para.nand_id[2], 383 nand_para.nand_id[3], 384 nand_para.nand_id[4], 385 nand_para.nand_id[5]); 386 PRINT_NANDC_I("die_per_chip: %x\n", nand_para.die_per_chip); 387 PRINT_NANDC_I("sec_per_page: %x\n", nand_para.sec_per_page); 388 PRINT_NANDC_I("page_per_blk: %x\n", nand_para.page_per_blk); 389 PRINT_NANDC_I("cell: %x\n", nand_para.cell); 390 PRINT_NANDC_I("plane_per_die: %x\n", nand_para.plane_per_die); 391 PRINT_NANDC_I("blk_per_plane: %x\n", nand_para.blk_per_plane); 392 PRINT_NANDC_I("TotleBlock: %x\n", g_totle_block); 393 PRINT_NANDC_I("die gap: %x\n", nand_para.die_gap); 394 PRINT_NANDC_I("lsb_mode: %x\n", nand_para.lsb_mode); 395 PRINT_NANDC_I("read_retry_mode: %x\n", nand_para.read_retry_mode); 396 PRINT_NANDC_I("ecc_bits: %x\n", nand_para.ecc_bits); 397 PRINT_NANDC_I("Use ecc_bits: %x\n", g_nand_flash_ecc_bits); 398 PRINT_NANDC_I("access_freq: %x\n", nand_para.access_freq); 399 PRINT_NANDC_I("opt_mode: %x\n", nand_para.opt_mode); 400 401 PRINT_NANDC_I("Cache read enable: %x\n", 402 nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0); 403 PRINT_NANDC_I("Cache random read enable: %x\n", 404 nand_para.operation_opt & 405 NAND_CACHE_RANDOM_READ_EN ? 1 : 0); 406 PRINT_NANDC_I("Cache prog enable: %x\n", 407 nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0); 408 PRINT_NANDC_I("multi read enable: %x\n", 409 nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0); 410 411 PRINT_NANDC_I("multi prog enable: %x\n", 412 nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0); 413 PRINT_NANDC_I("interleave enable: %x\n", 414 nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0); 415 416 PRINT_NANDC_I("read retry enable: %x\n", 417 nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0); 418 PRINT_NANDC_I("randomizer enable: %x\n", 419 nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0); 420 421 PRINT_NANDC_I("SDR enable: %x\n", 422 nand_para.operation_opt & NAND_SDR_EN ? 1 : 0); 423 PRINT_NANDC_I("ONFI enable: %x\n", 424 nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0); 425 PRINT_NANDC_I("TOGGLE enable: %x\n", 426 nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0); 427 428 PRINT_NANDC_I("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num); 429 } 430 431 static void ftl_flash_init(void) 432 { 433 /* para init */ 434 g_nand_phy_info.nand_type = nand_para.cell; 435 g_nand_phy_info.die_num = nand_para.die_per_chip; 436 g_nand_phy_info.plane_per_die = nand_para.plane_per_die; 437 g_nand_phy_info.blk_per_plane = nand_para.blk_per_plane; 438 g_nand_phy_info.page_per_blk = nand_para.page_per_blk; 439 g_nand_phy_info.page_per_slc_blk = nand_para.page_per_blk / 440 nand_para.cell; 441 g_nand_phy_info.byte_per_sec = 512; 442 g_nand_phy_info.sec_per_page = nand_para.sec_per_page; 443 g_nand_phy_info.sec_per_blk = nand_para.sec_per_page * 444 nand_para.page_per_blk; 445 g_nand_phy_info.reserved_blk = 8; 446 g_nand_phy_info.blk_per_die = nand_para.plane_per_die * 447 nand_para.blk_per_plane; 448 g_nand_phy_info.ecc_bits = nand_para.ecc_bits; 449 450 /* driver register */ 451 g_nand_ops.get_bad_blk_list = get_bad_blk_list; 452 g_nand_ops.erase_blk = flash_erase_block; 453 g_nand_ops.prog_page = flash_prog_page; 454 g_nand_ops.read_page = flash_read_page; 455 } 456 457 u32 nandc_flash_init(void __iomem *nandc_addr) 458 { 459 u32 cs; 460 461 PRINT_NANDC_I("...%s enter...\n", __func__); 462 g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK; 463 464 nandc_init(nandc_addr); 465 466 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 467 flash_read_id_raw(cs, id_byte[cs]); 468 if (cs == 0) { 469 if (id_byte[0][0] == 0xFF || 470 id_byte[0][0] == 0 || 471 id_byte[0][1] == 0xFF) 472 return FTL_NO_FLASH; 473 if (id_byte[0][1] != 0xF1 && 474 id_byte[0][1] != 0xDA && 475 id_byte[0][1] != 0xD1 && 476 id_byte[0][1] != 0x95 && 477 id_byte[0][1] != 0xDC) 478 479 return FTL_UNSUPPORTED_FLASH; 480 } 481 } 482 nand_para.nand_id[1] = id_byte[0][1]; 483 if (id_byte[0][1] == 0xDA) { 484 nand_para.plane_per_die = 2; 485 nand_para.nand_id[1] = 0xDA; 486 } else if (id_byte[0][1] == 0xDC) { 487 nand_para.nand_id[1] = 0xDC; 488 if (id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) { 489 nand_para.plane_per_die = 2; 490 nand_para.sec_per_page = 8; 491 } else { 492 nand_para.plane_per_die = 2; 493 nand_para.blk_per_plane = 2048; 494 } 495 } 496 flash_die_info_init(); 497 flash_bch_sel(nand_para.ecc_bits); 498 nandc_flash_print_info(); 499 /* flash_print_info(); */ 500 ftl_flash_init(); 501 502 #if FLASH_STRESS_TEST_EN 503 flash_test(); 504 #endif 505 506 return 0; 507 } 508 509 void nandc_flash_get_id(u8 cs, void *buf) 510 { 511 memcpy(buf, id_byte[cs], 5); 512 } 513 514 u32 nandc_flash_deinit(void) 515 { 516 return 0; 517 } 518