1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/delay.h> 9 10 #include "flash.h" 11 #include "flash_com.h" 12 #include "nandc.h" 13 #include "rkflash_debug.h" 14 15 #define FLASH_STRESS_TEST_EN 0 16 17 static u8 id_byte[MAX_FLASH_NUM][8]; 18 static u8 die_cs_index[MAX_FLASH_NUM]; 19 static u8 g_nand_max_die; 20 static u16 g_totle_block; 21 static u8 g_nand_flash_ecc_bits; 22 static u8 g_nand_idb_res_blk_num; 23 24 static struct NAND_PARA_INFO_T nand_para = { 25 2, 26 {0x98, 0xF1, 0, 0, 0, 0}, 27 TOSHIBA, 28 1, 29 4, 30 64, 31 1, 32 1, 33 1024, 34 0x100, 35 LSB_0, 36 RR_NONE, 37 16, 38 40, 39 1, 40 0, 41 BBF_1, 42 MPM_0, 43 {0} 44 }; /* TC58NVG0S3HTA00 */ 45 46 void nandc_flash_reset(u8 cs) 47 { 48 nandc_flash_cs(cs); 49 nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs)); 50 nandc_wait_flash_ready(cs); 51 nandc_flash_de_cs(cs); 52 } 53 54 static void flash_read_id_raw(u8 cs, u8 *buf) 55 { 56 u8 *ptr = (u8 *)buf; 57 58 nandc_flash_reset(cs); 59 nandc_flash_cs(cs); 60 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); 61 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 62 nandc_delayns(200); 63 64 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); 65 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); 66 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); 67 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); 68 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); 69 ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs)); 70 ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs)); 71 ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs)); 72 73 nandc_flash_de_cs(cs); 74 if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF) 75 PRINT_NANDC_E("No.%d FLASH ID:%x %x %x %x %x %x\n", 76 cs + 1, ptr[0], ptr[1], ptr[2], 77 ptr[3], ptr[4], ptr[5]); 78 } 79 80 static void flash_bch_sel(u8 bits) 81 { 82 g_nand_flash_ecc_bits = bits; 83 nandc_bch_sel(bits); 84 } 85 86 static void flash_set_sector(u8 num) 87 { 88 nand_para.sec_per_page = num; 89 } 90 91 static __maybe_unused void flash_timing_cfg(u32 ahb_khz) 92 { 93 nandc_time_cfg(nand_para.access_freq); 94 } 95 96 static void flash_read_cmd(u8 cs, u32 page_addr) 97 { 98 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 99 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 100 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 101 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 102 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 103 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 104 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 105 } 106 107 static void flash_prog_first_cmd(u8 cs, u32 page_addr) 108 { 109 nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs)); 110 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 111 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 112 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 113 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 114 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 115 } 116 117 static void flash_erase_cmd(u8 cs, u32 page_addr) 118 { 119 nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs)); 120 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 121 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 122 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 123 nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 124 } 125 126 static void flash_prog_second_cmd(u8 cs, u32 page_addr) 127 { 128 udelay(100); 129 nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 130 } 131 132 static u32 flash_read_status(u8 cs, u32 page_addr) 133 { 134 nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs)); 135 nandc_delayns(80); 136 137 return nandc_readl(NANDC_CHIP_DATA(cs)); 138 } 139 140 static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr) 141 { 142 nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs)); 143 nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 144 nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs)); 145 nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 146 } 147 148 static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 149 { 150 u32 ret = 0; 151 u32 error_ecc_bits; 152 u32 sec_per_page = nand_para.sec_per_page; 153 154 nandc_wait_flash_ready(cs); 155 nandc_flash_cs(cs); 156 flash_read_cmd(cs, page_addr); 157 nandc_wait_flash_ready(cs); 158 flash_read_random_dataout_cmd(cs, 0); 159 nandc_wait_flash_ready(cs); 160 161 error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page, 162 p_data, p_spare); 163 if (error_ecc_bits > 2) { 164 PRINT_NANDC_E("FlashReadRawPage %x %x error_ecc_bits %d\n", 165 cs, page_addr, error_ecc_bits); 166 if (p_data) 167 PRINT_NANDC_HEX("data:", p_data, 4, 8); 168 if (p_spare) 169 PRINT_NANDC_HEX("spare:", p_spare, 4, 2); 170 } 171 nandc_flash_de_cs(cs); 172 173 if (error_ecc_bits != NAND_STS_ECC_ERR) { 174 if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) 175 ret = NAND_STS_REFRESH; 176 else 177 ret = NAND_STS_OK; 178 } 179 180 return ret; 181 } 182 183 static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 184 { 185 u32 ret; 186 187 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 188 if (ret == NAND_STS_ECC_ERR) 189 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 190 191 return ret; 192 } 193 194 static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 195 { 196 u32 status; 197 u32 sec_per_page = nand_para.sec_per_page; 198 199 nandc_wait_flash_ready(cs); 200 nandc_flash_cs(cs); 201 flash_prog_first_cmd(cs, page_addr); 202 nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare); 203 flash_prog_second_cmd(cs, page_addr); 204 nandc_wait_flash_ready(cs); 205 status = flash_read_status(cs, page_addr); 206 nandc_flash_de_cs(cs); 207 status &= 0x01; 208 if (status) { 209 PRINT_NANDC_I("%s addr=%x status=%x\n", 210 __func__, page_addr, status); 211 } 212 return status; 213 } 214 215 static u32 flash_erase_block(u8 cs, u32 page_addr) 216 { 217 u32 status; 218 219 nandc_wait_flash_ready(cs); 220 nandc_flash_cs(cs); 221 flash_erase_cmd(cs, page_addr); 222 nandc_wait_flash_ready(cs); 223 status = flash_read_status(cs, page_addr); 224 nandc_flash_de_cs(cs); 225 status &= 0x01; 226 if (status) { 227 PRINT_NANDC_I("%s pageadd=%x status=%x\n", 228 __func__, page_addr, status); 229 } 230 return status; 231 } 232 233 static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare) 234 { 235 u32 col = nand_para.sec_per_page << 9; 236 237 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 238 nandc_writel(col, NANDC_CHIP_ADDR(cs)); 239 nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs)); 240 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 241 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 242 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 243 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 244 245 nandc_wait_flash_ready(cs); 246 247 *spare = nandc_readl(NANDC_CHIP_DATA(cs)); 248 } 249 250 /* 251 * Read the 1st page's 1st spare byte of a phy_blk 252 * If not FF, it's bad blk 253 */ 254 static s32 get_bad_blk_list(u16 *table, u32 die) 255 { 256 u16 blk; 257 u32 bad_cnt, page_addr0, page_addr1, page_addr2; 258 u32 blk_per_die; 259 u8 bad_flag0, bad_flag1, bad_flag2; 260 261 bad_cnt = 0; 262 blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane; 263 for (blk = 0; blk < blk_per_die; blk++) { 264 bad_flag0 = 0xFF; 265 bad_flag1 = 0xFF; 266 bad_flag2 = 0xFF; 267 page_addr0 = (blk + blk_per_die * die) * 268 nand_para.page_per_blk + 0; 269 page_addr1 = page_addr0 + 1; 270 page_addr2 = page_addr0 + nand_para.page_per_blk - 1; 271 flash_read_spare(die, page_addr0, &bad_flag0); 272 flash_read_spare(die, page_addr1, &bad_flag1); 273 flash_read_spare(die, page_addr2, &bad_flag2); 274 if (bad_flag0 != 0xFF || 275 bad_flag1 != 0xFF || 276 bad_flag2 != 0xFF) { 277 table[bad_cnt++] = blk; 278 PRINT_NANDC_E("die[%d], bad_blk[%d]\n", die, blk); 279 } 280 } 281 return bad_cnt; 282 } 283 284 #if FLASH_STRESS_TEST_EN 285 286 #define FLASH_PAGE_SIZE 2048 287 #define FLASH_SPARE_SIZE 8 288 289 static u16 bad_blk_list[1024]; 290 static u32 pwrite[FLASH_PAGE_SIZE / 4]; 291 static u32 pread[FLASH_PAGE_SIZE / 4]; 292 static u32 pspare_write[FLASH_SPARE_SIZE / 4]; 293 static u32 pspare_read[FLASH_SPARE_SIZE / 4]; 294 static u32 bad_blk_num; 295 static u32 bad_page_num; 296 297 static void flash_test(void) 298 { 299 u32 i, blk, page, bad_cnt, page_addr; 300 int ret; 301 u32 pages_num = 64; 302 u32 blk_addr = 64; 303 u32 is_bad_blk = 0; 304 305 PRINT_NANDC_E("%s\n", __func__); 306 bad_blk_num = 0; 307 bad_page_num = 0; 308 bad_cnt = get_bad_blk_list(bad_blk_list, 0); 309 310 for (blk = 0; blk < 1024; blk++) { 311 for (i = 0; i < bad_cnt; i++) { 312 if (bad_blk_list[i] == blk) 313 break; 314 } 315 if (i < bad_cnt) 316 continue; 317 is_bad_blk = 0; 318 PRINT_NANDC_E("Flash prog block: %x\n", blk); 319 flash_erase_block(0, blk * blk_addr); 320 for (page = 0; page < pages_num; page++) { 321 page_addr = blk * blk_addr + page; 322 for (i = 0; i < 512; i++) 323 pwrite[i] = (page_addr << 16) + i; 324 pspare_write[0] = pwrite[0] + 0x5AF0; 325 pspare_write[1] = pspare_write[0] + 1; 326 flash_prog_page(0, page_addr, pwrite, pspare_write); 327 memset(pread, 0, 2048); 328 memset(pspare_read, 0, 8); 329 ret = flash_read_page(0, page_addr, pread, 330 pspare_read); 331 if (ret != NAND_STS_OK) 332 is_bad_blk = 1; 333 for (i = 0; i < 512; i++) { 334 if (pwrite[i] != pread[i]) { 335 is_bad_blk = 1; 336 break; 337 } 338 } 339 for (i = 0; i < 2; i++) { 340 if (pspare_write[i] != pspare_read[i]) { 341 is_bad_blk = 1; 342 break; 343 } 344 } 345 if (is_bad_blk) { 346 bad_page_num++; 347 PRINT_NANDC_E("ERR:page %x, ret= %x\n", 348 page_addr, 349 ret); 350 PRINT_NANDC_HEX("data:", pread, 4, 8); 351 PRINT_NANDC_HEX("spare:", pspare_read, 4, 2); 352 } 353 } 354 flash_erase_block(0, blk * blk_addr); 355 if (is_bad_blk) 356 bad_blk_num++; 357 } 358 PRINT_NANDC_E("bad_blk_num = %d, bad_page_num = %d\n", 359 bad_blk_num, bad_page_num); 360 361 PRINT_NANDC_E("Flash Test Finish!!!\n"); 362 while (1) 363 ; 364 } 365 #endif 366 367 static void flash_die_info_init(void) 368 { 369 u32 cs; 370 371 g_nand_max_die = 0; 372 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 373 if (nand_para.nand_id[1] == id_byte[cs][1]) { 374 die_cs_index[g_nand_max_die] = cs; 375 g_nand_max_die++; 376 } 377 } 378 g_totle_block = g_nand_max_die * nand_para.plane_per_die * 379 nand_para.blk_per_plane; 380 } 381 382 static void nandc_flash_print_info(void) 383 { 384 PRINT_NANDC_I("No.0 FLASH ID: %x %x %x %x %x %x\n", 385 nand_para.nand_id[0], 386 nand_para.nand_id[1], 387 nand_para.nand_id[2], 388 nand_para.nand_id[3], 389 nand_para.nand_id[4], 390 nand_para.nand_id[5]); 391 PRINT_NANDC_I("die_per_chip: %x\n", nand_para.die_per_chip); 392 PRINT_NANDC_I("sec_per_page: %x\n", nand_para.sec_per_page); 393 PRINT_NANDC_I("page_per_blk: %x\n", nand_para.page_per_blk); 394 PRINT_NANDC_I("cell: %x\n", nand_para.cell); 395 PRINT_NANDC_I("plane_per_die: %x\n", nand_para.plane_per_die); 396 PRINT_NANDC_I("blk_per_plane: %x\n", nand_para.blk_per_plane); 397 PRINT_NANDC_I("TotleBlock: %x\n", g_totle_block); 398 PRINT_NANDC_I("die gap: %x\n", nand_para.die_gap); 399 PRINT_NANDC_I("lsb_mode: %x\n", nand_para.lsb_mode); 400 PRINT_NANDC_I("read_retry_mode: %x\n", nand_para.read_retry_mode); 401 PRINT_NANDC_I("ecc_bits: %x\n", nand_para.ecc_bits); 402 PRINT_NANDC_I("Use ecc_bits: %x\n", g_nand_flash_ecc_bits); 403 PRINT_NANDC_I("access_freq: %x\n", nand_para.access_freq); 404 PRINT_NANDC_I("opt_mode: %x\n", nand_para.opt_mode); 405 406 PRINT_NANDC_I("Cache read enable: %x\n", 407 nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0); 408 PRINT_NANDC_I("Cache random read enable: %x\n", 409 nand_para.operation_opt & 410 NAND_CACHE_RANDOM_READ_EN ? 1 : 0); 411 PRINT_NANDC_I("Cache prog enable: %x\n", 412 nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0); 413 PRINT_NANDC_I("multi read enable: %x\n", 414 nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0); 415 416 PRINT_NANDC_I("multi prog enable: %x\n", 417 nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0); 418 PRINT_NANDC_I("interleave enable: %x\n", 419 nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0); 420 421 PRINT_NANDC_I("read retry enable: %x\n", 422 nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0); 423 PRINT_NANDC_I("randomizer enable: %x\n", 424 nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0); 425 426 PRINT_NANDC_I("SDR enable: %x\n", 427 nand_para.operation_opt & NAND_SDR_EN ? 1 : 0); 428 PRINT_NANDC_I("ONFI enable: %x\n", 429 nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0); 430 PRINT_NANDC_I("TOGGLE enable: %x\n", 431 nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0); 432 433 PRINT_NANDC_I("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num); 434 } 435 436 static void ftl_flash_init(void) 437 { 438 u8 nandc_ver = nandc_get_version(); 439 440 /* para init */ 441 g_nand_phy_info.nand_type = nand_para.cell; 442 g_nand_phy_info.die_num = nand_para.die_per_chip; 443 g_nand_phy_info.plane_per_die = nand_para.plane_per_die; 444 g_nand_phy_info.blk_per_plane = nand_para.blk_per_plane; 445 g_nand_phy_info.page_per_blk = nand_para.page_per_blk; 446 g_nand_phy_info.page_per_slc_blk = nand_para.page_per_blk / 447 nand_para.cell; 448 g_nand_phy_info.byte_per_sec = 512; 449 g_nand_phy_info.sec_per_page = nand_para.sec_per_page; 450 g_nand_phy_info.sec_per_blk = nand_para.sec_per_page * 451 nand_para.page_per_blk; 452 g_nand_phy_info.reserved_blk = 8; 453 g_nand_phy_info.blk_per_die = nand_para.plane_per_die * 454 nand_para.blk_per_plane; 455 g_nand_phy_info.ecc_bits = nand_para.ecc_bits; 456 457 /* driver register */ 458 g_nand_ops.get_bad_blk_list = get_bad_blk_list; 459 g_nand_ops.erase_blk = flash_erase_block; 460 g_nand_ops.prog_page = flash_prog_page; 461 g_nand_ops.read_page = flash_read_page; 462 if (nandc_ver == 9) { 463 g_nand_ops.bch_sel = flash_bch_sel; 464 g_nand_ops.set_sec_num = flash_set_sector; 465 } 466 } 467 468 u32 nandc_flash_init(void __iomem *nandc_addr) 469 { 470 u32 cs; 471 472 PRINT_NANDC_I("...%s enter...\n", __func__); 473 g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK; 474 475 nandc_init(nandc_addr); 476 477 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 478 flash_read_id_raw(cs, id_byte[cs]); 479 if (cs == 0) { 480 if (id_byte[0][0] == 0xFF || 481 id_byte[0][0] == 0 || 482 id_byte[0][1] == 0xFF) 483 return FTL_NO_FLASH; 484 if (id_byte[0][1] != 0xF1 && 485 id_byte[0][1] != 0xDA && 486 id_byte[0][1] != 0xD1 && 487 id_byte[0][1] != 0x95 && 488 id_byte[0][1] != 0xDC) 489 490 return FTL_UNSUPPORTED_FLASH; 491 } 492 } 493 nand_para.nand_id[1] = id_byte[0][1]; 494 if (id_byte[0][1] == 0xDA) { 495 nand_para.plane_per_die = 2; 496 nand_para.nand_id[1] = 0xDA; 497 } else if (id_byte[0][1] == 0xDC) { 498 nand_para.nand_id[1] = 0xDC; 499 if (id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) { 500 nand_para.plane_per_die = 2; 501 nand_para.sec_per_page = 8; 502 } else if (id_byte[0][0] == 0x98 && id_byte[0][3] == 0x26) { 503 nand_para.blk_per_plane = 2048; 504 nand_para.sec_per_page = 8; 505 } else { 506 nand_para.plane_per_die = 2; 507 nand_para.blk_per_plane = 2048; 508 } 509 } 510 flash_die_info_init(); 511 flash_bch_sel(nand_para.ecc_bits); 512 nandc_flash_print_info(); 513 /* flash_print_info(); */ 514 ftl_flash_init(); 515 516 #if FLASH_STRESS_TEST_EN 517 flash_test(); 518 #endif 519 520 return 0; 521 } 522 523 void nandc_flash_get_id(u8 cs, void *buf) 524 { 525 memcpy(buf, id_byte[cs], 5); 526 } 527 528 u32 nandc_flash_deinit(void) 529 { 530 return 0; 531 } 532