1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/delay.h> 9 10 #include "flash.h" 11 #include "flash_com.h" 12 #include "nandc.h" 13 #include "rkflash_debug.h" 14 15 #define FLASH_STRESS_TEST_EN 0 16 17 static u8 id_byte[MAX_FLASH_NUM][8]; 18 static u8 die_cs_index[MAX_FLASH_NUM]; 19 static u8 g_nand_max_die; 20 static u16 g_totle_block; 21 static u8 g_nand_flash_ecc_bits; 22 static u8 g_nand_idb_res_blk_num; 23 24 static struct NAND_PARA_INFO_T nand_para = { 25 2, 26 {0x98, 0xF1, 0, 0, 0, 0}, 27 TOSHIBA, 28 1, 29 4, 30 64, 31 1, 32 1, 33 1024, 34 0x100, 35 LSB_0, 36 RR_NONE, 37 16, 38 40, 39 1, 40 0, 41 BBF_1, 42 MPM_0, 43 {0} 44 }; /* TC58NVG0S3HTA00 */ 45 46 void nandc_flash_reset(u8 cs) 47 { 48 nandc_flash_cs(cs); 49 nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs)); 50 nandc_wait_flash_ready(cs); 51 nandc_flash_de_cs(cs); 52 } 53 54 static void flash_read_id_raw(u8 cs, u8 *buf) 55 { 56 u8 *ptr = (u8 *)buf; 57 58 nandc_flash_reset(cs); 59 nandc_flash_cs(cs); 60 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); 61 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 62 nandc_delayns(200); 63 64 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); 65 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); 66 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); 67 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); 68 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); 69 ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs)); 70 ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs)); 71 ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs)); 72 73 nandc_flash_de_cs(cs); 74 if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF) 75 PRINT_NANDC_E("No.%d FLASH ID:%x %x %x %x %x %x\n", 76 cs + 1, ptr[0], ptr[1], ptr[2], 77 ptr[3], ptr[4], ptr[5]); 78 } 79 80 static void flash_bch_sel(u8 bits) 81 { 82 g_nand_flash_ecc_bits = bits; 83 nandc_bch_sel(bits); 84 } 85 86 static void flash_set_sector(u8 num) 87 { 88 nand_para.sec_per_page = num; 89 } 90 91 static __maybe_unused void flash_timing_cfg(u32 ahb_khz) 92 { 93 nandc_time_cfg(nand_para.access_freq); 94 } 95 96 static void flash_read_cmd(u8 cs, u32 page_addr) 97 { 98 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 99 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 100 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 101 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 102 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 103 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 104 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 105 } 106 107 static void flash_prog_first_cmd(u8 cs, u32 page_addr) 108 { 109 nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs)); 110 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 111 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 112 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 113 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 114 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 115 } 116 117 static void flash_erase_cmd(u8 cs, u32 page_addr) 118 { 119 nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs)); 120 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 121 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 122 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 123 nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 124 } 125 126 static void flash_prog_second_cmd(u8 cs, u32 page_addr) 127 { 128 nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 129 } 130 131 static u32 flash_read_status(u8 cs, u32 page_addr) 132 { 133 nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs)); 134 nandc_delayns(80); 135 136 return nandc_readl(NANDC_CHIP_DATA(cs)); 137 } 138 139 static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr) 140 { 141 nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs)); 142 nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 143 nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs)); 144 nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 145 } 146 147 static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 148 { 149 u32 ret = 0; 150 u32 error_ecc_bits; 151 u32 sec_per_page = nand_para.sec_per_page; 152 153 nandc_wait_flash_ready(cs); 154 nandc_flash_cs(cs); 155 flash_read_cmd(cs, page_addr); 156 nandc_wait_flash_ready(cs); 157 flash_read_random_dataout_cmd(cs, 0); 158 nandc_wait_flash_ready(cs); 159 160 error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page, 161 p_data, p_spare); 162 if (error_ecc_bits > 2) { 163 PRINT_NANDC_E("FlashReadRawPage %x %x error_ecc_bits %d\n", 164 cs, page_addr, error_ecc_bits); 165 if (p_data) 166 PRINT_NANDC_HEX("data:", p_data, 4, 8); 167 if (p_spare) 168 PRINT_NANDC_HEX("spare:", p_spare, 4, 2); 169 } 170 nandc_flash_de_cs(cs); 171 172 if (error_ecc_bits != NAND_STS_ECC_ERR) { 173 if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) 174 ret = NAND_STS_REFRESH; 175 else 176 ret = NAND_STS_OK; 177 } 178 179 return ret; 180 } 181 182 static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 183 { 184 u32 ret; 185 186 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 187 if (ret == NAND_STS_ECC_ERR) 188 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 189 190 return ret; 191 } 192 193 static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 194 { 195 u32 status; 196 u32 sec_per_page = nand_para.sec_per_page; 197 198 nandc_wait_flash_ready(cs); 199 nandc_flash_cs(cs); 200 flash_prog_first_cmd(cs, page_addr); 201 nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare); 202 flash_prog_second_cmd(cs, page_addr); 203 nandc_wait_flash_ready(cs); 204 status = flash_read_status(cs, page_addr); 205 nandc_flash_de_cs(cs); 206 status &= 0x01; 207 if (status) { 208 PRINT_NANDC_I("%s addr=%x status=%x\n", 209 __func__, page_addr, status); 210 } 211 return status; 212 } 213 214 static u32 flash_erase_block(u8 cs, u32 page_addr) 215 { 216 u32 status; 217 218 nandc_wait_flash_ready(cs); 219 nandc_flash_cs(cs); 220 flash_erase_cmd(cs, page_addr); 221 nandc_wait_flash_ready(cs); 222 status = flash_read_status(cs, page_addr); 223 nandc_flash_de_cs(cs); 224 status &= 0x01; 225 if (status) { 226 PRINT_NANDC_I("%s pageadd=%x status=%x\n", 227 __func__, page_addr, status); 228 } 229 return status; 230 } 231 232 static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare) 233 { 234 u32 col = nand_para.sec_per_page << 9; 235 236 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 237 nandc_writel(col, NANDC_CHIP_ADDR(cs)); 238 nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs)); 239 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 240 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 241 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 242 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 243 244 nandc_wait_flash_ready(cs); 245 246 *spare = nandc_readl(NANDC_CHIP_DATA(cs)); 247 } 248 249 /* 250 * Read the 1st page's 1st spare byte of a phy_blk 251 * If not FF, it's bad blk 252 */ 253 static s32 get_bad_blk_list(u16 *table, u32 die) 254 { 255 u16 blk; 256 u32 bad_cnt, page_addr0, page_addr1, page_addr2; 257 u32 blk_per_die; 258 u8 bad_flag0, bad_flag1, bad_flag2; 259 260 bad_cnt = 0; 261 blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane; 262 for (blk = 0; blk < blk_per_die; blk++) { 263 bad_flag0 = 0xFF; 264 bad_flag1 = 0xFF; 265 bad_flag2 = 0xFF; 266 page_addr0 = (blk + blk_per_die * die) * 267 nand_para.page_per_blk + 0; 268 page_addr1 = page_addr0 + 1; 269 page_addr2 = page_addr0 + nand_para.page_per_blk - 1; 270 flash_read_spare(die, page_addr0, &bad_flag0); 271 flash_read_spare(die, page_addr1, &bad_flag1); 272 flash_read_spare(die, page_addr2, &bad_flag2); 273 if (bad_flag0 != 0xFF || 274 bad_flag1 != 0xFF || 275 bad_flag2 != 0xFF) { 276 table[bad_cnt++] = blk; 277 PRINT_NANDC_E("die[%d], bad_blk[%d]\n", die, blk); 278 } 279 } 280 return bad_cnt; 281 } 282 283 #if FLASH_STRESS_TEST_EN 284 285 #define FLASH_PAGE_SIZE 2048 286 #define FLASH_SPARE_SIZE 8 287 288 static u16 bad_blk_list[1024]; 289 static u32 pwrite[FLASH_PAGE_SIZE / 4]; 290 static u32 pread[FLASH_PAGE_SIZE / 4]; 291 static u32 pspare_write[FLASH_SPARE_SIZE / 4]; 292 static u32 pspare_read[FLASH_SPARE_SIZE / 4]; 293 static u32 bad_blk_num; 294 static u32 bad_page_num; 295 296 static void flash_test(void) 297 { 298 u32 i, blk, page, bad_cnt, page_addr; 299 int ret; 300 u32 pages_num = 64; 301 u32 blk_addr = 64; 302 u32 is_bad_blk = 0; 303 304 PRINT_NANDC_E("%s\n", __func__); 305 bad_blk_num = 0; 306 bad_page_num = 0; 307 bad_cnt = get_bad_blk_list(bad_blk_list, 0); 308 309 for (blk = 0; blk < 1024; blk++) { 310 for (i = 0; i < bad_cnt; i++) { 311 if (bad_blk_list[i] == blk) 312 break; 313 } 314 if (i < bad_cnt) 315 continue; 316 is_bad_blk = 0; 317 PRINT_NANDC_E("Flash prog block: %x\n", blk); 318 flash_erase_block(0, blk * blk_addr); 319 for (page = 0; page < pages_num; page++) { 320 page_addr = blk * blk_addr + page; 321 for (i = 0; i < 512; i++) 322 pwrite[i] = (page_addr << 16) + i; 323 pspare_write[0] = pwrite[0] + 0x5AF0; 324 pspare_write[1] = pspare_write[0] + 1; 325 flash_prog_page(0, page_addr, pwrite, pspare_write); 326 memset(pread, 0, 2048); 327 memset(pspare_read, 0, 8); 328 ret = flash_read_page(0, page_addr, pread, 329 pspare_read); 330 if (ret != NAND_STS_OK) 331 is_bad_blk = 1; 332 for (i = 0; i < 512; i++) { 333 if (pwrite[i] != pread[i]) { 334 is_bad_blk = 1; 335 break; 336 } 337 } 338 for (i = 0; i < 2; i++) { 339 if (pspare_write[i] != pspare_read[i]) { 340 is_bad_blk = 1; 341 break; 342 } 343 } 344 if (is_bad_blk) { 345 bad_page_num++; 346 PRINT_NANDC_E("ERR:page %x, ret= %x\n", 347 page_addr, 348 ret); 349 PRINT_NANDC_HEX("data:", pread, 4, 8); 350 PRINT_NANDC_HEX("spare:", pspare_read, 4, 2); 351 } 352 } 353 flash_erase_block(0, blk * blk_addr); 354 if (is_bad_blk) 355 bad_blk_num++; 356 } 357 PRINT_NANDC_E("bad_blk_num = %d, bad_page_num = %d\n", 358 bad_blk_num, bad_page_num); 359 360 PRINT_NANDC_E("Flash Test Finish!!!\n"); 361 while (1) 362 ; 363 } 364 #endif 365 366 static void flash_die_info_init(void) 367 { 368 u32 cs; 369 370 g_nand_max_die = 0; 371 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 372 if (nand_para.nand_id[1] == id_byte[cs][1]) { 373 die_cs_index[g_nand_max_die] = cs; 374 g_nand_max_die++; 375 } 376 } 377 g_totle_block = g_nand_max_die * nand_para.plane_per_die * 378 nand_para.blk_per_plane; 379 } 380 381 static void nandc_flash_print_info(void) 382 { 383 PRINT_NANDC_I("No.0 FLASH ID: %x %x %x %x %x %x\n", 384 nand_para.nand_id[0], 385 nand_para.nand_id[1], 386 nand_para.nand_id[2], 387 nand_para.nand_id[3], 388 nand_para.nand_id[4], 389 nand_para.nand_id[5]); 390 PRINT_NANDC_I("die_per_chip: %x\n", nand_para.die_per_chip); 391 PRINT_NANDC_I("sec_per_page: %x\n", nand_para.sec_per_page); 392 PRINT_NANDC_I("page_per_blk: %x\n", nand_para.page_per_blk); 393 PRINT_NANDC_I("cell: %x\n", nand_para.cell); 394 PRINT_NANDC_I("plane_per_die: %x\n", nand_para.plane_per_die); 395 PRINT_NANDC_I("blk_per_plane: %x\n", nand_para.blk_per_plane); 396 PRINT_NANDC_I("TotleBlock: %x\n", g_totle_block); 397 PRINT_NANDC_I("die gap: %x\n", nand_para.die_gap); 398 PRINT_NANDC_I("lsb_mode: %x\n", nand_para.lsb_mode); 399 PRINT_NANDC_I("read_retry_mode: %x\n", nand_para.read_retry_mode); 400 PRINT_NANDC_I("ecc_bits: %x\n", nand_para.ecc_bits); 401 PRINT_NANDC_I("Use ecc_bits: %x\n", g_nand_flash_ecc_bits); 402 PRINT_NANDC_I("access_freq: %x\n", nand_para.access_freq); 403 PRINT_NANDC_I("opt_mode: %x\n", nand_para.opt_mode); 404 405 PRINT_NANDC_I("Cache read enable: %x\n", 406 nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0); 407 PRINT_NANDC_I("Cache random read enable: %x\n", 408 nand_para.operation_opt & 409 NAND_CACHE_RANDOM_READ_EN ? 1 : 0); 410 PRINT_NANDC_I("Cache prog enable: %x\n", 411 nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0); 412 PRINT_NANDC_I("multi read enable: %x\n", 413 nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0); 414 415 PRINT_NANDC_I("multi prog enable: %x\n", 416 nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0); 417 PRINT_NANDC_I("interleave enable: %x\n", 418 nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0); 419 420 PRINT_NANDC_I("read retry enable: %x\n", 421 nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0); 422 PRINT_NANDC_I("randomizer enable: %x\n", 423 nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0); 424 425 PRINT_NANDC_I("SDR enable: %x\n", 426 nand_para.operation_opt & NAND_SDR_EN ? 1 : 0); 427 PRINT_NANDC_I("ONFI enable: %x\n", 428 nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0); 429 PRINT_NANDC_I("TOGGLE enable: %x\n", 430 nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0); 431 432 PRINT_NANDC_I("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num); 433 } 434 435 static void ftl_flash_init(void) 436 { 437 u8 nandc_ver = nandc_get_version(); 438 439 /* para init */ 440 g_nand_phy_info.nand_type = nand_para.cell; 441 g_nand_phy_info.die_num = nand_para.die_per_chip; 442 g_nand_phy_info.plane_per_die = nand_para.plane_per_die; 443 g_nand_phy_info.blk_per_plane = nand_para.blk_per_plane; 444 g_nand_phy_info.page_per_blk = nand_para.page_per_blk; 445 g_nand_phy_info.page_per_slc_blk = nand_para.page_per_blk / 446 nand_para.cell; 447 g_nand_phy_info.byte_per_sec = 512; 448 g_nand_phy_info.sec_per_page = nand_para.sec_per_page; 449 g_nand_phy_info.sec_per_blk = nand_para.sec_per_page * 450 nand_para.page_per_blk; 451 g_nand_phy_info.reserved_blk = 8; 452 g_nand_phy_info.blk_per_die = nand_para.plane_per_die * 453 nand_para.blk_per_plane; 454 g_nand_phy_info.ecc_bits = nand_para.ecc_bits; 455 456 /* driver register */ 457 g_nand_ops.get_bad_blk_list = get_bad_blk_list; 458 g_nand_ops.erase_blk = flash_erase_block; 459 g_nand_ops.prog_page = flash_prog_page; 460 g_nand_ops.read_page = flash_read_page; 461 if (nandc_ver == 9) { 462 g_nand_ops.bch_sel = flash_bch_sel; 463 g_nand_ops.set_sec_num = flash_set_sector; 464 } 465 } 466 467 u32 nandc_flash_init(void __iomem *nandc_addr) 468 { 469 u32 cs; 470 471 PRINT_NANDC_I("...%s enter...\n", __func__); 472 g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK; 473 474 nandc_init(nandc_addr); 475 476 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 477 flash_read_id_raw(cs, id_byte[cs]); 478 if (cs == 0) { 479 if (id_byte[0][0] == 0xFF || 480 id_byte[0][0] == 0 || 481 id_byte[0][1] == 0xFF) 482 return FTL_NO_FLASH; 483 if (id_byte[0][1] != 0xF1 && 484 id_byte[0][1] != 0xDA && 485 id_byte[0][1] != 0xD1 && 486 id_byte[0][1] != 0x95 && 487 id_byte[0][1] != 0xDC) 488 489 return FTL_UNSUPPORTED_FLASH; 490 } 491 } 492 nand_para.nand_id[1] = id_byte[0][1]; 493 if (id_byte[0][1] == 0xDA) { 494 nand_para.plane_per_die = 2; 495 nand_para.nand_id[1] = 0xDA; 496 } else if (id_byte[0][1] == 0xDC) { 497 nand_para.nand_id[1] = 0xDC; 498 if (id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) { 499 nand_para.plane_per_die = 2; 500 nand_para.sec_per_page = 8; 501 } else if (id_byte[0][0] == 0x98 && id_byte[0][3] == 0x26) { 502 nand_para.blk_per_plane = 2048; 503 nand_para.sec_per_page = 8; 504 } else { 505 nand_para.plane_per_die = 2; 506 nand_para.blk_per_plane = 2048; 507 } 508 } 509 flash_die_info_init(); 510 flash_bch_sel(nand_para.ecc_bits); 511 nandc_flash_print_info(); 512 /* flash_print_info(); */ 513 ftl_flash_init(); 514 515 #if FLASH_STRESS_TEST_EN 516 flash_test(); 517 #endif 518 519 return 0; 520 } 521 522 void nandc_flash_get_id(u8 cs, void *buf) 523 { 524 memcpy(buf, id_byte[cs], 5); 525 } 526 527 u32 nandc_flash_deinit(void) 528 { 529 return 0; 530 } 531