1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/delay.h> 9 10 #include "flash.h" 11 #include "flash_com.h" 12 #include "nandc.h" 13 #include "rkflash_debug.h" 14 15 #define FLASH_STRESS_TEST_EN 0 16 17 static u8 id_byte[MAX_FLASH_NUM][8]; 18 static u8 die_cs_index[MAX_FLASH_NUM]; 19 static u8 g_nand_max_die; 20 static u16 g_totle_block; 21 static u8 g_nand_flash_ecc_bits; 22 static u8 g_nand_idb_res_blk_num; 23 24 static struct NAND_PARA_INFO_T nand_para = { 25 2, 26 {0x98, 0xF1, 0, 0, 0, 0}, 27 TOSHIBA, 28 1, 29 4, 30 64, 31 1, 32 1, 33 1024, 34 0x100, 35 LSB_0, 36 RR_NONE, 37 16, 38 40, 39 1, 40 0, 41 BBF_1, 42 MPM_0, 43 {0} 44 }; /* TC58NVG0S3HTA00 */ 45 46 void nandc_flash_reset(u8 cs) 47 { 48 nandc_flash_cs(cs); 49 nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs)); 50 nandc_wait_flash_ready(cs); 51 nandc_flash_de_cs(cs); 52 } 53 54 static void flash_read_id_raw(u8 cs, u8 *buf) 55 { 56 u8 *ptr = (u8 *)buf; 57 58 nandc_flash_reset(cs); 59 nandc_flash_cs(cs); 60 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); 61 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 62 nandc_delayns(200); 63 64 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); 65 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); 66 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); 67 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); 68 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); 69 ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs)); 70 ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs)); 71 ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs)); 72 73 nandc_flash_de_cs(cs); 74 if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF) 75 PRINT_NANDC_E("No.%d FLASH ID:%x %x %x %x %x %x\n", 76 cs + 1, ptr[0], ptr[1], ptr[2], 77 ptr[3], ptr[4], ptr[5]); 78 } 79 80 static void flash_bch_sel(u8 bits) 81 { 82 g_nand_flash_ecc_bits = bits; 83 nandc_bch_sel(bits); 84 } 85 86 static __maybe_unused void flash_timing_cfg(u32 ahb_khz) 87 { 88 nandc_time_cfg(nand_para.access_freq); 89 } 90 91 static void flash_read_cmd(u8 cs, u32 page_addr) 92 { 93 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 94 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 95 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 96 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 97 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 98 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 99 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 100 } 101 102 static void flash_prog_first_cmd(u8 cs, u32 page_addr) 103 { 104 nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs)); 105 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 106 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 107 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 108 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 109 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 110 } 111 112 static void flash_erase_cmd(u8 cs, u32 page_addr) 113 { 114 nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs)); 115 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 116 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 117 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 118 nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 119 } 120 121 static void flash_prog_second_cmd(u8 cs, u32 page_addr) 122 { 123 nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 124 } 125 126 static u32 flash_read_status(u8 cs, u32 page_addr) 127 { 128 nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs)); 129 nandc_delayns(80); 130 131 return nandc_readl(NANDC_CHIP_DATA(cs)); 132 } 133 134 static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr) 135 { 136 nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs)); 137 nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 138 nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs)); 139 nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 140 } 141 142 static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 143 { 144 u32 ret = 0; 145 u32 error_ecc_bits; 146 u32 sec_per_page = nand_para.sec_per_page; 147 148 nandc_wait_flash_ready(cs); 149 nandc_flash_cs(cs); 150 flash_read_cmd(cs, page_addr); 151 nandc_wait_flash_ready(cs); 152 flash_read_random_dataout_cmd(cs, 0); 153 nandc_wait_flash_ready(cs); 154 155 error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page, 156 p_data, p_spare); 157 if (error_ecc_bits > 2) { 158 PRINT_NANDC_E("FlashReadRawPage %x %x error_ecc_bits %d\n", 159 cs, page_addr, error_ecc_bits); 160 if (p_data) 161 PRINT_NANDC_HEX("data:", p_data, 4, 8); 162 if (p_spare) 163 PRINT_NANDC_HEX("spare:", p_spare, 4, 2); 164 } 165 nandc_flash_de_cs(cs); 166 167 if (error_ecc_bits != NAND_STS_ECC_ERR) { 168 if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) 169 ret = NAND_STS_REFRESH; 170 else 171 ret = NAND_STS_OK; 172 } 173 174 return ret; 175 } 176 177 static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 178 { 179 u32 ret; 180 181 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 182 if (ret == NAND_STS_ECC_ERR) 183 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 184 185 return ret; 186 } 187 188 static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 189 { 190 u32 status; 191 u32 sec_per_page = nand_para.sec_per_page; 192 193 nandc_wait_flash_ready(cs); 194 nandc_flash_cs(cs); 195 flash_prog_first_cmd(cs, page_addr); 196 nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare); 197 flash_prog_second_cmd(cs, page_addr); 198 nandc_wait_flash_ready(cs); 199 status = flash_read_status(cs, page_addr); 200 nandc_flash_de_cs(cs); 201 status &= 0x01; 202 if (status) { 203 PRINT_NANDC_I("%s addr=%x status=%x\n", 204 __func__, page_addr, status); 205 } 206 return status; 207 } 208 209 static u32 flash_erase_block(u8 cs, u32 page_addr) 210 { 211 u32 status; 212 213 nandc_wait_flash_ready(cs); 214 nandc_flash_cs(cs); 215 flash_erase_cmd(cs, page_addr); 216 nandc_wait_flash_ready(cs); 217 status = flash_read_status(cs, page_addr); 218 nandc_flash_de_cs(cs); 219 status &= 0x01; 220 if (status) { 221 PRINT_NANDC_I("%s pageadd=%x status=%x\n", 222 __func__, page_addr, status); 223 } 224 return status; 225 } 226 227 static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare) 228 { 229 u32 col = nand_para.sec_per_page << 9; 230 231 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 232 nandc_writel(col, NANDC_CHIP_ADDR(cs)); 233 nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs)); 234 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 235 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 236 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 237 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 238 239 nandc_wait_flash_ready(cs); 240 241 *spare = nandc_readl(NANDC_CHIP_DATA(cs)); 242 } 243 244 /* 245 * Read the 1st page's 1st spare byte of a phy_blk 246 * If not FF, it's bad blk 247 */ 248 static s32 get_bad_blk_list(u16 *table, u32 die) 249 { 250 u16 blk; 251 u32 bad_cnt, page_addr0, page_addr1, page_addr2; 252 u32 blk_per_die; 253 u8 bad_flag0, bad_flag1, bad_flag2; 254 255 bad_cnt = 0; 256 blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane; 257 for (blk = 0; blk < blk_per_die; blk++) { 258 bad_flag0 = 0xFF; 259 bad_flag1 = 0xFF; 260 bad_flag2 = 0xFF; 261 page_addr0 = (blk + blk_per_die * die) * 262 nand_para.page_per_blk + 0; 263 page_addr1 = page_addr0 + 1; 264 page_addr2 = page_addr0 + nand_para.page_per_blk - 1; 265 flash_read_spare(die, page_addr0, &bad_flag0); 266 flash_read_spare(die, page_addr1, &bad_flag1); 267 flash_read_spare(die, page_addr2, &bad_flag2); 268 if (bad_flag0 != 0xFF || 269 bad_flag1 != 0xFF || 270 bad_flag2 != 0xFF) { 271 table[bad_cnt++] = blk; 272 PRINT_NANDC_E("die[%d], bad_blk[%d]\n", die, blk); 273 } 274 } 275 return bad_cnt; 276 } 277 278 #if FLASH_STRESS_TEST_EN 279 280 #define FLASH_PAGE_SIZE 2048 281 #define FLASH_SPARE_SIZE 8 282 283 static u16 bad_blk_list[1024]; 284 static u32 pwrite[FLASH_PAGE_SIZE / 4]; 285 static u32 pread[FLASH_PAGE_SIZE / 4]; 286 static u32 pspare_write[FLASH_SPARE_SIZE / 4]; 287 static u32 pspare_read[FLASH_SPARE_SIZE / 4]; 288 static u32 bad_blk_num; 289 static u32 bad_page_num; 290 291 static void flash_test(void) 292 { 293 u32 i, blk, page, bad_cnt, page_addr; 294 int ret; 295 u32 pages_num = 64; 296 u32 blk_addr = 64; 297 u32 is_bad_blk = 0; 298 299 PRINT_NANDC_E("%s\n", __func__); 300 bad_blk_num = 0; 301 bad_page_num = 0; 302 bad_cnt = get_bad_blk_list(bad_blk_list, 0); 303 304 for (blk = 0; blk < 1024; blk++) { 305 for (i = 0; i < bad_cnt; i++) { 306 if (bad_blk_list[i] == blk) 307 break; 308 } 309 if (i < bad_cnt) 310 continue; 311 is_bad_blk = 0; 312 PRINT_NANDC_E("Flash prog block: %x\n", blk); 313 flash_erase_block(0, blk * blk_addr); 314 for (page = 0; page < pages_num; page++) { 315 page_addr = blk * blk_addr + page; 316 for (i = 0; i < 512; i++) 317 pwrite[i] = (page_addr << 16) + i; 318 pspare_write[0] = pwrite[0] + 0x5AF0; 319 pspare_write[1] = pspare_write[0] + 1; 320 flash_prog_page(0, page_addr, pwrite, pspare_write); 321 memset(pread, 0, 2048); 322 memset(pspare_read, 0, 8); 323 ret = flash_read_page(0, page_addr, pread, 324 pspare_read); 325 if (ret != NAND_STS_OK) 326 is_bad_blk = 1; 327 for (i = 0; i < 512; i++) { 328 if (pwrite[i] != pread[i]) { 329 is_bad_blk = 1; 330 break; 331 } 332 } 333 for (i = 0; i < 2; i++) { 334 if (pspare_write[i] != pspare_read[i]) { 335 is_bad_blk = 1; 336 break; 337 } 338 } 339 if (is_bad_blk) { 340 bad_page_num++; 341 PRINT_NANDC_E("ERR:page %x, ret= %x\n", 342 page_addr, 343 ret); 344 PRINT_NANDC_HEX("data:", pread, 4, 8); 345 PRINT_NANDC_HEX("spare:", pspare_read, 4, 2); 346 } 347 } 348 flash_erase_block(0, blk * blk_addr); 349 if (is_bad_blk) 350 bad_blk_num++; 351 } 352 PRINT_NANDC_E("bad_blk_num = %d, bad_page_num = %d\n", 353 bad_blk_num, bad_page_num); 354 355 PRINT_NANDC_E("Flash Test Finish!!!\n"); 356 while (1) 357 ; 358 } 359 #endif 360 361 static void flash_die_info_init(void) 362 { 363 u32 cs; 364 365 g_nand_max_die = 0; 366 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 367 if (nand_para.nand_id[1] == id_byte[cs][1]) { 368 die_cs_index[g_nand_max_die] = cs; 369 g_nand_max_die++; 370 } 371 } 372 g_totle_block = g_nand_max_die * nand_para.plane_per_die * 373 nand_para.blk_per_plane; 374 } 375 376 static void nandc_flash_print_info(void) 377 { 378 PRINT_NANDC_I("No.0 FLASH ID: %x %x %x %x %x %x\n", 379 nand_para.nand_id[0], 380 nand_para.nand_id[1], 381 nand_para.nand_id[2], 382 nand_para.nand_id[3], 383 nand_para.nand_id[4], 384 nand_para.nand_id[5]); 385 PRINT_NANDC_I("die_per_chip: %x\n", nand_para.die_per_chip); 386 PRINT_NANDC_I("sec_per_page: %x\n", nand_para.sec_per_page); 387 PRINT_NANDC_I("page_per_blk: %x\n", nand_para.page_per_blk); 388 PRINT_NANDC_I("cell: %x\n", nand_para.cell); 389 PRINT_NANDC_I("plane_per_die: %x\n", nand_para.plane_per_die); 390 PRINT_NANDC_I("blk_per_plane: %x\n", nand_para.blk_per_plane); 391 PRINT_NANDC_I("TotleBlock: %x\n", g_totle_block); 392 PRINT_NANDC_I("die gap: %x\n", nand_para.die_gap); 393 PRINT_NANDC_I("lsb_mode: %x\n", nand_para.lsb_mode); 394 PRINT_NANDC_I("read_retry_mode: %x\n", nand_para.read_retry_mode); 395 PRINT_NANDC_I("ecc_bits: %x\n", nand_para.ecc_bits); 396 PRINT_NANDC_I("Use ecc_bits: %x\n", g_nand_flash_ecc_bits); 397 PRINT_NANDC_I("access_freq: %x\n", nand_para.access_freq); 398 PRINT_NANDC_I("opt_mode: %x\n", nand_para.opt_mode); 399 400 PRINT_NANDC_I("Cache read enable: %x\n", 401 nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0); 402 PRINT_NANDC_I("Cache random read enable: %x\n", 403 nand_para.operation_opt & 404 NAND_CACHE_RANDOM_READ_EN ? 1 : 0); 405 PRINT_NANDC_I("Cache prog enable: %x\n", 406 nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0); 407 PRINT_NANDC_I("multi read enable: %x\n", 408 nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0); 409 410 PRINT_NANDC_I("multi prog enable: %x\n", 411 nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0); 412 PRINT_NANDC_I("interleave enable: %x\n", 413 nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0); 414 415 PRINT_NANDC_I("read retry enable: %x\n", 416 nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0); 417 PRINT_NANDC_I("randomizer enable: %x\n", 418 nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0); 419 420 PRINT_NANDC_I("SDR enable: %x\n", 421 nand_para.operation_opt & NAND_SDR_EN ? 1 : 0); 422 PRINT_NANDC_I("ONFI enable: %x\n", 423 nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0); 424 PRINT_NANDC_I("TOGGLE enable: %x\n", 425 nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0); 426 427 PRINT_NANDC_I("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num); 428 } 429 430 static void ftl_flash_init(void) 431 { 432 /* para init */ 433 g_nand_phy_info.nand_type = nand_para.cell; 434 g_nand_phy_info.die_num = nand_para.die_per_chip; 435 g_nand_phy_info.plane_per_die = nand_para.plane_per_die; 436 g_nand_phy_info.blk_per_plane = nand_para.blk_per_plane; 437 g_nand_phy_info.page_per_blk = nand_para.page_per_blk; 438 g_nand_phy_info.page_per_slc_blk = nand_para.page_per_blk / 439 nand_para.cell; 440 g_nand_phy_info.byte_per_sec = 512; 441 g_nand_phy_info.sec_per_page = nand_para.sec_per_page; 442 g_nand_phy_info.sec_per_blk = nand_para.sec_per_page * 443 nand_para.page_per_blk; 444 g_nand_phy_info.reserved_blk = 8; 445 g_nand_phy_info.blk_per_die = nand_para.plane_per_die * 446 nand_para.blk_per_plane; 447 g_nand_phy_info.ecc_bits = nand_para.ecc_bits; 448 449 /* driver register */ 450 g_nand_ops.get_bad_blk_list = get_bad_blk_list; 451 g_nand_ops.erase_blk = flash_erase_block; 452 g_nand_ops.prog_page = flash_prog_page; 453 g_nand_ops.read_page = flash_read_page; 454 } 455 456 u32 nandc_flash_init(void __iomem *nandc_addr) 457 { 458 u32 cs; 459 460 PRINT_NANDC_I("...%s enter...\n", __func__); 461 g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK; 462 463 nandc_init(nandc_addr); 464 465 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 466 flash_read_id_raw(cs, id_byte[cs]); 467 if (cs == 0) { 468 if (id_byte[0][0] == 0xFF || 469 id_byte[0][0] == 0 || 470 id_byte[0][1] == 0xFF) 471 return FTL_NO_FLASH; 472 if (id_byte[0][1] != 0xF1 && 473 id_byte[0][1] != 0xDA && 474 id_byte[0][1] != 0xD1 && 475 id_byte[0][1] != 0x95 && 476 id_byte[0][1] != 0xDC) 477 478 return FTL_UNSUPPORTED_FLASH; 479 } 480 } 481 nand_para.nand_id[1] = id_byte[0][1]; 482 if (id_byte[0][1] == 0xDA) { 483 nand_para.plane_per_die = 2; 484 nand_para.nand_id[1] = 0xDA; 485 } else if (id_byte[0][1] == 0xDC) { 486 nand_para.nand_id[1] = 0xDC; 487 if (id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) { 488 nand_para.plane_per_die = 2; 489 nand_para.sec_per_page = 8; 490 } else { 491 nand_para.plane_per_die = 2; 492 nand_para.blk_per_plane = 2048; 493 } 494 } 495 flash_die_info_init(); 496 flash_bch_sel(nand_para.ecc_bits); 497 nandc_flash_print_info(); 498 /* flash_print_info(); */ 499 ftl_flash_init(); 500 501 #if FLASH_STRESS_TEST_EN 502 flash_test(); 503 #endif 504 505 return 0; 506 } 507 508 void nandc_flash_get_id(u8 cs, void *buf) 509 { 510 memcpy(buf, id_byte[cs], 5); 511 } 512 513 u32 nandc_flash_deinit(void) 514 { 515 return 0; 516 } 517