1 /* 2 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <common.h> 8 #include <linux/delay.h> 9 10 #include "flash.h" 11 #include "flash_com.h" 12 #include "nandc.h" 13 #include "rkflash_debug.h" 14 15 #define FLASH_STRESS_TEST_EN 0 16 17 static u8 id_byte[MAX_FLASH_NUM][8]; 18 static u8 die_cs_index[MAX_FLASH_NUM]; 19 static u8 g_nand_max_die; 20 static u16 g_totle_block; 21 static u8 g_nand_flash_ecc_bits; 22 static u8 g_nand_idb_res_blk_num; 23 static u8 g_nand_ecc_en; 24 25 static struct NAND_PARA_INFO_T nand_para = { 26 2, 27 {0x98, 0xF1, 0, 0, 0, 0}, 28 TOSHIBA, 29 1, 30 4, 31 64, 32 1, 33 1, 34 1024, 35 0x100, 36 LSB_0, 37 RR_NONE, 38 16, 39 40, 40 1, 41 0, 42 BBF_1, 43 MPM_0, 44 {0} 45 }; /* TC58NVG0S3HTA00 */ 46 47 void nandc_flash_reset(u8 cs) 48 { 49 nandc_flash_cs(cs); 50 nandc_writel(RESET_CMD, NANDC_CHIP_CMD(cs)); 51 nandc_wait_flash_ready(cs); 52 nandc_flash_de_cs(cs); 53 } 54 55 static void flash_read_id_raw(u8 cs, u8 *buf) 56 { 57 u8 *ptr = (u8 *)buf; 58 59 nandc_flash_reset(cs); 60 nandc_flash_cs(cs); 61 nandc_writel(READ_ID_CMD, NANDC_CHIP_CMD(cs)); 62 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 63 nandc_delayns(200); 64 65 ptr[0] = nandc_readl(NANDC_CHIP_DATA(cs)); 66 ptr[1] = nandc_readl(NANDC_CHIP_DATA(cs)); 67 ptr[2] = nandc_readl(NANDC_CHIP_DATA(cs)); 68 ptr[3] = nandc_readl(NANDC_CHIP_DATA(cs)); 69 ptr[4] = nandc_readl(NANDC_CHIP_DATA(cs)); 70 ptr[5] = nandc_readl(NANDC_CHIP_DATA(cs)); 71 ptr[6] = nandc_readl(NANDC_CHIP_DATA(cs)); 72 ptr[7] = nandc_readl(NANDC_CHIP_DATA(cs)); 73 74 nandc_flash_de_cs(cs); 75 if (ptr[0] != 0xFF && ptr[0] && ptr[1] != 0xFF) 76 PRINT_NANDC_E("No.%d FLASH ID:%x %x %x %x %x %x\n", 77 cs + 1, ptr[0], ptr[1], ptr[2], 78 ptr[3], ptr[4], ptr[5]); 79 } 80 81 static void flash_bch_sel(u8 bits) 82 { 83 g_nand_flash_ecc_bits = bits; 84 nandc_bch_sel(bits); 85 } 86 87 static void flash_set_sector(u8 num) 88 { 89 nand_para.sec_per_page = num; 90 } 91 92 static __maybe_unused void flash_timing_cfg(u32 ahb_khz) 93 { 94 nandc_time_cfg(nand_para.access_freq); 95 } 96 97 static void flash_read_cmd(u8 cs, u32 page_addr) 98 { 99 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 100 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 101 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 102 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 103 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 104 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 105 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 106 } 107 108 static void flash_prog_first_cmd(u8 cs, u32 page_addr) 109 { 110 nandc_writel(PAGE_PROG_CMD >> 8, NANDC_CHIP_CMD(cs)); 111 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 112 nandc_writel(0x00, NANDC_CHIP_ADDR(cs)); 113 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 114 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 115 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 116 } 117 118 static void flash_erase_cmd(u8 cs, u32 page_addr) 119 { 120 nandc_writel(BLOCK_ERASE_CMD >> 8, NANDC_CHIP_CMD(cs)); 121 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 122 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 123 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 124 nandc_writel(BLOCK_ERASE_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 125 } 126 127 static void flash_prog_second_cmd(u8 cs, u32 page_addr) 128 { 129 udelay(100); 130 nandc_writel(PAGE_PROG_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 131 } 132 133 static u32 flash_read_status(u8 cs, u32 page_addr) 134 { 135 nandc_writel(READ_STATUS_CMD, NANDC_CHIP_CMD(cs)); 136 nandc_delayns(80); 137 138 return nandc_readl(NANDC_CHIP_DATA(cs)); 139 } 140 141 static void flash_read_random_dataout_cmd(u8 cs, u32 col_addr) 142 { 143 nandc_writel(READ_DP_OUT_CMD >> 8, NANDC_CHIP_CMD(cs)); 144 nandc_writel(col_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 145 nandc_writel(col_addr >> 8, NANDC_CHIP_ADDR(cs)); 146 nandc_writel(READ_DP_OUT_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 147 } 148 149 static u32 flash_read_ecc(u8 cs) 150 { 151 u32 ecc0, ecc1; 152 153 nandc_writel(READ_ECC_STATUS_CMD, NANDC_CHIP_CMD(cs)); 154 nandc_delayns(80); 155 ecc0 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF; 156 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF; 157 if (ecc1 > ecc0) 158 ecc0 = ecc1; 159 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF; 160 if (ecc1 > ecc0) 161 ecc0 = ecc1; 162 ecc1 = nandc_readl(NANDC_CHIP_DATA(cs)) & 0xF; 163 if (ecc1 > ecc0) 164 ecc0 = ecc1; 165 166 return ecc0; 167 } 168 169 static u32 flash_read_page_raw(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 170 { 171 u32 error_ecc_bits; 172 u32 sec_per_page = nand_para.sec_per_page; 173 174 nandc_wait_flash_ready(cs); 175 nandc_flash_cs(cs); 176 flash_read_cmd(cs, page_addr); 177 nandc_wait_flash_ready(cs); 178 flash_read_random_dataout_cmd(cs, 0); 179 nandc_wait_flash_ready(cs); 180 181 error_ecc_bits = nandc_xfer_data(cs, NANDC_READ, sec_per_page, 182 p_data, p_spare); 183 /* 184 if (error_ecc_bits > 12) { 185 PRINT_NANDC_E("%s %x %x error_ecc_bits %d\n", 186 __func__, cs, page_addr, error_ecc_bits); 187 if (p_data) 188 PRINT_NANDC_HEX("data:", p_data, 4, 2); 189 if (p_spare) 190 PRINT_NANDC_HEX("spare:", p_spare, 4, 2); 191 } 192 */ 193 nandc_flash_de_cs(cs); 194 195 if (error_ecc_bits != NAND_STS_ECC_ERR) { 196 if (error_ecc_bits >= (u32)nand_para.ecc_bits - 3) { 197 error_ecc_bits = NAND_STS_REFRESH; 198 } else { 199 error_ecc_bits = NAND_STS_OK; 200 if (g_nand_ecc_en) { 201 u32 nand_ecc = flash_read_ecc(cs); 202 203 if (nand_ecc >= 6) { 204 PRINT_NANDC_E("%s nand ecc %x ecc %d\n", 205 __func__, page_addr, nand_ecc); 206 error_ecc_bits = NAND_STS_REFRESH; 207 } 208 } 209 } 210 } 211 212 return error_ecc_bits; 213 } 214 215 static u32 flash_read_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 216 { 217 u32 ret, i; 218 219 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 220 if (ret == NAND_STS_ECC_ERR) { 221 for (i = 0; i < 50; i++) { 222 ret = flash_read_page_raw(cs, page_addr, p_data, p_spare); 223 if (ret != NAND_STS_ECC_ERR) { 224 ret = NAND_STS_REFRESH; 225 break; 226 } 227 } 228 PRINT_NANDC_E("flash_read_page %x err_ecc %d\n", page_addr, ret); 229 } 230 return ret; 231 } 232 233 static u32 flash_prog_page(u8 cs, u32 page_addr, u32 *p_data, u32 *p_spare) 234 { 235 u32 status; 236 u32 sec_per_page = nand_para.sec_per_page; 237 238 nandc_wait_flash_ready(cs); 239 nandc_flash_cs(cs); 240 flash_prog_first_cmd(cs, page_addr); 241 nandc_xfer_data(cs, NANDC_WRITE, sec_per_page, p_data, p_spare); 242 flash_prog_second_cmd(cs, page_addr); 243 nandc_wait_flash_ready(cs); 244 status = flash_read_status(cs, page_addr); 245 nandc_flash_de_cs(cs); 246 status &= 0x01; 247 if (status) { 248 PRINT_NANDC_I("%s addr=%x status=%x\n", 249 __func__, page_addr, status); 250 } 251 return status; 252 } 253 254 static u32 flash_erase_block(u8 cs, u32 page_addr) 255 { 256 u32 status; 257 258 nandc_wait_flash_ready(cs); 259 nandc_flash_cs(cs); 260 flash_erase_cmd(cs, page_addr); 261 nandc_wait_flash_ready(cs); 262 status = flash_read_status(cs, page_addr); 263 nandc_flash_de_cs(cs); 264 status &= 0x01; 265 if (status) { 266 PRINT_NANDC_I("%s pageadd=%x status=%x\n", 267 __func__, page_addr, status); 268 } 269 return status; 270 } 271 272 static void flash_read_spare(u8 cs, u32 page_addr, u8 *spare) 273 { 274 u32 col = nand_para.sec_per_page << 9; 275 276 nandc_writel(READ_CMD >> 8, NANDC_CHIP_CMD(cs)); 277 nandc_writel(col, NANDC_CHIP_ADDR(cs)); 278 nandc_writel(col >> 8, NANDC_CHIP_ADDR(cs)); 279 nandc_writel(page_addr & 0x00ff, NANDC_CHIP_ADDR(cs)); 280 nandc_writel(page_addr >> 8, NANDC_CHIP_ADDR(cs)); 281 nandc_writel(page_addr >> 16, NANDC_CHIP_ADDR(cs)); 282 nandc_writel(READ_CMD & 0x00ff, NANDC_CHIP_CMD(cs)); 283 284 nandc_wait_flash_ready(cs); 285 286 *spare = nandc_readl(NANDC_CHIP_DATA(cs)); 287 } 288 289 /* 290 * Read the 1st page's 1st spare byte of a phy_blk 291 * If not FF, it's bad blk 292 */ 293 static s32 get_bad_blk_list(u16 *table, u32 die) 294 { 295 u16 blk; 296 u32 bad_cnt, page_addr0, page_addr1, page_addr2; 297 u32 blk_per_die; 298 u8 bad_flag0, bad_flag1, bad_flag2; 299 300 bad_cnt = 0; 301 blk_per_die = nand_para.plane_per_die * nand_para.blk_per_plane; 302 for (blk = 0; blk < blk_per_die; blk++) { 303 bad_flag0 = 0xFF; 304 bad_flag1 = 0xFF; 305 bad_flag2 = 0xFF; 306 page_addr0 = (blk + blk_per_die * die) * 307 nand_para.page_per_blk + 0; 308 page_addr1 = page_addr0 + 1; 309 page_addr2 = page_addr0 + nand_para.page_per_blk - 1; 310 flash_read_spare(die, page_addr0, &bad_flag0); 311 flash_read_spare(die, page_addr1, &bad_flag1); 312 flash_read_spare(die, page_addr2, &bad_flag2); 313 if (bad_flag0 != 0xFF || 314 bad_flag1 != 0xFF || 315 bad_flag2 != 0xFF) { 316 table[bad_cnt++] = blk; 317 PRINT_NANDC_E("die[%d], bad_blk[%d]\n", die, blk); 318 } 319 } 320 return bad_cnt; 321 } 322 323 #if FLASH_STRESS_TEST_EN 324 325 #define FLASH_PAGE_SIZE 2048 326 #define FLASH_SPARE_SIZE 8 327 328 static u16 bad_blk_list[1024]; 329 static u32 pwrite[FLASH_PAGE_SIZE / 4]; 330 static u32 pread[FLASH_PAGE_SIZE / 4]; 331 static u32 pspare_write[FLASH_SPARE_SIZE / 4]; 332 static u32 pspare_read[FLASH_SPARE_SIZE / 4]; 333 static u32 bad_blk_num; 334 static u32 bad_page_num; 335 336 static void flash_test(void) 337 { 338 u32 i, blk, page, bad_cnt, page_addr; 339 int ret; 340 u32 pages_num = 64; 341 u32 blk_addr = 64; 342 u32 is_bad_blk = 0; 343 344 PRINT_NANDC_E("%s\n", __func__); 345 bad_blk_num = 0; 346 bad_page_num = 0; 347 bad_cnt = get_bad_blk_list(bad_blk_list, 0); 348 349 for (blk = 0; blk < 1024; blk++) { 350 for (i = 0; i < bad_cnt; i++) { 351 if (bad_blk_list[i] == blk) 352 break; 353 } 354 if (i < bad_cnt) 355 continue; 356 is_bad_blk = 0; 357 PRINT_NANDC_E("Flash prog block: %x\n", blk); 358 flash_erase_block(0, blk * blk_addr); 359 for (page = 0; page < pages_num; page++) { 360 page_addr = blk * blk_addr + page; 361 for (i = 0; i < 512; i++) 362 pwrite[i] = (page_addr << 16) + i; 363 pspare_write[0] = pwrite[0] + 0x5AF0; 364 pspare_write[1] = pspare_write[0] + 1; 365 flash_prog_page(0, page_addr, pwrite, pspare_write); 366 memset(pread, 0, 2048); 367 memset(pspare_read, 0, 8); 368 ret = flash_read_page(0, page_addr, pread, 369 pspare_read); 370 if (ret != NAND_STS_OK) 371 is_bad_blk = 1; 372 for (i = 0; i < 512; i++) { 373 if (pwrite[i] != pread[i]) { 374 is_bad_blk = 1; 375 break; 376 } 377 } 378 for (i = 0; i < 2; i++) { 379 if (pspare_write[i] != pspare_read[i]) { 380 is_bad_blk = 1; 381 break; 382 } 383 } 384 if (is_bad_blk) { 385 bad_page_num++; 386 PRINT_NANDC_E("ERR:page %x, ret= %x\n", 387 page_addr, 388 ret); 389 PRINT_NANDC_HEX("data:", pread, 4, 8); 390 PRINT_NANDC_HEX("spare:", pspare_read, 4, 2); 391 } 392 } 393 flash_erase_block(0, blk * blk_addr); 394 if (is_bad_blk) 395 bad_blk_num++; 396 } 397 PRINT_NANDC_E("bad_blk_num = %d, bad_page_num = %d\n", 398 bad_blk_num, bad_page_num); 399 400 PRINT_NANDC_E("Flash Test Finish!!!\n"); 401 while (1) 402 ; 403 } 404 #endif 405 406 static void flash_die_info_init(void) 407 { 408 u32 cs; 409 410 g_nand_max_die = 0; 411 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 412 if (nand_para.nand_id[1] == id_byte[cs][1]) { 413 die_cs_index[g_nand_max_die] = cs; 414 g_nand_max_die++; 415 } 416 } 417 g_totle_block = g_nand_max_die * nand_para.plane_per_die * 418 nand_para.blk_per_plane; 419 } 420 421 static void nandc_flash_print_info(void) 422 { 423 PRINT_NANDC_I("No.0 FLASH ID: %x %x %x %x %x %x\n", 424 nand_para.nand_id[0], 425 nand_para.nand_id[1], 426 nand_para.nand_id[2], 427 nand_para.nand_id[3], 428 nand_para.nand_id[4], 429 nand_para.nand_id[5]); 430 PRINT_NANDC_I("die_per_chip: %x\n", nand_para.die_per_chip); 431 PRINT_NANDC_I("sec_per_page: %x\n", nand_para.sec_per_page); 432 PRINT_NANDC_I("page_per_blk: %x\n", nand_para.page_per_blk); 433 PRINT_NANDC_I("cell: %x\n", nand_para.cell); 434 PRINT_NANDC_I("plane_per_die: %x\n", nand_para.plane_per_die); 435 PRINT_NANDC_I("blk_per_plane: %x\n", nand_para.blk_per_plane); 436 PRINT_NANDC_I("TotleBlock: %x\n", g_totle_block); 437 PRINT_NANDC_I("die gap: %x\n", nand_para.die_gap); 438 PRINT_NANDC_I("lsb_mode: %x\n", nand_para.lsb_mode); 439 PRINT_NANDC_I("read_retry_mode: %x\n", nand_para.read_retry_mode); 440 PRINT_NANDC_I("ecc_bits: %x\n", nand_para.ecc_bits); 441 PRINT_NANDC_I("Use ecc_bits: %x\n", g_nand_flash_ecc_bits); 442 PRINT_NANDC_I("access_freq: %x\n", nand_para.access_freq); 443 PRINT_NANDC_I("opt_mode: %x\n", nand_para.opt_mode); 444 445 PRINT_NANDC_I("Cache read enable: %x\n", 446 nand_para.operation_opt & NAND_CACHE_READ_EN ? 1 : 0); 447 PRINT_NANDC_I("Cache random read enable: %x\n", 448 nand_para.operation_opt & 449 NAND_CACHE_RANDOM_READ_EN ? 1 : 0); 450 PRINT_NANDC_I("Cache prog enable: %x\n", 451 nand_para.operation_opt & NAND_CACHE_PROG_EN ? 1 : 0); 452 PRINT_NANDC_I("multi read enable: %x\n", 453 nand_para.operation_opt & NAND_MULTI_READ_EN ? 1 : 0); 454 455 PRINT_NANDC_I("multi prog enable: %x\n", 456 nand_para.operation_opt & NAND_MULTI_PROG_EN ? 1 : 0); 457 PRINT_NANDC_I("interleave enable: %x\n", 458 nand_para.operation_opt & NAND_INTERLEAVE_EN ? 1 : 0); 459 460 PRINT_NANDC_I("read retry enable: %x\n", 461 nand_para.operation_opt & NAND_READ_RETRY_EN ? 1 : 0); 462 PRINT_NANDC_I("randomizer enable: %x\n", 463 nand_para.operation_opt & NAND_RANDOMIZER_EN ? 1 : 0); 464 465 PRINT_NANDC_I("SDR enable: %x\n", 466 nand_para.operation_opt & NAND_SDR_EN ? 1 : 0); 467 PRINT_NANDC_I("ONFI enable: %x\n", 468 nand_para.operation_opt & NAND_ONFI_EN ? 1 : 0); 469 PRINT_NANDC_I("TOGGLE enable: %x\n", 470 nand_para.operation_opt & NAND_TOGGLE_EN ? 1 : 0); 471 472 PRINT_NANDC_I("g_nand_idb_res_blk_num: %x\n", g_nand_idb_res_blk_num); 473 } 474 475 static void ftl_flash_init(void) 476 { 477 u8 nandc_ver = nandc_get_version(); 478 479 /* para init */ 480 g_nand_phy_info.nand_type = nand_para.cell; 481 g_nand_phy_info.die_num = nand_para.die_per_chip; 482 g_nand_phy_info.plane_per_die = nand_para.plane_per_die; 483 g_nand_phy_info.blk_per_plane = nand_para.blk_per_plane; 484 g_nand_phy_info.page_per_blk = nand_para.page_per_blk; 485 g_nand_phy_info.page_per_slc_blk = nand_para.page_per_blk / 486 nand_para.cell; 487 g_nand_phy_info.byte_per_sec = 512; 488 g_nand_phy_info.sec_per_page = nand_para.sec_per_page; 489 g_nand_phy_info.sec_per_blk = nand_para.sec_per_page * 490 nand_para.page_per_blk; 491 g_nand_phy_info.reserved_blk = 8; 492 g_nand_phy_info.blk_per_die = nand_para.plane_per_die * 493 nand_para.blk_per_plane; 494 g_nand_phy_info.ecc_bits = nand_para.ecc_bits; 495 496 /* driver register */ 497 g_nand_ops.get_bad_blk_list = get_bad_blk_list; 498 g_nand_ops.erase_blk = flash_erase_block; 499 g_nand_ops.prog_page = flash_prog_page; 500 g_nand_ops.read_page = flash_read_page; 501 if (nandc_ver == 9) { 502 g_nand_ops.bch_sel = flash_bch_sel; 503 g_nand_ops.set_sec_num = flash_set_sector; 504 } 505 } 506 507 u32 nandc_flash_init(void __iomem *nandc_addr) 508 { 509 u32 cs; 510 511 PRINT_NANDC_I("...%s enter...\n", __func__); 512 g_nand_idb_res_blk_num = MAX_IDB_RESERVED_BLOCK; 513 g_nand_ecc_en = 0; 514 515 nandc_init(nandc_addr); 516 517 for (cs = 0; cs < MAX_FLASH_NUM; cs++) { 518 flash_read_id_raw(cs, id_byte[cs]); 519 if (cs == 0) { 520 if (id_byte[0][0] == 0xFF || 521 id_byte[0][0] == 0 || 522 id_byte[0][1] == 0xFF) 523 return FTL_NO_FLASH; 524 if (id_byte[0][1] != 0xF1 && 525 id_byte[0][1] != 0xDA && 526 id_byte[0][1] != 0xD1 && 527 id_byte[0][1] != 0x95 && 528 id_byte[0][1] != 0xDC && 529 id_byte[0][1] != 0x48) 530 531 return FTL_UNSUPPORTED_FLASH; 532 } 533 } 534 if (id_byte[0][0] == 0x98 && (id_byte[0][4] & 0x80)) 535 g_nand_ecc_en = 1; 536 nand_para.nand_id[1] = id_byte[0][1]; 537 if (id_byte[0][1] == 0xDA) { 538 nand_para.plane_per_die = 2; 539 nand_para.nand_id[1] = 0xDA; 540 } else if (id_byte[0][1] == 0xDC) { 541 nand_para.nand_id[1] = 0xDC; 542 if (id_byte[0][0] == 0x2C && id_byte[0][3] == 0xA6) { 543 nand_para.plane_per_die = 2; 544 nand_para.sec_per_page = 8; 545 } else if (id_byte[0][0] == 0x98 && id_byte[0][3] == 0x26) { 546 nand_para.blk_per_plane = 1024; 547 nand_para.sec_per_page = 8; 548 nand_para.plane_per_die = 2; 549 } else { 550 nand_para.plane_per_die = 2; 551 nand_para.blk_per_plane = 2048; 552 } 553 } else if (id_byte[0][1] == 0x48) { 554 nand_para.sec_per_page = 8; 555 nand_para.page_per_blk = 128; 556 nand_para.plane_per_die = 2; 557 nand_para.blk_per_plane = 2048; 558 } 559 flash_die_info_init(); 560 flash_bch_sel(nand_para.ecc_bits); 561 nandc_flash_print_info(); 562 /* flash_print_info(); */ 563 ftl_flash_init(); 564 565 #if FLASH_STRESS_TEST_EN 566 flash_test(); 567 #endif 568 569 return 0; 570 } 571 572 void nandc_flash_get_id(u8 cs, void *buf) 573 { 574 memcpy(buf, id_byte[cs], 5); 575 } 576 577 u32 nandc_flash_deinit(void) 578 { 579 return 0; 580 } 581