1 /* 2 * (C) Copyright 2016-2017 Rockchip Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 * 6 * Adapted from coreboot. 7 */ 8 9 #include <common.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <dt-structs.h> 13 #include <ram.h> 14 #include <regmap.h> 15 #include <syscon.h> 16 #include <asm/io.h> 17 #include <asm/arch/clock.h> 18 #include <asm/arch/sdram_common.h> 19 #include <asm/arch/sdram_rk3399.h> 20 #include <asm/arch/cru_rk3399.h> 21 #include <asm/arch/grf_rk3399.h> 22 #include <asm/arch/hardware.h> 23 #include <linux/err.h> 24 #include <time.h> 25 26 DECLARE_GLOBAL_DATA_PTR; 27 struct chan_info { 28 struct rk3399_ddr_pctl_regs *pctl; 29 struct rk3399_ddr_pi_regs *pi; 30 struct rk3399_ddr_publ_regs *publ; 31 struct msch_regs *msch; 32 }; 33 34 struct dram_info { 35 #ifdef CONFIG_TPL_BUILD 36 struct chan_info chan[2]; 37 struct clk ddr_clk; 38 struct rk3399_cru *cru; 39 struct rk3399_pmucru *pmucru; 40 struct rk3399_pmusgrf_regs *pmusgrf; 41 struct rk3399_ddr_cic_regs *cic; 42 #endif 43 struct ram_info info; 44 struct rk3399_pmugrf_regs *pmugrf; 45 }; 46 47 #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6)) 48 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7)) 49 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8)) 50 51 #define PHY_DRV_ODT_Hi_Z 0x0 52 #define PHY_DRV_ODT_240 0x1 53 #define PHY_DRV_ODT_120 0x8 54 #define PHY_DRV_ODT_80 0x9 55 #define PHY_DRV_ODT_60 0xc 56 #define PHY_DRV_ODT_48 0xd 57 #define PHY_DRV_ODT_40 0xe 58 #define PHY_DRV_ODT_34_3 0xf 59 60 #ifdef CONFIG_TPL_BUILD 61 62 struct rockchip_dmc_plat { 63 #if CONFIG_IS_ENABLED(OF_PLATDATA) 64 struct dtd_rockchip_rk3399_dmc dtplat; 65 #else 66 struct rk3399_sdram_params sdram_params; 67 #endif 68 struct regmap *map; 69 }; 70 71 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ 72 ((n) << (8 + (ch) * 4))) 73 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \ 74 ((n) << (9 + (ch) * 4))) 75 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl, 76 u32 phy) 77 { 78 channel &= 0x1; 79 ctl &= 0x1; 80 phy &= 0x1; 81 writel(CRU_SFTRST_DDR_CTRL(channel, ctl) | 82 CRU_SFTRST_DDR_PHY(channel, phy), 83 &cru->softrst_con[4]); 84 } 85 86 static void phy_pctrl_reset(struct rk3399_cru *cru, 87 u32 channel) 88 { 89 rkclk_ddr_reset(cru, channel, 1, 1); 90 udelay(10); 91 rkclk_ddr_reset(cru, channel, 1, 0); 92 udelay(10); 93 rkclk_ddr_reset(cru, channel, 0, 0); 94 udelay(10); 95 } 96 97 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs, 98 u32 freq) 99 { 100 u32 *denali_phy = ddr_publ_regs->denali_phy; 101 102 /* From IP spec, only freq small than 125 can enter dll bypass mode */ 103 if (freq <= 125) { 104 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 105 setbits_le32(&denali_phy[86], (0x3 << 2) << 8); 106 setbits_le32(&denali_phy[214], (0x3 << 2) << 8); 107 setbits_le32(&denali_phy[342], (0x3 << 2) << 8); 108 setbits_le32(&denali_phy[470], (0x3 << 2) << 8); 109 110 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 111 setbits_le32(&denali_phy[547], (0x3 << 2) << 16); 112 setbits_le32(&denali_phy[675], (0x3 << 2) << 16); 113 setbits_le32(&denali_phy[803], (0x3 << 2) << 16); 114 } else { 115 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ 116 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8); 117 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8); 118 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8); 119 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8); 120 121 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ 122 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16); 123 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16); 124 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16); 125 } 126 } 127 128 static void set_memory_map(const struct chan_info *chan, u32 channel, 129 const struct rk3399_sdram_params *sdram_params) 130 { 131 const struct rk3399_sdram_channel *sdram_ch = 132 &sdram_params->ch[channel]; 133 u32 *denali_ctl = chan->pctl->denali_ctl; 134 u32 *denali_pi = chan->pi->denali_pi; 135 u32 cs_map; 136 u32 reduc; 137 u32 row; 138 139 /* Get row number from ddrconfig setting */ 140 if (sdram_ch->cap_info.ddrconfig < 2 || 141 sdram_ch->cap_info.ddrconfig == 4) 142 row = 16; 143 else if (sdram_ch->cap_info.ddrconfig == 3) 144 row = 14; 145 else 146 row = 15; 147 148 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1; 149 reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1; 150 151 /* Set the dram configuration to ctrl */ 152 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col)); 153 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), 154 ((3 - sdram_ch->cap_info.bk) << 16) | 155 ((16 - row) << 24)); 156 157 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), 158 cs_map | (reduc << 16)); 159 160 /* PI_199 PI_COL_DIFF:RW:0:4 */ 161 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col)); 162 163 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ 164 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), 165 ((3 - sdram_ch->cap_info.bk) << 16) | 166 ((16 - row) << 24)); 167 /* PI_41 PI_CS_MAP:RW:24:4 */ 168 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); 169 if (sdram_ch->cap_info.rank == 1 && 170 sdram_params->base.dramtype == DDR3) 171 writel(0x2EC7FFFF, &denali_pi[34]); 172 } 173 174 static void set_ds_odt(const struct chan_info *chan, 175 const struct rk3399_sdram_params *sdram_params) 176 { 177 u32 *denali_phy = chan->publ->denali_phy; 178 179 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; 180 u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p; 181 u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n; 182 u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n; 183 u32 reg_value; 184 185 if (sdram_params->base.dramtype == LPDDR4) { 186 tsel_rd_select_p = PHY_DRV_ODT_Hi_Z; 187 tsel_wr_select_p = PHY_DRV_ODT_40; 188 ca_tsel_wr_select_p = PHY_DRV_ODT_40; 189 tsel_idle_select_p = PHY_DRV_ODT_Hi_Z; 190 191 tsel_rd_select_n = PHY_DRV_ODT_240; 192 tsel_wr_select_n = PHY_DRV_ODT_40; 193 ca_tsel_wr_select_n = PHY_DRV_ODT_40; 194 tsel_idle_select_n = PHY_DRV_ODT_240; 195 } else if (sdram_params->base.dramtype == LPDDR3) { 196 tsel_rd_select_p = PHY_DRV_ODT_240; 197 tsel_wr_select_p = PHY_DRV_ODT_34_3; 198 ca_tsel_wr_select_p = PHY_DRV_ODT_48; 199 tsel_idle_select_p = PHY_DRV_ODT_240; 200 201 tsel_rd_select_n = PHY_DRV_ODT_Hi_Z; 202 tsel_wr_select_n = PHY_DRV_ODT_34_3; 203 ca_tsel_wr_select_n = PHY_DRV_ODT_48; 204 tsel_idle_select_n = PHY_DRV_ODT_Hi_Z; 205 } else { 206 tsel_rd_select_p = PHY_DRV_ODT_240; 207 tsel_wr_select_p = PHY_DRV_ODT_34_3; 208 ca_tsel_wr_select_p = PHY_DRV_ODT_34_3; 209 tsel_idle_select_p = PHY_DRV_ODT_240; 210 211 tsel_rd_select_n = PHY_DRV_ODT_240; 212 tsel_wr_select_n = PHY_DRV_ODT_34_3; 213 ca_tsel_wr_select_n = PHY_DRV_ODT_34_3; 214 tsel_idle_select_n = PHY_DRV_ODT_240; 215 } 216 217 if (sdram_params->base.odt == 1) 218 tsel_rd_en = 1; 219 else 220 tsel_rd_en = 0; 221 222 tsel_wr_en = 0; 223 tsel_idle_en = 0; 224 225 /* 226 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 227 * sets termination values for read/idle cycles and drive strength 228 * for write cycles for DQ/DM 229 */ 230 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | 231 (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) | 232 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20); 233 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); 234 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); 235 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); 236 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); 237 238 /* 239 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0 240 * sets termination values for read/idle cycles and drive strength 241 * for write cycles for DQS 242 */ 243 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); 244 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); 245 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); 246 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); 247 248 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */ 249 reg_value = ca_tsel_wr_select_n | (ca_tsel_wr_select_p << 0x4); 250 clrsetbits_le32(&denali_phy[544], 0xff, reg_value); 251 clrsetbits_le32(&denali_phy[672], 0xff, reg_value); 252 clrsetbits_le32(&denali_phy[800], 0xff, reg_value); 253 254 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */ 255 clrsetbits_le32(&denali_phy[928], 0xff, reg_value); 256 257 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */ 258 clrsetbits_le32(&denali_phy[937], 0xff, reg_value); 259 260 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */ 261 clrsetbits_le32(&denali_phy[935], 0xff, reg_value); 262 263 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */ 264 clrsetbits_le32(&denali_phy[939], 0xff, reg_value); 265 266 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */ 267 clrsetbits_le32(&denali_phy[929], 0xff, reg_value); 268 269 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */ 270 clrsetbits_le32(&denali_phy[924], 0xff, 271 tsel_wr_select_n | (tsel_wr_select_p << 4)); 272 clrsetbits_le32(&denali_phy[925], 0xff, 273 tsel_rd_select_n | (tsel_rd_select_p << 4)); 274 275 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */ 276 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) 277 << 16; 278 clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value); 279 clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value); 280 clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value); 281 clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value); 282 283 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */ 284 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2)) 285 << 24; 286 clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value); 287 clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value); 288 clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value); 289 clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value); 290 291 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */ 292 reg_value = tsel_wr_en << 8; 293 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value); 294 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value); 295 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value); 296 297 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */ 298 reg_value = tsel_wr_en << 17; 299 clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value); 300 /* 301 * pad_rst/cke/cs/clk_term tsel 1bits 302 * DENALI_PHY_938/936/940/934 offset_17 303 */ 304 clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value); 305 clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value); 306 clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value); 307 clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value); 308 309 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */ 310 clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value); 311 } 312 313 static int phy_io_config(const struct chan_info *chan, 314 const struct rk3399_sdram_params *sdram_params) 315 { 316 u32 *denali_phy = chan->publ->denali_phy; 317 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac; 318 u32 mode_sel; 319 u32 reg_value; 320 u32 drv_value, odt_value; 321 u32 speed; 322 323 /* vref setting */ 324 if (sdram_params->base.dramtype == LPDDR4) { 325 /* LPDDR4 */ 326 vref_mode_dq = 0x6; 327 vref_value_dq = 0x1f; 328 vref_mode_ac = 0x6; 329 vref_value_ac = 0x1f; 330 } else if (sdram_params->base.dramtype == LPDDR3) { 331 if (sdram_params->base.odt == 1) { 332 vref_mode_dq = 0x5; /* LPDDR3 ODT */ 333 drv_value = (readl(&denali_phy[6]) >> 12) & 0xf; 334 odt_value = (readl(&denali_phy[6]) >> 4) & 0xf; 335 if (drv_value == PHY_DRV_ODT_48) { 336 switch (odt_value) { 337 case PHY_DRV_ODT_240: 338 vref_value_dq = 0x16; 339 break; 340 case PHY_DRV_ODT_120: 341 vref_value_dq = 0x26; 342 break; 343 case PHY_DRV_ODT_60: 344 vref_value_dq = 0x36; 345 break; 346 default: 347 debug("Invalid ODT value.\n"); 348 return -EINVAL; 349 } 350 } else if (drv_value == PHY_DRV_ODT_40) { 351 switch (odt_value) { 352 case PHY_DRV_ODT_240: 353 vref_value_dq = 0x19; 354 break; 355 case PHY_DRV_ODT_120: 356 vref_value_dq = 0x23; 357 break; 358 case PHY_DRV_ODT_60: 359 vref_value_dq = 0x31; 360 break; 361 default: 362 debug("Invalid ODT value.\n"); 363 return -EINVAL; 364 } 365 } else if (drv_value == PHY_DRV_ODT_34_3) { 366 switch (odt_value) { 367 case PHY_DRV_ODT_240: 368 vref_value_dq = 0x17; 369 break; 370 case PHY_DRV_ODT_120: 371 vref_value_dq = 0x20; 372 break; 373 case PHY_DRV_ODT_60: 374 vref_value_dq = 0x2e; 375 break; 376 default: 377 debug("Invalid ODT value.\n"); 378 return -EINVAL; 379 } 380 } else { 381 debug("Invalid DRV value.\n"); 382 return -EINVAL; 383 } 384 } else { 385 vref_mode_dq = 0x2; /* LPDDR3 */ 386 vref_value_dq = 0x1f; 387 } 388 vref_mode_ac = 0x2; 389 vref_value_ac = 0x1f; 390 } else if (sdram_params->base.dramtype == DDR3) { 391 /* DDR3L */ 392 vref_mode_dq = 0x1; 393 vref_value_dq = 0x1f; 394 vref_mode_ac = 0x1; 395 vref_value_ac = 0x1f; 396 } else { 397 debug("Unknown DRAM type.\n"); 398 return -EINVAL; 399 } 400 401 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq; 402 403 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */ 404 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8); 405 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */ 406 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value); 407 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */ 408 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16); 409 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */ 410 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value); 411 412 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac; 413 414 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */ 415 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16); 416 417 if (sdram_params->base.dramtype == LPDDR4) 418 mode_sel = 0x6; 419 else if (sdram_params->base.dramtype == LPDDR3) 420 mode_sel = 0x0; 421 else if (sdram_params->base.dramtype == DDR3) 422 mode_sel = 0x1; 423 else 424 return -EINVAL; 425 426 /* PHY_924 PHY_PAD_FDBK_DRIVE */ 427 clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15); 428 /* PHY_926 PHY_PAD_DATA_DRIVE */ 429 clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6); 430 /* PHY_927 PHY_PAD_DQS_DRIVE */ 431 clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6); 432 /* PHY_928 PHY_PAD_ADDR_DRIVE */ 433 clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14); 434 /* PHY_929 PHY_PAD_CLK_DRIVE */ 435 clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14); 436 /* PHY_935 PHY_PAD_CKE_DRIVE */ 437 clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14); 438 /* PHY_937 PHY_PAD_RST_DRIVE */ 439 clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14); 440 /* PHY_939 PHY_PAD_CS_DRIVE */ 441 clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14); 442 443 /* speed setting */ 444 if (sdram_params->base.ddr_freq < 400) 445 speed = 0x0; 446 else if (sdram_params->base.ddr_freq < 800) 447 speed = 0x1; 448 else if (sdram_params->base.ddr_freq < 1200) 449 speed = 0x2; 450 else 451 speed = 0x3; 452 453 /* PHY_924 PHY_PAD_FDBK_DRIVE */ 454 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21); 455 /* PHY_926 PHY_PAD_DATA_DRIVE */ 456 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9); 457 /* PHY_927 PHY_PAD_DQS_DRIVE */ 458 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9); 459 /* PHY_928 PHY_PAD_ADDR_DRIVE */ 460 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17); 461 /* PHY_929 PHY_PAD_CLK_DRIVE */ 462 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17); 463 /* PHY_935 PHY_PAD_CKE_DRIVE */ 464 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17); 465 /* PHY_937 PHY_PAD_RST_DRIVE */ 466 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17); 467 /* PHY_939 PHY_PAD_CS_DRIVE */ 468 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17); 469 470 return 0; 471 } 472 473 static int pctl_cfg(const struct chan_info *chan, u32 channel, 474 const struct rk3399_sdram_params *sdram_params) 475 { 476 u32 *denali_ctl = chan->pctl->denali_ctl; 477 u32 *denali_pi = chan->pi->denali_pi; 478 u32 *denali_phy = chan->publ->denali_phy; 479 const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; 480 const u32 *params_phy = sdram_params->phy_regs.denali_phy; 481 u32 tmp, tmp1, tmp2; 482 u32 pwrup_srefresh_exit; 483 int ret; 484 const ulong timeout_ms = 200; 485 486 /* 487 * work around controller bug: 488 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed 489 */ 490 sdram_copy_to_reg(&denali_ctl[1], ¶ms_ctl[1], 491 sizeof(struct rk3399_ddr_pctl_regs) - 4); 492 writel(params_ctl[0], &denali_ctl[0]); 493 sdram_copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], 494 sizeof(struct rk3399_ddr_pi_regs)); 495 /* rank count need to set for init */ 496 set_memory_map(chan, channel, sdram_params); 497 498 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); 499 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); 500 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); 501 502 pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT; 503 clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT); 504 505 /* PHY_DLL_RST_EN */ 506 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24); 507 508 setbits_le32(&denali_pi[0], START); 509 setbits_le32(&denali_ctl[0], START); 510 511 /* Waiting for phy DLL lock */ 512 while (1) { 513 tmp = readl(&denali_phy[920]); 514 tmp1 = readl(&denali_phy[921]); 515 tmp2 = readl(&denali_phy[922]); 516 if ((((tmp >> 16) & 0x1) == 0x1) && 517 (((tmp1 >> 16) & 0x1) == 0x1) && 518 (((tmp1 >> 0) & 0x1) == 0x1) && 519 (((tmp2 >> 0) & 0x1) == 0x1)) 520 break; 521 } 522 523 sdram_copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); 524 sdram_copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); 525 sdram_copy_to_reg(&denali_phy[128], 526 ¶ms_phy[128], (218 - 128 + 1) * 4); 527 sdram_copy_to_reg(&denali_phy[256], 528 ¶ms_phy[256], (346 - 256 + 1) * 4); 529 sdram_copy_to_reg(&denali_phy[384], 530 ¶ms_phy[384], (474 - 384 + 1) * 4); 531 sdram_copy_to_reg(&denali_phy[512], 532 ¶ms_phy[512], (549 - 512 + 1) * 4); 533 sdram_copy_to_reg(&denali_phy[640], 534 ¶ms_phy[640], (677 - 640 + 1) * 4); 535 sdram_copy_to_reg(&denali_phy[768], 536 ¶ms_phy[768], (805 - 768 + 1) * 4); 537 set_ds_odt(chan, sdram_params); 538 539 /* 540 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8 541 * dqs_tsel_wr_end[7:4] add Half cycle 542 */ 543 tmp = (readl(&denali_phy[84]) >> 8) & 0xff; 544 clrsetbits_le32(&denali_phy[84], 0xff << 8, (tmp + 0x10) << 8); 545 tmp = (readl(&denali_phy[212]) >> 8) & 0xff; 546 clrsetbits_le32(&denali_phy[212], 0xff << 8, (tmp + 0x10) << 8); 547 tmp = (readl(&denali_phy[340]) >> 8) & 0xff; 548 clrsetbits_le32(&denali_phy[340], 0xff << 8, (tmp + 0x10) << 8); 549 tmp = (readl(&denali_phy[468]) >> 8) & 0xff; 550 clrsetbits_le32(&denali_phy[468], 0xff << 8, (tmp + 0x10) << 8); 551 552 /* 553 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 554 * dq_tsel_wr_end[7:4] add Half cycle 555 */ 556 tmp = (readl(&denali_phy[83]) >> 16) & 0xff; 557 clrsetbits_le32(&denali_phy[83], 0xff << 16, (tmp + 0x10) << 16); 558 tmp = (readl(&denali_phy[211]) >> 16) & 0xff; 559 clrsetbits_le32(&denali_phy[211], 0xff << 16, (tmp + 0x10) << 16); 560 tmp = (readl(&denali_phy[339]) >> 16) & 0xff; 561 clrsetbits_le32(&denali_phy[339], 0xff << 16, (tmp + 0x10) << 16); 562 tmp = (readl(&denali_phy[467]) >> 16) & 0xff; 563 clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16); 564 565 ret = phy_io_config(chan, sdram_params); 566 if (ret) 567 return ret; 568 569 /* PHY_DLL_RST_EN */ 570 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24); 571 572 /* Waiting for PHY and DRAM init complete */ 573 tmp = get_timer(0); 574 do { 575 if (get_timer(tmp) > timeout_ms) { 576 pr_err("DRAM (%s): phy failed to lock within %ld ms\n", 577 __func__, timeout_ms); 578 return -ETIME; 579 } 580 } while (!(readl(&denali_ctl[203]) & (1 << 3))); 581 debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp)); 582 583 clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, 584 pwrup_srefresh_exit); 585 return 0; 586 } 587 588 static void select_per_cs_training_index(const struct chan_info *chan, 589 u32 rank) 590 { 591 u32 *denali_phy = chan->publ->denali_phy; 592 593 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */ 594 if ((readl(&denali_phy[84]) >> 16) & 1) { 595 /* 596 * PHY_8/136/264/392 597 * phy_per_cs_training_index_X 1bit offset_24 598 */ 599 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24); 600 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24); 601 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24); 602 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24); 603 } 604 } 605 606 static void override_write_leveling_value(const struct chan_info *chan) 607 { 608 u32 *denali_ctl = chan->pctl->denali_ctl; 609 u32 *denali_phy = chan->publ->denali_phy; 610 u32 byte; 611 612 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ 613 setbits_le32(&denali_phy[896], 1); 614 615 /* 616 * PHY_8/136/264/392 617 * phy_per_cs_training_multicast_en_X 1bit offset_16 618 */ 619 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16); 620 clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); 621 clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); 622 clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); 623 624 for (byte = 0; byte < 4; byte++) 625 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, 626 0x200 << 16); 627 628 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ 629 clrbits_le32(&denali_phy[896], 1); 630 631 /* CTL_200 ctrlupd_req 1bit offset_8 */ 632 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); 633 } 634 635 static int data_training_ca(const struct chan_info *chan, u32 channel, 636 const struct rk3399_sdram_params *sdram_params) 637 { 638 u32 *denali_pi = chan->pi->denali_pi; 639 u32 *denali_phy = chan->publ->denali_phy; 640 u32 i, tmp; 641 u32 obs_0, obs_1, obs_2, obs_err = 0; 642 u32 rank = sdram_params->ch[channel].cap_info.rank; 643 644 for (i = 0; i < rank; i++) { 645 select_per_cs_training_index(chan, i); 646 /* PI_100 PI_CALVL_EN:RW:8:2 */ 647 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8); 648 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */ 649 clrsetbits_le32(&denali_pi[92], 650 (0x1 << 16) | (0x3 << 24), 651 (0x1 << 16) | (i << 24)); 652 653 /* Waiting for training complete */ 654 while (1) { 655 /* PI_174 PI_INT_STATUS:RD:8:18 */ 656 tmp = readl(&denali_pi[174]) >> 8; 657 /* 658 * check status obs 659 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32 660 */ 661 obs_0 = readl(&denali_phy[532]); 662 obs_1 = readl(&denali_phy[660]); 663 obs_2 = readl(&denali_phy[788]); 664 if (((obs_0 >> 30) & 0x3) || 665 ((obs_1 >> 30) & 0x3) || 666 ((obs_2 >> 30) & 0x3)) 667 obs_err = 1; 668 if ((((tmp >> 11) & 0x1) == 0x1) && 669 (((tmp >> 13) & 0x1) == 0x1) && 670 (((tmp >> 5) & 0x1) == 0x0) && 671 (obs_err == 0)) 672 break; 673 else if ((((tmp >> 5) & 0x1) == 0x1) || 674 (obs_err == 1)) 675 return -EIO; 676 } 677 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 678 writel(0x00003f7c, (&denali_pi[175])); 679 } 680 clrbits_le32(&denali_pi[100], 0x3 << 8); 681 682 return 0; 683 } 684 685 static int data_training_wl(const struct chan_info *chan, u32 channel, 686 const struct rk3399_sdram_params *sdram_params) 687 { 688 u32 *denali_pi = chan->pi->denali_pi; 689 u32 *denali_phy = chan->publ->denali_phy; 690 u32 i, tmp; 691 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; 692 u32 rank = sdram_params->ch[channel].cap_info.rank; 693 694 for (i = 0; i < rank; i++) { 695 select_per_cs_training_index(chan, i); 696 /* PI_60 PI_WRLVL_EN:RW:8:2 */ 697 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8); 698 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */ 699 clrsetbits_le32(&denali_pi[59], 700 (0x1 << 8) | (0x3 << 16), 701 (0x1 << 8) | (i << 16)); 702 703 /* Waiting for training complete */ 704 while (1) { 705 /* PI_174 PI_INT_STATUS:RD:8:18 */ 706 tmp = readl(&denali_pi[174]) >> 8; 707 708 /* 709 * check status obs, if error maybe can not 710 * get leveling done PHY_40/168/296/424 711 * phy_wrlvl_status_obs_X:0:13 712 */ 713 obs_0 = readl(&denali_phy[40]); 714 obs_1 = readl(&denali_phy[168]); 715 obs_2 = readl(&denali_phy[296]); 716 obs_3 = readl(&denali_phy[424]); 717 if (((obs_0 >> 12) & 0x1) || 718 ((obs_1 >> 12) & 0x1) || 719 ((obs_2 >> 12) & 0x1) || 720 ((obs_3 >> 12) & 0x1)) 721 obs_err = 1; 722 if ((((tmp >> 10) & 0x1) == 0x1) && 723 (((tmp >> 13) & 0x1) == 0x1) && 724 (((tmp >> 4) & 0x1) == 0x0) && 725 (obs_err == 0)) 726 break; 727 else if ((((tmp >> 4) & 0x1) == 0x1) || 728 (obs_err == 1)) 729 return -EIO; 730 } 731 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 732 writel(0x00003f7c, (&denali_pi[175])); 733 } 734 735 override_write_leveling_value(chan); 736 clrbits_le32(&denali_pi[60], 0x3 << 8); 737 738 return 0; 739 } 740 741 static int data_training_rg(const struct chan_info *chan, u32 channel, 742 const struct rk3399_sdram_params *sdram_params) 743 { 744 u32 *denali_pi = chan->pi->denali_pi; 745 u32 *denali_phy = chan->publ->denali_phy; 746 u32 i, tmp; 747 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0; 748 u32 rank = sdram_params->ch[channel].cap_info.rank; 749 750 for (i = 0; i < rank; i++) { 751 select_per_cs_training_index(chan, i); 752 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */ 753 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24); 754 /* 755 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1 756 * PI_RDLVL_CS:RW:24:2 757 */ 758 clrsetbits_le32(&denali_pi[74], 759 (0x1 << 16) | (0x3 << 24), 760 (0x1 << 16) | (i << 24)); 761 762 /* Waiting for training complete */ 763 while (1) { 764 /* PI_174 PI_INT_STATUS:RD:8:18 */ 765 tmp = readl(&denali_pi[174]) >> 8; 766 767 /* 768 * check status obs 769 * PHY_43/171/299/427 770 * PHY_GTLVL_STATUS_OBS_x:16:8 771 */ 772 obs_0 = readl(&denali_phy[43]); 773 obs_1 = readl(&denali_phy[171]); 774 obs_2 = readl(&denali_phy[299]); 775 obs_3 = readl(&denali_phy[427]); 776 if (((obs_0 >> (16 + 6)) & 0x3) || 777 ((obs_1 >> (16 + 6)) & 0x3) || 778 ((obs_2 >> (16 + 6)) & 0x3) || 779 ((obs_3 >> (16 + 6)) & 0x3)) 780 obs_err = 1; 781 if ((((tmp >> 9) & 0x1) == 0x1) && 782 (((tmp >> 13) & 0x1) == 0x1) && 783 (((tmp >> 3) & 0x1) == 0x0) && 784 (obs_err == 0)) 785 break; 786 else if ((((tmp >> 3) & 0x1) == 0x1) || 787 (obs_err == 1)) 788 return -EIO; 789 } 790 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 791 writel(0x00003f7c, (&denali_pi[175])); 792 } 793 clrbits_le32(&denali_pi[80], 0x3 << 24); 794 795 return 0; 796 } 797 798 static int data_training_rl(const struct chan_info *chan, u32 channel, 799 const struct rk3399_sdram_params *sdram_params) 800 { 801 u32 *denali_pi = chan->pi->denali_pi; 802 u32 i, tmp; 803 u32 rank = sdram_params->ch[channel].cap_info.rank; 804 805 for (i = 0; i < rank; i++) { 806 select_per_cs_training_index(chan, i); 807 /* PI_80 PI_RDLVL_EN:RW:16:2 */ 808 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16); 809 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */ 810 clrsetbits_le32(&denali_pi[74], 811 (0x1 << 8) | (0x3 << 24), 812 (0x1 << 8) | (i << 24)); 813 814 /* Waiting for training complete */ 815 while (1) { 816 /* PI_174 PI_INT_STATUS:RD:8:18 */ 817 tmp = readl(&denali_pi[174]) >> 8; 818 819 /* 820 * make sure status obs not report error bit 821 * PHY_46/174/302/430 822 * phy_rdlvl_status_obs_X:16:8 823 */ 824 if ((((tmp >> 8) & 0x1) == 0x1) && 825 (((tmp >> 13) & 0x1) == 0x1) && 826 (((tmp >> 2) & 0x1) == 0x0)) 827 break; 828 else if (((tmp >> 2) & 0x1) == 0x1) 829 return -EIO; 830 } 831 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 832 writel(0x00003f7c, (&denali_pi[175])); 833 } 834 clrbits_le32(&denali_pi[80], 0x3 << 16); 835 836 return 0; 837 } 838 839 static int data_training_wdql(const struct chan_info *chan, u32 channel, 840 const struct rk3399_sdram_params *sdram_params) 841 { 842 u32 *denali_pi = chan->pi->denali_pi; 843 u32 i, tmp; 844 u32 rank = sdram_params->ch[channel].cap_info.rank; 845 846 for (i = 0; i < rank; i++) { 847 select_per_cs_training_index(chan, i); 848 /* 849 * disable PI_WDQLVL_VREF_EN before wdq leveling? 850 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1 851 */ 852 clrbits_le32(&denali_pi[181], 0x1 << 8); 853 /* PI_124 PI_WDQLVL_EN:RW:16:2 */ 854 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16); 855 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */ 856 clrsetbits_le32(&denali_pi[121], 857 (0x1 << 8) | (0x3 << 16), 858 (0x1 << 8) | (i << 16)); 859 860 /* Waiting for training complete */ 861 while (1) { 862 /* PI_174 PI_INT_STATUS:RD:8:18 */ 863 tmp = readl(&denali_pi[174]) >> 8; 864 if ((((tmp >> 12) & 0x1) == 0x1) && 865 (((tmp >> 13) & 0x1) == 0x1) && 866 (((tmp >> 6) & 0x1) == 0x0)) 867 break; 868 else if (((tmp >> 6) & 0x1) == 0x1) 869 return -EIO; 870 } 871 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ 872 writel(0x00003f7c, (&denali_pi[175])); 873 } 874 clrbits_le32(&denali_pi[124], 0x3 << 16); 875 876 return 0; 877 } 878 879 static int data_training(const struct chan_info *chan, u32 channel, 880 const struct rk3399_sdram_params *sdram_params, 881 u32 training_flag) 882 { 883 u32 *denali_phy = chan->publ->denali_phy; 884 int ret = 0; 885 886 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 887 setbits_le32(&denali_phy[927], (1 << 22)); 888 889 if (training_flag == PI_FULL_TRAINING) { 890 if (sdram_params->base.dramtype == LPDDR4) { 891 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | 892 PI_READ_GATE_TRAINING | 893 PI_READ_LEVELING | PI_WDQ_LEVELING; 894 } else if (sdram_params->base.dramtype == LPDDR3) { 895 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | 896 PI_READ_GATE_TRAINING; 897 } else if (sdram_params->base.dramtype == DDR3) { 898 training_flag = PI_WRITE_LEVELING | 899 PI_READ_GATE_TRAINING | 900 PI_READ_LEVELING; 901 } 902 } 903 904 /* ca training(LPDDR4,LPDDR3 support) */ 905 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) { 906 ret = data_training_ca(chan, channel, sdram_params); 907 if (ret != 0) 908 goto out; 909 } 910 911 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ 912 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) { 913 ret = data_training_wl(chan, channel, sdram_params); 914 if (ret != 0) 915 goto out; 916 } 917 918 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ 919 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) { 920 ret = data_training_rg(chan, channel, sdram_params); 921 if (ret != 0) 922 goto out; 923 } 924 925 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ 926 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) { 927 ret = data_training_rl(chan, channel, sdram_params); 928 if (ret != 0) 929 goto out; 930 } 931 932 /* wdq leveling(LPDDR4 support) */ 933 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) { 934 ret = data_training_wdql(chan, channel, sdram_params); 935 if (ret != 0) 936 goto out; 937 } 938 939 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ 940 clrbits_le32(&denali_phy[927], (1 << 22)); 941 942 out: 943 return ret; 944 } 945 946 static void set_ddrconfig(const struct chan_info *chan, 947 const struct rk3399_sdram_params *sdram_params, 948 unsigned char channel, u32 ddrconfig) 949 { 950 /* only need to set ddrconfig */ 951 struct msch_regs *ddr_msch_regs = chan->msch; 952 unsigned int cs0_cap = 0; 953 unsigned int cs1_cap = 0; 954 955 cs0_cap = (1 << (sdram_params->ch[channel].cap_info.cs0_row 956 + sdram_params->ch[channel].cap_info.col 957 + sdram_params->ch[channel].cap_info.bk 958 + sdram_params->ch[channel].cap_info.bw - 20)); 959 if (sdram_params->ch[channel].cap_info.rank > 1) 960 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cap_info.cs0_row 961 - sdram_params->ch[channel].cap_info.cs1_row); 962 if (sdram_params->ch[channel].cap_info.row_3_4) { 963 cs0_cap = cs0_cap * 3 / 4; 964 cs1_cap = cs1_cap * 3 / 4; 965 } 966 967 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); 968 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8), 969 &ddr_msch_regs->ddrsize); 970 } 971 972 static void dram_all_config(struct dram_info *dram, 973 struct rk3399_sdram_params *sdram_params) 974 { 975 u32 sys_reg2 = 0; 976 u32 sys_reg3 = 0; 977 unsigned int channel, idx; 978 979 for (channel = 0, idx = 0; 980 (idx < sdram_params->base.num_channels) && (channel < 2); 981 channel++) { 982 struct msch_regs *ddr_msch_regs; 983 struct sdram_msch_timings *noc_timing; 984 985 if (sdram_params->ch[channel].cap_info.col == 0) 986 continue; 987 idx++; 988 sdram_org_config(&sdram_params->ch[channel].cap_info, 989 &sdram_params->base, &sys_reg2, 990 &sys_reg3, channel); 991 ddr_msch_regs = dram->chan[channel].msch; 992 noc_timing = &sdram_params->ch[channel].noc_timings; 993 sdram_msch_config(ddr_msch_regs, noc_timing); 994 995 /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */ 996 if (sdram_params->ch[channel].cap_info.rank == 1) 997 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], 998 1 << 17); 999 } 1000 1001 writel(sys_reg2, &dram->pmugrf->os_reg2); 1002 writel(sys_reg3, &dram->pmugrf->os_reg3); 1003 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, 1004 sdram_params->base.stride << 10); 1005 1006 /* reboot hold register set */ 1007 writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) | 1008 PRESET_GPIO1_HOLD(1), 1009 &dram->pmucru->pmucru_rstnhold_con[1]); 1010 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); 1011 } 1012 1013 static int switch_to_phy_index1(struct dram_info *dram, 1014 const struct rk3399_sdram_params *sdram_params) 1015 { 1016 u32 channel; 1017 u32 *denali_phy; 1018 u32 ch_count = sdram_params->base.num_channels; 1019 int ret; 1020 int i = 0; 1021 1022 writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, 1023 1 << 4 | 1 << 2 | 1), 1024 &dram->cic->cic_ctrl0); 1025 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { 1026 mdelay(10); 1027 i++; 1028 if (i > 10) { 1029 debug("index1 frequency change overtime\n"); 1030 return -ETIME; 1031 } 1032 } 1033 1034 i = 0; 1035 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); 1036 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { 1037 mdelay(10); 1038 if (i > 10) { 1039 debug("index1 frequency done overtime\n"); 1040 return -ETIME; 1041 } 1042 } 1043 1044 for (channel = 0; channel < ch_count; channel++) { 1045 denali_phy = dram->chan[channel].publ->denali_phy; 1046 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); 1047 ret = data_training(&dram->chan[channel], channel, 1048 sdram_params, PI_FULL_TRAINING); 1049 if (ret) { 1050 debug("index1 training failed\n"); 1051 return ret; 1052 } 1053 } 1054 1055 return 0; 1056 } 1057 1058 u16 ddr_cfg_2_rbc[] = { 1059 /* 1060 * [6] highest bit col 1061 * [5:3] max row(14+n) 1062 * [2] insertion row 1063 * [1:0] col(9+n),col, data bus 32bit 1064 * 1065 * highbitcol, max_row, insertion_row, col 1066 */ 1067 ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */ 1068 ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */ 1069 ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */ 1070 ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */ 1071 ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */ 1072 ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */ 1073 ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */ 1074 ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */ 1075 }; 1076 1077 unsigned int calculate_ddrconfig(struct rk3399_sdram_params *sdram_params, 1078 unsigned int channel) 1079 { 1080 unsigned int i; 1081 unsigned int cs0_row = sdram_params->ch[channel].cap_info.cs0_row; 1082 unsigned int col = sdram_params->ch[channel].cap_info.col; 1083 unsigned int bw = sdram_params->ch[channel].cap_info.bw; 1084 1085 col -= (bw == 2) ? 0 : 1; 1086 col -= 9; 1087 1088 for (i = 0; i < 4; i++) { 1089 if ((col == (ddr_cfg_2_rbc[i] & 0x3)) && 1090 (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14))) 1091 break; 1092 } 1093 1094 if (i >= 4) 1095 i = -1; 1096 1097 return i; 1098 } 1099 1100 unsigned char calculate_stride(struct rk3399_sdram_params *sdram_params) 1101 { 1102 unsigned int gstride_type; 1103 unsigned int channel; 1104 unsigned int chinfo = 0; 1105 unsigned int cap = 0; 1106 unsigned int stride = -1; 1107 unsigned int ch_cap[2] = {0, 0}; 1108 1109 gstride_type = STRIDE_256B; 1110 1111 for (channel = 0; channel < 2; channel++) { 1112 unsigned int cs0_cap = 0; 1113 unsigned int cs1_cap = 0; 1114 struct sdram_cap_info *cap_info = 1115 &sdram_params->ch[channel].cap_info; 1116 1117 if (cap_info->col == 0) 1118 continue; 1119 1120 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + 1121 cap_info->bk + cap_info->bw - 20)); 1122 if (cap_info->rank > 1) 1123 cs1_cap = cs0_cap >> (cap_info->cs0_row 1124 - cap_info->cs1_row); 1125 if (cap_info->row_3_4) { 1126 cs0_cap = cs0_cap * 3 / 4; 1127 cs1_cap = cs1_cap * 3 / 4; 1128 } 1129 ch_cap[channel] = cs0_cap + cs1_cap; 1130 chinfo |= 1 << channel; 1131 } 1132 1133 cap = ch_cap[0] + ch_cap[1]; 1134 if (sdram_params->base.num_channels == 1) { 1135 if (chinfo & 1) /* channel a only */ 1136 stride = 0x17; 1137 else /* channel b only */ 1138 stride = 0x18; 1139 } else {/* 2 channel */ 1140 if (ch_cap[0] == ch_cap[1]) { 1141 /* interleaved */ 1142 if (gstride_type == PART_STRIDE) { 1143 /* 1144 * first 64MB no interleaved other 256B interleaved 1145 * if 786M+768M.useful space from 0-1280MB and 1146 * 1536MB-1792MB 1147 * if 1.5G+1.5G(continuous).useful space from 0-2560MB 1148 * and 3072MB-3584MB 1149 */ 1150 stride = 0x1F; 1151 } else { 1152 switch (cap) { 1153 /* 512MB */ 1154 case 512: 1155 stride = 0; 1156 break; 1157 /* 1GB unstride or 256B stride*/ 1158 case 1024: 1159 stride = (gstride_type == UN_STRIDE) ? 1160 0x1 : 0x5; 1161 break; 1162 /* 1163 * 768MB + 768MB same as total 2GB memory 1164 * useful space: 0-768MB 1GB-1792MB 1165 */ 1166 case 1536: 1167 /* 2GB unstride or 256B or 512B stride */ 1168 case 2048: 1169 stride = (gstride_type == UN_STRIDE) ? 1170 0x2 : 1171 ((gstride_type == STRIDE_512B) ? 1172 0xA : 0x9); 1173 break; 1174 /* 1536MB + 1536MB */ 1175 case 3072: 1176 stride = (gstride_type == UN_STRIDE) ? 1177 0x3 : 1178 ((gstride_type == STRIDE_512B) ? 1179 0x12 : 0x11); 1180 break; 1181 /* 4GB unstride or 128B,256B,512B,4KB stride */ 1182 case 4096: 1183 stride = (gstride_type == UN_STRIDE) ? 1184 0x3 : (0xC + gstride_type); 1185 break; 1186 } 1187 } 1188 } 1189 if (ch_cap[0] == 2048 && ch_cap[1] == 1024) { 1190 /* 2GB + 1GB */ 1191 stride = (gstride_type == UN_STRIDE) ? 0x3 : 0x19; 1192 } 1193 /* 1194 * remain two channel capability not equal OR capability 1195 * power function of 2 1196 */ 1197 if (stride == (-1)) { 1198 switch ((ch_cap[0] > ch_cap[1]) ? 1199 ch_cap[0] : ch_cap[1]) { 1200 case 256: /* 256MB + 128MB */ 1201 stride = 0; 1202 break; 1203 case 512: /* 512MB + 256MB */ 1204 stride = 1; 1205 break; 1206 case 1024:/* 1GB + 128MB/256MB/384MB/512MB/768MB */ 1207 stride = 2; 1208 break; 1209 case 2048: /* 2GB + 128MB/256MB/384MB/512MB/768MB/1GB */ 1210 stride = 3; 1211 break; 1212 default: 1213 break; 1214 } 1215 } 1216 if (stride == (-1)) 1217 goto error; 1218 } 1219 switch (stride) { 1220 case 0xc: 1221 printf("128B stride\n"); 1222 break; 1223 case 5: 1224 case 9: 1225 case 0xd: 1226 case 0x11: 1227 case 0x19: 1228 printf("256B stride\n"); 1229 break; 1230 case 0xa: 1231 case 0xe: 1232 case 0x12: 1233 printf("512B stride\n"); 1234 break; 1235 case 0xf: 1236 printf("4K stride\n"); 1237 break; 1238 case 0x1f: 1239 printf("32MB + 256B stride\n"); 1240 break; 1241 default: 1242 printf("no stride\n"); 1243 } 1244 1245 return stride; 1246 error: 1247 printf("Cap not support!\n"); 1248 return (-1); 1249 } 1250 1251 static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride) 1252 { 1253 rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, 1254 stride << 10); 1255 } 1256 1257 void set_cap_relate_config(const struct chan_info *chan, 1258 struct rk3399_sdram_params *sdram_params, 1259 unsigned int channel) 1260 { 1261 u32 *denali_ctl = chan->pctl->denali_ctl; 1262 u32 tmp; 1263 struct sdram_msch_timings *noc_timing; 1264 1265 if (sdram_params->base.dramtype == LPDDR3) { 1266 tmp = (8 << sdram_params->ch[channel].cap_info.bw) / 1267 (8 << sdram_params->ch[channel].cap_info.dbw); 1268 /* memdata_ratio 1269 * 1 -> 0, 2 -> 1, 4 -> 2 1270 */ 1271 clrsetbits_le32(&denali_ctl[197], 0x7, 1272 (tmp >> 1)); 1273 clrsetbits_le32(&denali_ctl[198], 0x7 << 8, 1274 (tmp >> 1) << 8); 1275 } 1276 noc_timing = &sdram_params->ch[channel].noc_timings; 1277 /* 1278 * noc timing bw relate timing is 32 bit, and real bw is 16bit 1279 * actually noc reg is setting at function dram_all_config 1280 */ 1281 if (sdram_params->ch[channel].cap_info.bw == 16 && 1282 noc_timing->ddrmode.b.mwrsize == 2) { 1283 if (noc_timing->ddrmode.b.burstsize) 1284 noc_timing->ddrmode.b.burstsize -= 1; 1285 noc_timing->ddrmode.b.mwrsize -= 1; 1286 noc_timing->ddrtimingc0.b.burstpenalty *= 2; 1287 noc_timing->ddrtimingc0.b.wrtomwr *= 2; 1288 } 1289 } 1290 1291 void clear_channel_params(struct rk3399_sdram_params *sdram_params, 1292 unsigned int channel) 1293 { 1294 sdram_params->ch[channel].cap_info.rank = 0; 1295 sdram_params->ch[channel].cap_info.col = 0; 1296 sdram_params->ch[channel].cap_info.bk = 0; 1297 sdram_params->ch[channel].cap_info.bw = 32; 1298 sdram_params->ch[channel].cap_info.dbw = 32; 1299 sdram_params->ch[channel].cap_info.row_3_4 = 0; 1300 sdram_params->ch[channel].cap_info.cs0_row = 0; 1301 sdram_params->ch[channel].cap_info.cs1_row = 0; 1302 sdram_params->ch[channel].cap_info.ddrconfig = 0; 1303 } 1304 1305 /* CS0,n=1 1306 * CS1,n=2 1307 * CS0 & CS1, n=3 1308 * cs0_cap: MB unit 1309 */ 1310 void dram_set_cs(const struct chan_info *chan, u32 cs_map, u32 cs0_cap, 1311 unsigned char dramtype) 1312 { 1313 u32 *denali_ctl = chan->pctl->denali_ctl; 1314 u32 *denali_pi = chan->pi->denali_pi; 1315 struct msch_regs *ddr_msch_regs = chan->msch; 1316 1317 clrsetbits_le32(&denali_ctl[196], 0x3, cs_map); 1318 writel((cs0_cap / 32) | (((4096 - cs0_cap) / 32) << 8), 1319 &ddr_msch_regs->ddrsize); 1320 if (dramtype == LPDDR4) { 1321 if (cs_map == 1) 1322 cs_map = 0x5; 1323 else if (cs_map == 2) 1324 cs_map = 0xa; 1325 else 1326 cs_map = 0xF; 1327 } 1328 /*PI_41 PI_CS_MAP:RW:24:4*/ 1329 clrsetbits_le32(&denali_pi[41], 1330 0xf << 24, cs_map << 24); 1331 if (cs_map == 1 && dramtype == DDR3) 1332 writel(0x2EC7FFFF, &denali_pi[34]); 1333 } 1334 1335 void dram_set_bw(const struct chan_info *chan, u32 bw) 1336 { 1337 u32 *denali_ctl = chan->pctl->denali_ctl; 1338 1339 if (bw == 2) 1340 clrbits_le32(&denali_ctl[196], 1 << 16); 1341 else 1342 setbits_le32(&denali_ctl[196], 1 << 16); 1343 } 1344 1345 void dram_set_max_col(const struct chan_info *chan, u32 bw, u32 *pcol) 1346 { 1347 u32 *denali_ctl = chan->pctl->denali_ctl; 1348 struct msch_regs *ddr_msch_regs = chan->msch; 1349 u32 *denali_pi = chan->pi->denali_pi; 1350 u32 ddrconfig; 1351 1352 clrbits_le32(&denali_ctl[191], 0xf); 1353 clrsetbits_le32(&denali_ctl[190], 1354 (7 << 24), 1355 ((16 - ((bw == 2) ? 14 : 15)) << 24)); 1356 /*PI_199 PI_COL_DIFF:RW:0:4*/ 1357 clrbits_le32(&denali_pi[199], 0xf); 1358 /*PI_155 PI_ROW_DIFF:RW:24:3*/ 1359 clrsetbits_le32(&denali_pi[155], 1360 (7 << 24), 1361 ((16 - 12) << 24)); 1362 ddrconfig = (bw == 2) ? 3 : 2; 1363 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); 1364 /* set max cs0 size */ 1365 writel((4096 / 32) | ((0 / 32) << 8), 1366 &ddr_msch_regs->ddrsize); 1367 1368 *pcol = 12; 1369 } 1370 1371 void dram_set_max_bank(const struct chan_info *chan, u32 bw, u32 *pbank, 1372 u32 *pcol) 1373 { 1374 u32 *denali_ctl = chan->pctl->denali_ctl; 1375 u32 *denali_pi = chan->pi->denali_pi; 1376 1377 clrbits_le32(&denali_ctl[191], 0xf); 1378 clrbits_le32(&denali_ctl[190], (3 << 16)); 1379 /*PI_199 PI_COL_DIFF:RW:0:4*/ 1380 clrbits_le32(&denali_pi[199], 0xf); 1381 /*PI_155 PI_BANK_DIFF:RW:16:2*/ 1382 clrbits_le32(&denali_pi[155], (3 << 16)); 1383 1384 *pbank = 3; 1385 *pcol = 12; 1386 } 1387 1388 void dram_set_max_row(const struct chan_info *chan, u32 bw, u32 *prow, 1389 u32 *pbank, u32 *pcol) 1390 { 1391 u32 *denali_ctl = chan->pctl->denali_ctl; 1392 u32 *denali_pi = chan->pi->denali_pi; 1393 struct msch_regs *ddr_msch_regs = chan->msch; 1394 1395 clrsetbits_le32(&denali_ctl[191], 0xf, 12 - 10); 1396 clrbits_le32(&denali_ctl[190], 1397 (0x3 << 16) | (0x7 << 24)); 1398 /*PI_199 PI_COL_DIFF:RW:0:4*/ 1399 clrsetbits_le32(&denali_pi[199], 0xf, 12 - 10); 1400 /*PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2*/ 1401 clrbits_le32(&denali_pi[155], 1402 (0x3 << 16) | (0x7 << 24)); 1403 writel(1 | (1 << 8), &ddr_msch_regs->ddrconf); 1404 /* set max cs0 size */ 1405 writel((4096 / 32) | ((0 / 32) << 8), 1406 &ddr_msch_regs->ddrsize); 1407 1408 *prow = 16; 1409 *pbank = 3; 1410 *pcol = (bw == 2) ? 10 : 11; 1411 } 1412 1413 static u64 dram_detect_cap(struct dram_info *dram, 1414 struct rk3399_sdram_params *sdram_params, 1415 unsigned char channel) 1416 { 1417 const struct chan_info *chan = &dram->chan[channel]; 1418 struct sdram_cap_info *cap_info = &sdram_params->ch[channel].cap_info; 1419 u32 bw; 1420 u32 col_tmp; 1421 u32 bk_tmp; 1422 u32 row_tmp; 1423 u32 cs0_cap; 1424 u32 training_flag; 1425 u32 ddrconfig; 1426 1427 /* detect bw */ 1428 bw = 2; 1429 dram_set_bw(chan, bw); 1430 cap_info->bw = bw; 1431 if (data_training(chan, channel, sdram_params, PI_READ_GATE_TRAINING)) { 1432 bw = 1; 1433 dram_set_bw(chan, 1); 1434 cap_info->bw = bw; 1435 if (data_training(chan, channel, sdram_params, 1436 PI_READ_GATE_TRAINING)) { 1437 printf("16bit error!!!\n"); 1438 goto error; 1439 } 1440 } 1441 1442 /* 1443 * LPDDR3 CA training msut be trigger before other training. 1444 * DDR3 is not have CA training. 1445 */ 1446 if (sdram_params->base.dramtype == LPDDR3) 1447 training_flag = PI_WRITE_LEVELING; 1448 else 1449 training_flag = PI_FULL_TRAINING; 1450 1451 if (sdram_params->base.dramtype != LPDDR4) { 1452 if (data_training(chan, channel, sdram_params, training_flag)) { 1453 printf("full training error!!!\n"); 1454 goto error; 1455 } 1456 } 1457 1458 /* detect col */ 1459 dram_set_max_col(chan, bw, &col_tmp); 1460 if (sdram_detect_col(cap_info, col_tmp) != 0) 1461 goto error; 1462 1463 /* detect bank */ 1464 dram_set_max_bank(chan, bw, &bk_tmp, &col_tmp); 1465 sdram_detect_bank(cap_info, col_tmp, bk_tmp); 1466 1467 /* detect row */ 1468 dram_set_max_row(chan, bw, &row_tmp, &bk_tmp, &col_tmp); 1469 if (sdram_detect_row(cap_info, col_tmp, bk_tmp, row_tmp) != 0) 1470 goto error; 1471 1472 /* detect row_3_4 */ 1473 sdram_detect_row_3_4(cap_info, col_tmp, bk_tmp); 1474 1475 /* set ddrconfig */ 1476 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + cap_info->bk + 1477 cap_info->bw - 20)); 1478 if (cap_info->row_3_4) 1479 cs0_cap = cs0_cap * 3 / 4; 1480 1481 cap_info->cs1_row = cap_info->cs0_row; 1482 set_memory_map(chan, channel, sdram_params); 1483 ddrconfig = calculate_ddrconfig(sdram_params, channel); 1484 if (-1 == ddrconfig) 1485 goto error; 1486 set_ddrconfig(chan, sdram_params, channel, 1487 cap_info->ddrconfig); 1488 1489 /* detect cs1 row */ 1490 sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype); 1491 1492 /* detect die bw */ 1493 sdram_detect_dbw(cap_info, sdram_params->base.dramtype); 1494 1495 return 0; 1496 error: 1497 return (-1); 1498 } 1499 1500 static int sdram_init(struct dram_info *dram, 1501 struct rk3399_sdram_params *sdram_params) 1502 { 1503 unsigned char dramtype = sdram_params->base.dramtype; 1504 unsigned int ddr_freq = sdram_params->base.ddr_freq; 1505 int channel; 1506 u32 rank; 1507 int ch; 1508 u32 tmp; 1509 u32 training_flag; 1510 1511 debug("Starting SDRAM initialization...\n"); 1512 1513 if ((dramtype == DDR3 && ddr_freq > 933) || 1514 (dramtype == LPDDR3 && ddr_freq > 933) || 1515 (dramtype == LPDDR4 && ddr_freq > 800)) { 1516 debug("SDRAM frequency is to high!"); 1517 return -E2BIG; 1518 } 1519 1520 /* detect rank */ 1521 for (ch = 0; ch < 2; ch++) { 1522 sdram_params->ch[ch].cap_info.rank = 2; 1523 for (rank = 2; rank != 0; rank--) { 1524 for (channel = 0; channel < 2; channel++) { 1525 const struct chan_info *chan = 1526 &dram->chan[channel]; 1527 struct rk3399_cru *cru = dram->cru; 1528 struct rk3399_ddr_publ_regs *publ = chan->publ; 1529 1530 phy_pctrl_reset(cru, channel); 1531 phy_dll_bypass_set(publ, ddr_freq); 1532 if (pctl_cfg(chan, channel, sdram_params) != 0) 1533 printf("pctl_cfg fail\n"); 1534 } 1535 1536 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */ 1537 if (dramtype == LPDDR3) 1538 udelay(10); 1539 1540 tmp = (rank == 2) ? 3 : 1; 1541 dram_set_cs(&dram->chan[ch], tmp, 2048, 1542 sdram_params->base.dramtype); 1543 sdram_params->ch[ch].cap_info.rank = rank; 1544 /* 1545 * LPDDR3 CA training msut be trigger before 1546 * other training. 1547 * DDR3 is not have CA training. 1548 * LPDDR4 need confirm here! 1549 */ 1550 if (sdram_params->base.dramtype == LPDDR3) 1551 training_flag = PI_CA_TRAINING | 1552 PI_READ_GATE_TRAINING; 1553 else 1554 training_flag = PI_READ_GATE_TRAINING; 1555 if (!(data_training(&dram->chan[ch], ch, sdram_params, 1556 training_flag))) 1557 break; 1558 } 1559 sdram_params->ch[ch].cap_info.rank = rank; 1560 } 1561 1562 sdram_params->base.num_channels = 0; 1563 for (channel = 0; channel < 2; channel++) { 1564 const struct chan_info *chan = &dram->chan[channel]; 1565 struct sdram_cap_info *cap_info = 1566 &sdram_params->ch[channel].cap_info; 1567 1568 if (cap_info->rank == 0) { 1569 clear_channel_params(sdram_params, 1); 1570 continue; 1571 } else { 1572 sdram_params->base.num_channels++; 1573 } 1574 1575 printf("Channel "); 1576 printf(channel ? "1: " : "0: "); 1577 1578 if (channel == 0) 1579 set_ddr_stride(dram->pmusgrf, 0x17); 1580 else 1581 set_ddr_stride(dram->pmusgrf, 0x18); 1582 1583 if (dram_detect_cap(dram, sdram_params, channel)) { 1584 printf("Cap error!\n"); 1585 continue; 1586 } 1587 1588 sdram_print_ddr_info(cap_info, &sdram_params->base, 0); 1589 set_memory_map(chan, channel, sdram_params); 1590 cap_info->ddrconfig = 1591 calculate_ddrconfig(sdram_params, channel); 1592 if (-1 == cap_info->ddrconfig) { 1593 printf("no ddrconfig find, Cap not support!\n"); 1594 continue; 1595 } 1596 set_ddrconfig(chan, sdram_params, channel, cap_info->ddrconfig); 1597 set_cap_relate_config(chan, sdram_params, channel); 1598 } 1599 1600 sdram_params->base.stride = calculate_stride(sdram_params); 1601 dram_all_config(dram, sdram_params); 1602 switch_to_phy_index1(dram, sdram_params); 1603 1604 debug("Finish SDRAM initialization...\n"); 1605 return 0; 1606 } 1607 1608 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev) 1609 { 1610 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1611 struct rockchip_dmc_plat *plat = dev_get_platdata(dev); 1612 int ret; 1613 1614 ret = dev_read_u32_array(dev, "rockchip,sdram-params", 1615 (u32 *)&plat->sdram_params, 1616 sizeof(plat->sdram_params) / sizeof(u32)); 1617 if (ret) { 1618 printf("%s: Cannot read rockchip,sdram-params %d\n", 1619 __func__, ret); 1620 return ret; 1621 } 1622 ret = regmap_init_mem(dev, &plat->map); 1623 if (ret) 1624 printf("%s: regmap failed %d\n", __func__, ret); 1625 1626 #endif 1627 return 0; 1628 } 1629 1630 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1631 static int conv_of_platdata(struct udevice *dev) 1632 { 1633 struct rockchip_dmc_plat *plat = dev_get_platdata(dev); 1634 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; 1635 int ret; 1636 1637 ret = regmap_init_mem_platdata(dev, dtplat->reg, 1638 ARRAY_SIZE(dtplat->reg) / 2, 1639 &plat->map); 1640 if (ret) 1641 return ret; 1642 1643 return 0; 1644 } 1645 #endif 1646 1647 static int rk3399_dmc_init(struct udevice *dev) 1648 { 1649 struct dram_info *priv = dev_get_priv(dev); 1650 struct rockchip_dmc_plat *plat = dev_get_platdata(dev); 1651 int ret; 1652 #if !CONFIG_IS_ENABLED(OF_PLATDATA) 1653 struct rk3399_sdram_params *params = &plat->sdram_params; 1654 #else 1655 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; 1656 struct rk3399_sdram_params *params = 1657 (void *)dtplat->rockchip_sdram_params; 1658 1659 ret = conv_of_platdata(dev); 1660 if (ret) 1661 return ret; 1662 #endif 1663 1664 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); 1665 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 1666 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); 1667 priv->pmucru = rockchip_get_pmucru(); 1668 priv->cru = rockchip_get_cru(); 1669 priv->chan[0].pctl = regmap_get_range(plat->map, 0); 1670 priv->chan[0].pi = regmap_get_range(plat->map, 1); 1671 priv->chan[0].publ = regmap_get_range(plat->map, 2); 1672 priv->chan[0].msch = regmap_get_range(plat->map, 3); 1673 priv->chan[1].pctl = regmap_get_range(plat->map, 4); 1674 priv->chan[1].pi = regmap_get_range(plat->map, 5); 1675 priv->chan[1].publ = regmap_get_range(plat->map, 6); 1676 priv->chan[1].msch = regmap_get_range(plat->map, 7); 1677 1678 debug("con reg %p %p %p %p %p %p %p %p\n", 1679 priv->chan[0].pctl, priv->chan[0].pi, 1680 priv->chan[0].publ, priv->chan[0].msch, 1681 priv->chan[1].pctl, priv->chan[1].pi, 1682 priv->chan[1].publ, priv->chan[1].msch); 1683 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, 1684 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); 1685 #if CONFIG_IS_ENABLED(OF_PLATDATA) 1686 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); 1687 #else 1688 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); 1689 #endif 1690 if (ret) { 1691 printf("%s clk get failed %d\n", __func__, ret); 1692 return ret; 1693 } 1694 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); 1695 if (ret < 0) { 1696 printf("%s clk set failed %d\n", __func__, ret); 1697 return ret; 1698 } 1699 ret = sdram_init(priv, params); 1700 if (ret < 0) { 1701 printf("%s DRAM init failed%d\n", __func__, ret); 1702 return ret; 1703 } 1704 1705 return 0; 1706 } 1707 #endif 1708 1709 static int rk3399_dmc_probe(struct udevice *dev) 1710 { 1711 #ifdef CONFIG_TPL_BUILD 1712 if (rk3399_dmc_init(dev)) 1713 return 0; 1714 #else 1715 struct dram_info *priv = dev_get_priv(dev); 1716 1717 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 1718 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); 1719 priv->info.base = CONFIG_SYS_SDRAM_BASE; 1720 priv->info.size = rockchip_sdram_size( 1721 (phys_addr_t)&priv->pmugrf->os_reg2); 1722 #ifdef CONFIG_SPL_BUILD 1723 struct ddr_param ddr_parem; 1724 1725 ddr_parem.count = 1; 1726 ddr_parem.para[0] = priv->info.base; 1727 ddr_parem.para[1] = priv->info.size; 1728 rockchip_setup_ddr_param(&ddr_parem); 1729 #endif 1730 1731 #endif 1732 return 0; 1733 } 1734 1735 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info) 1736 { 1737 struct dram_info *priv = dev_get_priv(dev); 1738 1739 *info = priv->info; 1740 1741 return 0; 1742 } 1743 1744 static struct ram_ops rk3399_dmc_ops = { 1745 .get_info = rk3399_dmc_get_info, 1746 }; 1747 1748 static const struct udevice_id rk3399_dmc_ids[] = { 1749 { .compatible = "rockchip,rk3399-dmc" }, 1750 { } 1751 }; 1752 1753 U_BOOT_DRIVER(dmc_rk3399) = { 1754 .name = "rockchip_rk3399_dmc", 1755 .id = UCLASS_RAM, 1756 .of_match = rk3399_dmc_ids, 1757 .ops = &rk3399_dmc_ops, 1758 #ifdef CONFIG_TPL_BUILD 1759 .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata, 1760 #endif 1761 .probe = rk3399_dmc_probe, 1762 .priv_auto_alloc_size = sizeof(struct dram_info), 1763 #ifdef CONFIG_TPL_BUILD 1764 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat), 1765 #endif 1766 }; 1767